CN103390560A - Forming method of semiconductor device and semiconductor device - Google Patents
Forming method of semiconductor device and semiconductor device Download PDFInfo
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- CN103390560A CN103390560A CN2013103177244A CN201310317724A CN103390560A CN 103390560 A CN103390560 A CN 103390560A CN 2013103177244 A CN2013103177244 A CN 2013103177244A CN 201310317724 A CN201310317724 A CN 201310317724A CN 103390560 A CN103390560 A CN 103390560A
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Abstract
The invention provides a forming method of a semiconductor device and the semiconductor device. The forming method of the semiconductor device comprises the steps as follows: a substrate is provided; at least two parallelly arranged grid electrodes are formed on the surface of the substrate; each grid electrode comprises multiple sections; multiple sections of grooves are formed between every two adjacent grid electrodes; the ratio of the depth to the width of at least one section of groove is larger than or equal to 1; side walls are formed around the grid electrodes; source electrodes and drain electrodes are formed in the substrate on two sides of each side wall; after the source electrodes and the drain electrodes are formed, interlayered dielectric layers are formed in the surface of the substrate and the surfaces of the grid electrodes. With the adoption of the forming method, stray capacitance between the grid electrodes and the source electrodes and between the grid electrodes and the drain electrodes can be reduced, and the performance of the semiconductor device is improved.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of formation method and semiconductor device of semiconductor device.
Background technology
In semiconductor device, usually form parasitic capacitance between grid and source electrode, grid and drain electrode.This parasitic capacitance can affect the performance of semiconductor device, for example, can affect the speed of service of semiconductor device.Therefore, in semiconductor device, wish that the parasitic capacitance that forms between grid and source electrode, grid and drain electrode is the smaller the better.And for some semiconductor device application when the radio circuit, require harsher to the parasitic capacitance between grid and source electrode, grid and drain electrode.
The formation method of semiconductor device of the prior art comprises:
With reference to reference to figure 1 and Fig. 2, substrate 100 is provided, form at least two grids 101 on substrate 100, form side wall 102 around grid 101, form source electrode and drain electrode (not shown) in the substrate of side wall 102 both sides.
Afterwards, form silicon dioxide layer 103, cover substrate 100 with and the upper structure that forms, then silicon dioxide layer 103 is carried out graphically, form contact hole (contact) in silicon dioxide layer 103, the filled conductive material forms gate contact connector 105, source electrode contact plunger 104 and drain electrode contact plunger 106 in contact hole, is electrically connected to grid 101, source electrode and drain electrode respectively.
But in prior art, the parasitic capacitance between the grid in the semiconductor device of formation and source electrode, grid and drain electrode is larger.
More methods of formation about semiconductor device please refer to the United States Patent (USP) that publication number is US2011/0018091A1.
Summary of the invention
The problem that the present invention solves is that grid and the parasitic capacitance between source electrode, grid and drain electrode in the semiconductor device that forms of prior art is larger.
For addressing the above problem, the invention provides a kind of formation method of semiconductor device, comprise: substrate is provided, form at least two grids that are arranged in parallel at described substrate surface, each described grid comprises multistage, have the multistage groove between adjacent two grids, the depth-to-width ratio of at least one section groove is more than or equal to 1;
Form side wall around described grid;
Form source electrode and drain electrode in the substrate of described side wall both sides;
After forming described source electrode and drain electrode, at described substrate surface and gate surface, form interlayer dielectric layer.
Optionally, at described substrate surface, form in the technique of at least two grids, also form the line that described at least two grids are electrically connected to, the material of described line is identical with the material of described grid.
Optionally, the depth-to-width ratio of at least one section groove is less than 1, described source electrode or drain electrode in described depth-to-width ratio less than 1 beneath trenches.
Optionally, the material of described interlayer dielectric layer is SiO
2, the formation method of described interlayer dielectric layer is that plasma strengthens the tetraethoxysilane deposition.
Optionally, described side wall comprises the silicon nitride side wall, after forming the step of described source electrode and drain electrode, before the step of described substrate surface and gate surface formation interlayer dielectric layer, also comprises step:
Remove described silicon nitride side wall.
Optionally, described semiconductor device is to refer to gate transistor more.
The present invention also provides a kind of semiconductor device, comprising:
Substrate, be positioned at least two grids that are arranged in parallel of described substrate surface, and each described grid comprises multistage, has the multistage groove between adjacent two grids, and the depth-to-width ratio of at least one section groove is more than or equal to 1;
Be positioned at described grid side wall on every side, source electrode and drain electrode in the substrate of described side wall both sides;
Fill the interlayer dielectric layer of described multistage groove, the described substrate of covering and described gate surface, have space in described interlayer dielectric layer.
Optionally, described grid is electrically connected to by line, and the material of described line is identical with the material of grid.
Optionally, the depth-to-width ratio of at least one section groove is less than 1, described source electrode or drain electrode in described depth-to-width ratio less than 1 beneath trenches.
Optionally, described semiconductor device is to refer to gate transistor more.
Compared with prior art, technical scheme of the present invention has the following advantages:
in the technical program, form at least two grids that are arranged in parallel at described substrate surface, each grid comprises multistage, has the multistage groove between adjacent two grids, the depth-to-width ratio of at least one section groove is more than or equal to 1, form interlayer dielectric layer at described substrate surface and gate surface, can form larger air-gap in interlayer dielectric layer in this groove, make grid and source electrode, the dielectric constant of the material between grid and drain electrode obviously reduces, thereby grid and source electrode have been reduced, parasitic capacitance between grid and drain electrode, improved the performance of the whole semiconductor device of follow-up formation.When this semiconductor device application is in radio circuit, can obviously reduce the parasitic capacitance between grid and source electrode, grid and drain electrode.
Description of drawings
Fig. 1 is the planar structure schematic diagram of the semiconductor device of prior art;
Fig. 2 is the local amplification profile structural representation of Fig. 1 along the AA direction;
Fig. 3 is the planar structure schematic diagram of the grid of the specific embodiment of the invention;
Fig. 4 is the part section structural representation of the oval delineation of Fig. 3 zone along the BB direction;
Fig. 5 is the part section structural representation of the oval delineation of Fig. 3 zone along the CC direction;
Fig. 6 is the grid of the specific embodiment of the invention and the planar structure schematic diagram of side wall;
Fig. 7 is the part section structural representation of Fig. 6 along the BB direction;
Fig. 8 is the planar structure schematic diagram of the semiconductor device of the specific embodiment of the invention;
Fig. 9 is the part section structural representation of Fig. 8 along the BB direction;
Figure 10 is the part section structural representation of Fig. 8 along the CC direction.
Embodiment
Cause larger former of grid in semiconductor device and the parasitic capacitance between source electrode, grid and drain electrode because:
The parasitic capacitance that forms between grid and source electrode, grid and drain electrode comprises sidewall capacitance and overlap capacitance.Wherein, gate bottom and source electrode, gate bottom and drain electrode have overlapping region, and the electric capacity of this overlapping region is overlap capacitance.In the gate lateral wall direction, the electric capacity between grid and source electrode, grid and drain electrode is sidewall capacitance.With reference to figure 2, the pole plate of sidewall capacitance is grid 101 and source electrode, is perhaps grid 101 and drain electrode.Material between this pole plate is mainly silicon dioxide layer 103 and side wall 102.In prior art, silicon dioxide layer 103 is very fine and close, and the dielectric constant of fine and close silicon dioxide layer 103 is larger than the dielectric constant of fine and close not silicon dioxide layer, thereby makes the dielectric constant K of material between pole plate larger, and then makes the sidewall capacitance C between grid and source electrode, grid and drain electrode
SidewallLarger, in the situation that overlap capacitance is constant, the parasitic capacitance between grid and source electrode, grid and drain electrode is also larger, affects transistorized performance.
The inventor, through creative work, obtains a kind of formation method of semiconductor device.
, for above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.When the embodiment of the present invention was described in detail in detail, for ease of explanation, schematic diagram can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of the invention at this.
With reference to figure 3 and Fig. 4, Fig. 5, substrate 200 is provided, form at least two grids that are arranged in parallel 201 on described substrate 200 surfaces, each described grid 201 comprises multistage, has the multistage groove between adjacent two grids, the depth-to-width ratio of at least one section groove is more than or equal to 1.
In specific embodiment, the material of described substrate 200 can be monocrystalline silicon (Si), monocrystalline germanium (Ge) or SiGe (GeSi), carborundum (SiC); Can be also silicon-on-insulator (SOI), germanium on insulator (GOI); Perhaps can also be for other material, such as the III such as GaAs-V compounds of group.
With reference to figure 3 to Fig. 5, substrate 200 surfaces form at least two grids that are arranged in parallel 201, every grid 201 comprises five sections, is respectively first paragraph grid 2011, second segment grid 2012, the 3rd section grid 2013, the 4th section grid 2014 and the 5th section grid 2015.Has the multistage groove between adjacent grid 201, has the depth-to-width ratio of one section groove at least more than or equal to 1 in this multistage groove, in the present embodiment, the depth-to-width ratio of the groove 205 that forms between the 3rd section grid 2013 of adjacent grid 201 more than or equal to 1(with reference to figure 4).The depth-to-width ratio that has one section groove at least in multistage groove between adjacent grid 201, less than 1, in the present embodiment, forms groove 206(with reference to figure 5 between the 5th section grid 2015 of neighboring gates), the depth-to-width ratio of groove 206 is less than 1.The depth-to-width ratio of the groove that forms between the 4th section grid 2014 of neighboring gates 201, between second segment grid 2012 and between first paragraph grid 2011 is also less than 1.
The depth-to-width ratio that has one section groove 205 at least between neighboring gates 201 is more than or equal to 1, just can guarantee in follow-up interlayer dielectric layer in groove 205 to have the larger and a fairly large number of air-gap of volume.And while making semiconductor device of the present invention, the depth-to-width ratio of the above-mentioned groove 205 between neighboring gates 201 is larger, and the volume of the air-gap of formation can be larger, and the quantity of air-gap can be more.
Need to prove, the depth-to-width ratio of the above-mentioned groove 205 between neighboring gates 201 was more than or equal to 1 o'clock, distance between the 3rd section grid 2013 on these groove 205 both sides is too near, exceed photoetching process and formed accuracy rating with source electrode 211 or 210 contact holes that are connected that drain, can't be in depth-to-width ratio more than or equal to groove 205 places' formation source electrodes 211 of 1 or 210 the contact hole of draining.Therefore, in the present embodiment,, with reference to figure 3 and Fig. 5, at least also comprise depth-to-width ratio between adjacent two grids less than one section groove 206 of 1, source electrode 211 is follow-up be formed on this groove 206 below.Distant between the 5th section grid 2015 of the grid 201 of these groove 206 both sides, can be at the interior formation contact hole of the interlayer dielectric layer 203 at these groove 206 places, then, can form contact plunger (with reference to figure 8 and Figure 10) by the filled conductive material in contact hole.
In the present embodiment, be electrically connected to by line 207 between grid.What be electrically connected to act as: the depth-to-width ratio of the groove 205 between grid was more than or equal to 1 o'clock, and the distance between the 3rd section grid 2013 of grid is very little, makes between the 3rd section grid 2013 and produces parasitic capacitance.In the present embodiment, after grid is electrically connected to by line 207, make the current potential of each grid equate, at this moment, just can not produce parasitic capacitance between the 3rd section grid 2013 of the grid that distance is very little.
In the present embodiment, line 207 is with grid 201 parallel connections, and the semiconductor device of follow-up formation is to refer to gate transistor (multi-finger transisitors) more.That is to say, refer to that gate transistor is to be formed in parallel by a plurality of transistors, be specially: the source electrode of grid one side is carried out parallel connection, and parallel connection is carried out in the drain electrode of grid opposite side more, grid carries out parallel connection by line 207, and many fingers gate transistor of formation can increase drive current.
In other embodiments, within line 207 also belonged to the scope of protection of the invention with grid 201 series connection, the semiconductor device of follow-up formation was the device that a plurality of transistor series form.Be specially the source electrode of grid one side is connected with the drain electrode of neighboring gates.
In the present embodiment, the method that forms grid 201 and line 207 on substrate 200 surfaces is as follows: on substrate 200 surfaces, form polysilicon layer.Form patterned mask layer on polysilicon layer, the shape of definition grid and line and distribution, take described patterned mask layer as the mask etching polysilicon layer, form grid 201 on the surface of substrate 200, also formed line 207 simultaneously.
Need to prove, in the present embodiment, patterned mask layer is preferably photoresist, and reason is as follows: in subsequent technique, metal silicide has the mask layer of removing top portions of gates and the step that forms metal silicide at the top of grid, because can reduce the contact resistance of top portions of gates.In the present embodiment, photoresist is removed easily, and the processing step of removal is fairly simple, and removal effect is relatively good, is difficult for forming residual.In other embodiments, patterned mask layer can be the hard mask materials such as boron nitride, and still, the process of removing this hard mask is complicated more than the process of removing photoresist, and technology difficulty is larger.
With reference to figure 6 and Fig. 7, form side wall 202 around described grid 201, form source electrode 211 and drain electrode 210 in the substrate of described side wall 202 both sides.
In the present embodiment, side wall 202 is the three-decker (not shown), and nexine is monox lateral wall, and intermediate layer is the silicon nitride side wall, and skin is monox lateral wall.
Then, form source electrode 211 and drain electrode 210 in the substrate of described side wall 202 both sides, the method that wherein forms source electrode 211 and drain electrode 210 is known technology for those skilled in the art, does not repeat them here.
Need to prove, the silicon nitride side wall in side wall 202 is also grid 201 and source electrode 211, grid 201 and the material between 210 of draining, and its dielectric constant is higher than monox lateral wall, also higher than the dielectric constant of the interlayer dielectric layer that forms in subsequent technique.Therefore, in the subsequent technique of the present embodiment, after forming source electrode 211 and drain electrode 210 steps, after the mission that is to say side wall 202 is completed, in order further to reduce grid 201 and source electrode 211, grid 201 and the sidewall capacitance between 210 of draining, the silicon nitride side wall can be removed, so that the reduced dielectric constant of grid 201 and source electrode 211, grid 201 and the material between 210 of draining.In the present embodiment, also have monox lateral wall around the silicon nitride side wall, therefore need first monox lateral wall to be removed, and then remove the silicon nitride side wall.
In other embodiments, side wall is single layer structure.The material of side wall is silicon nitride.After the mission of side wall is completed,, in order further to reduce the sidewall capacitance between grid and source electrode, grid and drain electrode, can directly the silicon nitride side wall be removed.
In other embodiments, the material of side wall is double-decker.Nexine is the silicon nitride side wall, and skin is monox lateral wall.After the mission of side wall is completed,, in order further to reduce the sidewall capacitance between grid and source electrode, grid and drain electrode, can first monox lateral wall be removed, then the silicon nitride side wall is removed.
, with reference to figure 8, after forming described source electrode 211 and drain electrode 210, on described substrate 200 surfaces and grid 201 surfaces, form interlayer dielectric layer 203.
The method that forms interlayer dielectric layer 203 is chemical vapour deposition (CVD) (Chemical Vapor Deposition, CVD).In the present embodiment, the material of interlayer dielectric layer 203 is silicon dioxide.The formation method of interlayer dielectric layer 203 is that plasma strengthens tetraethoxysilane deposition (PE-TEOS, Plasma Enhanced TEOS), and the filling capacity of the interlayer dielectric layer 203 that the method forms is bad.When adopting the method filling groove 205, due to the depth-to-width ratio of groove 205,, more than or equal to 1, therefore, can form air-gap 204 groove 205 is interior, and air-gap 204 volumes that form are large and quantity is many.When making semiconductor device of the present invention, the depth-to-width ratio of the groove between at least one section grid of neighboring gates is larger, and the volume of the air-gap of formation can be larger, and the quantity of air-gap can be more.In the present embodiment, because the dielectric constant of vacuum is minimum, the air-gaps 204 more than the large and quantity of volume can reduce the K value of interlayer dielectric layer 203 greatly, thereby can reduce the dielectric constant of material between pole plate, and then can reduce sidewall capacitance C
Sidewall, reduce the parasitic capacitance that forms between grid 201 and source electrode, grid 201 and drain electrode.When this semiconductor device application is in radio circuit, can obviously reduce the parasitic capacitance between grid and source electrode, grid and drain electrode.
Need to prove, the present invention is not suitable for adopting (the BPSG of deposition boron phosphoric acid glass, boro-phospho-sillicate-glass) method and high-density plasma (HDP, high density plasma) method forms interlayer dielectric layer 203, because, the filling capacity of the interlayer dielectric layer 203 that these two kinds of methods form is good, even the filling depth-to-width ratio can not form air-gap more than or equal to 1 groove 205 yet in groove 205.
In other embodiments, the material of described interlayer dielectric layer can also be low-K dielectric material or ultralow K dielectric material.Described low-K dielectric material is SiOF, SiCOH, SiO, SiCO or SiCON.Described ultralow K dielectric material is black diamond.
Need to prove, if the material of interlayer dielectric layer adopts low-K dielectric material or ultralow K dielectric material, also can reduce the parasitic capacitance between grid and source electrode, grid and drain electrode, but some low-K dielectric material after all, especially ultralow K dielectric material cost is higher, and not universal at present.So technical scheme of the present invention, not only can significantly reduce the dielectric constant of material between grid and source electrode, grid and drain electrode, can obviously reduce accordingly the parasitic capacitance between grid and source electrode, grid and drain electrode, but also can reduce production costs greatly.Certainly, in other embodiments, the material of interlayer dielectric layer is the low-K dielectric material, and the depth-to-width ratio between two adjacent grids also is applicable to the present invention more than or equal to the technique that forms air-gap in the low-K dielectric material in 1 groove, although cost is high, the effect that reduces the parasitic capacitance between grid and source electrode, grid and drain electrode can be better.Those skilled in the art can select according to the technique of reality.
What need to go on to say is in other embodiments, after forming interlayer dielectric layer, also to comprise: form the interconnection structure that described at least two grids are electrically connected in described interlayer dielectric layer.
In conjunction with reference to Fig. 8 to Figure 10, the present invention also provides a kind of semiconductor device, comprising:
Be positioned at described grid 201 side wall 202 on every side, source electrode and drain electrode in described side wall 202 both sides substrates;
Fill described multistage groove, cover the interlayer dielectric layer 203 on described substrate 200 and described grid 201 surfaces, have space 204 in described interlayer dielectric layer 203.
Wherein, described grid 201 is electrically connected to by line 207, and the material of described line 207 is identical with the material of grid.
In the present embodiment, groove 205(is with reference to figure 4) be to be formed by the 3rd section adjacent grid 2013.
In other embodiments, also comprise between the neighboring gates 201 of semiconductor device of the present invention at least one section depth-to-width ratio less than 1 groove 206(with reference to figure 5), groove 206 is to be formed by the 5th section adjacent grid 2015.Source electrode or drain electrode in described depth-to-width ratio less than 1 beneath trenches.
In other embodiments, the material of interlayer dielectric layer 203 is low-K dielectric material or ultralow K dielectric material.
In other embodiments, the material of described interlayer dielectric layer is SiO
2, SiOF, SiCOH, SiO, SiCO, SiCON or black diamond.
In the present embodiment, described semiconductor device is to refer to gate transistor more.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not break away from technical solution of the present invention;, to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (10)
1. the formation method of a semiconductor device, is characterized in that, comprising:
Substrate is provided, at described substrate surface, forms at least two grids that are arranged in parallel, each described grid comprises multistage, has the multistage groove between adjacent two grids, and the depth-to-width ratio of at least one section groove is more than or equal to 1;
Form side wall around described grid;
Form source electrode and drain electrode in the substrate of described side wall both sides;
After forming described source electrode and drain electrode, at described substrate surface and gate surface, form interlayer dielectric layer.
2. formation method as claimed in claim 1, is characterized in that, at described substrate surface, forms in the technique of at least two grids, also forms the line that described at least two grids are electrically connected to, and the material of described line is identical with the material of described grid.
3. formation method as claimed in claim 1, is characterized in that, the depth-to-width ratio of at least one section groove is less than 1, described source electrode or drain electrode in described depth-to-width ratio less than 1 beneath trenches.
4. formation method as claimed in claim 1, is characterized in that, the material of described interlayer dielectric layer is SiO
2, the formation method of described interlayer dielectric layer is that plasma strengthens the tetraethoxysilane deposition.
5. formation method as claimed in claim 1, is characterized in that, described side wall comprises the silicon nitride side wall, after forming the step of described source electrode and drain electrode, before the step of described substrate surface and gate surface formation interlayer dielectric layer, also comprises step:
Remove described silicon nitride side wall.
6. formation method as claimed in claim 1, is characterized in that, described semiconductor device is to refer to gate transistor more.
7. a semiconductor device, is characterized in that, comprising:
Substrate, be positioned at least two grids that are arranged in parallel of described substrate surface, and each described grid comprises multistage, has the multistage groove between adjacent two grids, and the depth-to-width ratio of at least one section groove is more than or equal to 1;
Be positioned at described grid side wall on every side, source electrode and drain electrode in the substrate of described side wall both sides;
Fill the interlayer dielectric layer of described multistage groove, the described substrate of covering and described gate surface, have space in described interlayer dielectric layer.
8. semiconductor device as claimed in claim 7, is characterized in that, described grid is electrically connected to by line, and the material of described line is identical with the material of grid.
9. semiconductor device as claimed in claim 7, is characterized in that, the depth-to-width ratio of at least one section groove is less than 1, described source electrode or drain electrode in described depth-to-width ratio less than 1 beneath trenches.
10. semiconductor device as claimed in claim 7, is characterized in that, described semiconductor device is to refer to gate transistor more.
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| US6238987B1 (en) * | 1999-09-13 | 2001-05-29 | United Microelectronics Corp. | Method to reduce parasitic capacitance |
| US20020127763A1 (en) * | 2000-12-28 | 2002-09-12 | Mohamed Arafa | Sidewall spacers and methods of making same |
| JP2002535849A (en) * | 1999-01-20 | 2002-10-22 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Method for forming voids in a dielectric material to reduce capacitance between interconnect lines |
| US20040232496A1 (en) * | 2003-05-21 | 2004-11-25 | Jian Chen | Use of voids between elements in semiconductor structures for isolation |
| CN101399222A (en) * | 2007-09-24 | 2009-04-01 | 台湾积体电路制造股份有限公司 | Manufacturing method for semiconductor elements having air gap |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002535849A (en) * | 1999-01-20 | 2002-10-22 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Method for forming voids in a dielectric material to reduce capacitance between interconnect lines |
| US6238987B1 (en) * | 1999-09-13 | 2001-05-29 | United Microelectronics Corp. | Method to reduce parasitic capacitance |
| US20020127763A1 (en) * | 2000-12-28 | 2002-09-12 | Mohamed Arafa | Sidewall spacers and methods of making same |
| US20040232496A1 (en) * | 2003-05-21 | 2004-11-25 | Jian Chen | Use of voids between elements in semiconductor structures for isolation |
| CN101399222A (en) * | 2007-09-24 | 2009-04-01 | 台湾积体电路制造股份有限公司 | Manufacturing method for semiconductor elements having air gap |
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