CN103389039A - High-speed and high-precision light curtain detection device based on FPGA (field programmable gate array) and FPAA (field programmable analog array) - Google Patents
High-speed and high-precision light curtain detection device based on FPGA (field programmable gate array) and FPAA (field programmable analog array) Download PDFInfo
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Abstract
The invention discloses a high-speed and high precision light curtain detection device based on an FPGA and an FPAA. The device comprises a light curtain emitter and a light curtain receiver, wherein infrared transmitting tubes are arranged on the light curtain emitter; receiving photocells are arranged on the light curtain receiver; the infrared transmitting tubes, as well as the receiving photocells, are distributed in double rows and staggered in a plane; and a system core of the light curtain emitter and the light curtain receiver is based on two types (FPGA/FPAA) of super-large-scale digital/analog integrated circuits, that is, by means of a site reconfigurable characteristic of the FPAA and a parallel processing characteristic of the FPGA, the FPAA preprocesses a light envelope signal, and then the FPGA performs real-time in-place detection and edge detection on an object. With the adoption of the technical scheme, the high-speed and high precision light curtain detection device has the advantages as follows: the data processing speed and the system response speed are high, interference resistance is high, and the upgrade is convenient; the device can be applied to various industrial severe environments, in particular to a deformed steel bar production line of a bar production factory in the metallurgical industry; and in-place detection and size measurement performed on tiny objects moving at high speeds can be realized.
Description
Technical field
The present invention relates to a kind ofly to small, high-speed moving object realize putting in place the light curtain system of detection, dimensional measurement, belong to the optical computing apparatus field.
Background technology
The light curtain is a kind of special correlation photoelectric sensor, comprises transmitter, receiver two parts.Transmitter along its length, drives an infrared tube every a determining deviation and sends a branch of infrared ray, has produced a carrier wave infrared array, and receiver arranges the photoelectric cell of equal number according to uniform distances.During work at first transmitter send light pulse and corresponding receiver is found this pulse simultaneously, namely complete the scanning of a passage after finding, then turn to next passage, until all scanning is all completed.After one-period scanning was completed, which passage of system log (SYSLOG) led to light, and which passage is blocked, thereby realized the function of monitoring and measurement object physical dimension.Tradition light curtain is widely used in the freeway toll station vehicle classification and detects the multiple occasions such as meter is heavy, elevator door switch is controlled, online accessory size detection, packing control.For example on the pressing equipment of the continuous material-feeding and fetching of needs,, if the contact safety protective door is installed, need operating personnel's switch protective door continually, cause increasing operating personnel's workload, reduce production efficiency.Installation light is behind the scenes, when operating personnel's material-feeding and fetching,, as long as any part blocking light of health is arranged, will cause machine to enter safe condition and can not bring injury to operating personnel.
At the metallurgical industry Bar Plant, new, higher requirement has been proposed light curtain detecting device.At finish rolling regional production line, square billet is after milling train, become the screw-thread steel of 200 meters of single length, movement velocity 15m/s, need to be cut to the screw-thread steel that four segment length are 50 meters specifications, if wait for after it stops and cutting, production efficiency can be very low, therefore to carry out position probing to the screw-thread steel of high-speed cruising, bob, and cut in real time standard specification.Existing common single beam optoelectronic switch can't meet beats and rate request, and traditional light curtain also, because the optical axis spacing is excessive, detection speed is excessively slow, can't detect the screw-thread steel of high-speed motion, diameter 10mm.
Number of patent application is to have provided " but light proscenia of the direct of travel of measuring vehicle, the number of axle and vehicle two-dimensional shapes " in 201210548649.8 document, it matches by many groups picking sensor, accurately detects the vehicle features such as vehicle direction of traffic and the number of axle, overall height, chassis height, side geometric profile.It is 10mm～100mm that the method makes the optical axis spacing of using up act transmitter and receiver, and accuracy of detection is not high, when inspected object, just can't detect during less than 15mm.
Number of patent application is to have provided " based on high precision position and posture detection method and the device of light veil type laser " in 200810116377.8 document, and take light veil type laser as detection means, the motion by displacement platform, rotation platform realizes that high precision detects.The method is used industrial computer, step motor control worktable, complex structure, processing difficulties.
Number of patent application is to have provided " the outer infrared light curtain protective device of elevator door " in 201210346209.4 document, and this light proscenia, take the Tiny26L single-chip microcomputer as core, is controlled infrared transmitting tube, receiving tube, possesses the infrared transmitting tube sleep mode.The method uses single-chip microcomputer to be control core, and detection speed is slower, more than the response time needs 100ms.
Summary of the invention
, for light proscenia above shortcomings in prior art, the invention provides a kind of light of high-speed, high precision based on FPGA and FPAA curtain pick-up unit.
Technical scheme of the present invention is:
A kind of light of high-speed, high precision based on FPGA and FPAA curtain pick-up unit, comprise light curtain transmitter and light curtain receiver, is provided with infrared transmitting tube on light curtain transmitter, is provided with the reception photoelectric cell on light curtain receiver.Described infrared transmitting tube and reception photoelectric cell are the staggered plane distribution of biserial; The system core of described light curtain transmitter and light curtain receiver is based on two kinds of ultra-large digital-to-analog integrated circuit of FPGA/FPAA: described light curtain transmitter drives infrared transmitting tube by the FPGA functional module and realizes the high-speed optical pulse emission; Described light curtain receiver is used for photoelectric cell is received that light signal is converted to faint electric signal, amplify by the amplifier signal, again after comparer output digit signals to the FPGA functional module, signal conditioning circuit adopts FPAA to realize the on-the-spot restructural of mimic channel, light curtain receiver, by the real-time reception of FPGA functional module gated sweep formula multi beam infrared light, realizes that putting in place of high-speed moving object detected and edge detects.
Further, the FPGA functional module in described light curtain transmitter comprises clock frequency division module, string and modular converter, loss of clock judging module, the initial generation module of light pulse, reliable light pulse output module, wherein:
The input clock CLK50M of clock frequency division module is from the active crystal oscillator of 50M, and its output terminal of clock JudgeCLK links the input end of clock of string and modular converter;
String and modular converter are used for the SerCLK signal is gone here and there and changed, and its input end of clock JudgeCLK is from clock frequency division module, and its data input pin is linked the input pin SerCLK of FPGA, output 8 bit parallel bus InCLKPara[7..0];
The bus input of loss of clock judging module is from the parallel data output InCLKPara[7..0 of string and modular converter], its output control signal SignCt;
The initial generation module of light pulse is for generation of the conducting control signal of 16 road infrared transmitting tubes, the input clock of the initial generation module of light pulse is SerCLK, incoming sync pulse is SerData, and the output signal of the initial generation module of light pulse is the conducting control signal LightTA[15..0 of 16 road infrared transmitting tubes];
The input signal that reliable light pulse output module forms is respectively from the LightTA[15..0 of the initial generation module of light pulse and loss of clock judging module] and SignCt, reliable light pulse output module judgement SignCt high-low level, thereby output LightTB[15..0] signal.
Further, FPGA functional module in described light curtain receiver comprises clock frequency division module, synchronizing pulse/data generation module, light signal synthesis module, the detection module that puts in place, edge detection module, digital communication and D/A transition drive signal generation module, wherein:
The input clock CLK50M of clock frequency division module is from the active crystal oscillator of 50M, its high-frequency clock output terminal CLKA links respectively the input end of clock of the detection module that puts in place, edge detection module, digital communication and D/A transition drive signal generation module, and another output terminal of clock LEDCLK of clock frequency division module links the input end of clock of synchronizing pulse/data generation module;
Synchronizing pulse/data generation module is for generation of clock SerCLK and the synchrodata SerData of synchronous communication between light curtain receiver and light curtain transmitter, and the input clock of synchronizing pulse/data generation module is that LEDCLK, frequency are 4.17MHz.
The light signal synthesis module is used for according to 16 tunnel light pulse digital signal Dig[15..0 from FPAA] and from clock SerCLK and the synchrodata SerData of synchronizing pulse/data generation module, adopt time-division multiplex technology, a synthetic road signal LightSign output that can represent 16 road photoelectric cell states.
The detection module that puts in place is used for according to the light pulse digital signal LightSign from the light signal synthesis module, from the clock CLKA of clock frequency division module with from clock SerCLK and the synchrodata SerData of synchronizing pulse/data generation module, judge whether moving object occurs, export a switching value signal SwitchOut;
The edge detection module is for detection of the front and rear side edge of moving object, and its input signal is identical with the input signal of the detection module that puts in place, output expression is initial, the data SPosi[10..0 of end position], EPosi[10..0];
Digital communication and D/A transition drive signal generation module are used for according to the SPosi[10..0 from the edge detection module] or EPosi[10..0], from the clock CLKA of clock frequency division module with from the synchrodata SerData of synchronizing pulse/data generation module, output can drive clock ComCLK and the data ComData of Interface for digital communication chip, and output can drive clock DACLK, data DAData and the latch signal DALatch of D/A conversion chip.
Further, the described detection module that puts in place comprises single beam start stop signal generation module, single beam judgement clock generating module, string and modular converter, data accumulation module, counting judge module, wherein:
The input signal of single beam start stop signal generation module is clock SerCLK and synchrodata SerData, take SerCLK as clock, SerData is reset signal, carry out mould 4 countings, produce count bus QA[1..0], and with SerCLK, QA[1], QA[0] three signals produce enabling signal EPulClr and the stop signal EPulLatch of single light pulse by combinational logic;
The input signal of single beam judgement clock generating module is high-frequency clock CLKA, clock SerCLK and synchrodata SerData, the judgement clock JudgeCLK of the single light pulse of output;
String and modular converter are used for the single light pulse to the LightSign signal and carry out 12 bit strings and conversion, its input end of clock JudgeCLK adjudicates clock generating module from single beam, data input pin is light pulse signal LightSign, outputting ten two bit parallel bus EPulData[11..0];
The input signal of data accumulation module is from single light pulse enabling signal EPulClr, the stop signal EPulLatch of single beam start stop signal generation module and from going here and there also 12 bit parallel bus EPulData[11..0 of modular converter], the output signal of data accumulation module is EPulFlag;
The input signal of counting judge module is synchrodata SerData and from the EPulFlag signal of data accumulation module, and the output signal of counting judge module is switching value control signal SwitchOut.
Further, described edge detection module comprises standard time clock generation module, standard time clock counting module, photo-impulses counting module, synchronous subtraction block, one period delay module, state machine judge module, wherein:
The input signal of standard time clock generation module is clock SerCLK and synchrodata SerData, take SerCLK as clock, SerData is reset signal, carries out mould 4 countings, produce count bus QA[1..0], its most significant digit QA[1] be exactly the output signal CalcuCLK of standard time clock generation module;
The input signal of standard time clock counting module is synchrodata SerData and from the CalcuCLK of standard time clock generation module, and take CalcuCLK as clock, SerData is reset signal, carries out mould 2048 countings, produces count bus CalCLKCount[10..0];
The input signal of photo-impulses counting module is synchrodata SerData and light signal LightSign, and take LightSign as clock, SerData is reset signal, carries out mould 2048 countings, produces count bus RecDataCount[10..0];
The input signal of synchronous subtraction block be from the standard time clock generation module CalcuCLK, from the count bus CalCLKCount[10..0 of standard time clock counting module], from the count bus RecDataCount[10..0 of photo-impulses counting module], when CalcuCLK signal negative edge, count bus is carried out subtraction, be SubValA[10..0]=CalCLKCount[10..0]-RecDataCount[10..0], SubValA[10..0 wherein] and be the output signal of synchronous subtraction block;
The input signal of one period delay module for from the CalcuCLK of standard time clock generation module, carry out the SubValA[10..0 of motor synchronizing subtraction block], postpone a CalcuCLK and produce the output signal SubValB[10..0 of one period delay module after the clock period];
The input signal of state machine judge module is the SubValA[10..0 that carrys out the motor synchronizing subtraction block] and from one period delay module SubValB[10..0], these two groups of bus states are judged: as SubValA[10..0]=1 the time, SPosi[10..0]=CalCLKCount[10..0], the anterior edge of expression object occurs, follows edge, judgment object rear portion; As SubValA[10..0]=SubValB[10..0] time, EPosi[10..0]=CalCLKCount[10..0] – 1; The output signal SPosi[10..0 of state machine judge module] and EPosi[10..0] be exactly the front and rear side edge of object.
The invention has the beneficial effects as follows:
In the present invention, the sensing element biserial plane distribution of interlocking, utilize the on-the-spot restructural characteristic of FPAA, the parallel behavior of FPGA, uses FPAA to the pre-service of light envelope signal, then carry out object by FPGA and put in place in real time and detect and the edge detection.Technique scheme makes the present invention have that data processing speed is high, system response time is fast, antijamming capability is strong, upgrading is convenient, can be used for various industrial rugged surroundings, be specially adapted to metallurgical industry Bar Plant screw-thread steel production line, can realize putting in place detection, dimensional measurement to small, high-speed moving object.
Description of drawings
Fig. 1 is the overall work schematic diagram of a kind of light of high-speed, high precision based on FPGA and FPAA of the present invention curtain pick-up unit;
Fig. 2 is the layout schematic diagram of sensor in the present invention;
Fig. 3 is the layout PCB pictorial diagram of sensor in the present invention;
Fig. 4 is the structural representation of FPGA functional module in light curtain transmitter in the present invention;
Fig. 5 is the system chart of light curtain receiver in Fig. 1;
Fig. 6 is FPAA signal conditioning circuit figure in Fig. 5;
Fig. 7 is the structural representation of FPGA functional module in light curtain receiver in the present invention;
Fig. 8 is the structural representation of detection module of putting in place in Fig. 7;
Fig. 9 is the structural representation of edge detection module in Fig. 7;
Figure 10 is the wave simulation figure that object edge detects.
In figure: 1, infrared transmitting tube or receiving tube; 2, receive the photoelectric cell pad.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in further detail.
A kind of light of high-speed, high precision based on FPGA and FPAA curtain pick-up unit, in this device, FPGA uses VHDL to describe in the Quartus Integrated Development Environment, partly be comprised of clock frequency division module, synchronizing pulse/data generation module, the detection module that puts in place, edge detection module etc., FPAA designs the signal conditioning circuits such as variable gain amplifier, comparer in the AnadigmDesigner2 Integrated Development Environment.
As shown in Figure 1, transmitter along its length, drives an infrared tube every a determining deviation and sends a branch of infrared ray the overall work situation of this device, has produced a carrier wave infrared array, and receiver arranges the photoelectric cell of equal number according to uniform distances.During work at first transmitter send light pulse and corresponding receiver is found this pulse simultaneously, namely complete the scanning of a passage after finding, then turn to next passage, until all scanning is all completed.After one-period scanning was completed, which passage of system log (SYSLOG) led to light, and which passage is blocked, thereby realized the function of monitoring and measurement object physical dimension.
The infrared transmitting tube of this device and reception photoelectric cell do not adopt traditional light curtain lineal layout form, but adopt the staggered plane distribution of biserial, have overcome like this restriction of sensor own vol, improve measuring accuracy.Infrared transmitting tube or receiving tube 1 and photoelectric cell are arranged (having marked the layout that receives photoelectric cell pad 2 in figure) as shown in Figure 2, this is that sensor is arranged schematic diagram, the explanation as an example of 16 roads example, sensor is arranged the PCB material object as shown in Figure 3, the middle two shinny places of row receive photronic pad exactly.
In this device, the built-in function of light curtain transmitter core chip FPGA as shown in Figure 4, is comprised of clock frequency division module, string and modular converter, loss of clock judging module, the initial generation module of light pulse, reliable light pulse output module.Wherein:
The major function of clock frequency division module is input 50M clock, the clock 4.17MHz after generation 12 frequency divisions.The input clock CLK50M of clock frequency division module is from the active crystal oscillator of 50M, and output terminal of clock JudgeCLK links the input end of clock of string and modular converter.Clock frequency division module is worked according to 50M crystal oscillator rising edge, rising edge of every appearance, and four count bus add one, are added to 11 rear count bus zero clearings, and the count bus most significant digit is exactly needed clock JudgeCLK.
JudgeCLK=CLK50M/12=4.17MHz
String and modular converter major function are that the SerCLK signal is gone here and there and changed, and its input end of clock JudgeCLK is from clock frequency division module, and data input pin is linked the input pin SerCLK of FPGA, output 8 bit parallel bus InCLKPara[7..0].String and modular converter are worked according to the JudgeCLK rising edge, rising edge of every appearance, give parallel bus InCLKPara[7..0 with SerCLK] lowest order, use simultaneously for circulation with InCLKPara[7..0] 8 bits of byte move to left one, realize string and translation function.
The bus input of loss of clock judging module is from the parallel data output InCLKPara[7..0 of string and modular converter], if judgement InCLKPara[7..0] be 0 or 255, communication line fault between light curtain transmitter and receiver is described, output control signal SignCt is 0, if proper communication, SignCt is 1.
The Main Function of above-mentioned three module clock frequency division modules, string and modular converter, loss of clock judging module is to judge whether the communication line between light curtain transmitter and receiver breaks down, if break down, close all infrared transmitting tubes, otherwise can cause electric current excessive, power valve damages.
The initial generation module effect of light pulse is the conducting control signal that produces 16 road infrared transmitting tubes, the input clock of the initial generation module of light pulse is SerCLK, frequency is 4.17MHz, incoming sync pulse is SerData, this signal is at instantaneous high level of initial appearance of per cycle, these two signals are to send transmitter by light curtain receiver to by telecommunication cable, and the output signal of the initial generation module of light pulse is the conducting control signal LightTA[15..0 of 16 road infrared transmitting tubes].
The course of work of the initial generation module of light pulse is described below: at first take SerCLK as clock, SerData is reset signal, and design stops pattern 256 counters, produces count bus CLKCount[7..0]; Next judge CLKCount[7..0] numerical value, as CLKCount[7..0]=1 the time, the conducting of first via infrared transmitting tube, as CLKCount[7..0]=5 the time, the second road infrared transmitting tube conducting, CLKCount[7..0] judgement numerical value constantly add four, by that analogy, produce the conducting control signal LightTA[15..0 of 16 road infrared transmitting tubes], can make between light pulse certain intervals is arranged like this, receiving photoelectric cell has time enough to discharge and recharge.
The input signal that reliable light pulse output module forms is LightTA[15..0] and SignCt, respectively from the initial generation module of light pulse and loss of clock judging module, reliable light pulse output module judgement SignCt high-low level, thereby output LightTB[15..0] signal.
As SignCt while being high, LightTB[15..0]=LightTA[15..0].
As SignCt when low, LightTB[15..0]=" 0,000 0,000 0,000 0000 ".
In this device, the system chart of light curtain receiver ，Yi16 road receiver as shown in Figure 5 is example,, for realizing opto-electronic conversion, the negative pole of photoelectric cell L1 be linked+the 5V power supply, and positive pole is linked resistance R 1, another pin ground connection of R1.Photronic positive pole is exactly the ultra-weak electronic signal Ana1 by light signal generating, other 15 road photoelectric cell methods of attachment are identical, and 16 road signal Ana1～Ana16 of photoelectric cell output are very faint, only have tens millivolts, therefore need to it be amplified with operational amplifier.Because the photoelectric cell way is too much, while especially arriving individual plates 64 tunnel, use traditional analog device, pcb board can't be placed, therefore use ultra-large chip FPAA(field-programmable analog device), the signal conditioning circuit such as amplifier, comparer realizes by FPAA, and FPAA exports 16 tunnel light pulse digital signal Dig[15..0].Because light signal may be crossed by force or excessively, therefore FPAA can give simulating signal AnaO the A/D input pin of auxiliary MCU, MCU judges that at regular intervals light signal is strong and weak, and the program that produces different gains and benchmark voltage reconfigures FPAA, realizes the on-the-spot reconfigurable function of mimic channel.FPGA receives 16 tunnel light pulse digital signal Dig[15..0], object is put in place and detects and the edge detection, and drive various numerals, analog chip, realize the output of digital signal, simulating signal, switching signal.
In this device, the FPAA signal conditioning circuit as shown in Figure 6, has designed a road optical signal amplification comparator circuit in figure, and left side element is the variable gain amplifier, and right elements is the adjustable comparer of reference voltage, and output digital light pulse signal is given FPGA.
In this device, the built-in function of light curtain receiver FPGA as shown in Figure 7, is comprised of clock frequency division module, synchronizing pulse/data generation module, light signal synthesis module, the detection module that puts in place, edge detection module, digital communication and D/A transition drive signal generation module.Wherein:
The major function of clock frequency division module is input 50M clock, the clock 4.17MHz after generation 12 frequency divisions.The input clock CLK50M of clock frequency division module is from the active crystal oscillator of 50M, high-frequency clock output terminal CLKA links the input end of clock of the detection module that puts in place, edge detection module, digital communication and D/A transition drive signal generation module, and another output terminal of clock LEDCLK of clock frequency division module links the input end of clock of synchronizing pulse/data generation module.Clock frequency division module is worked according to 50M crystal oscillator rising edge, rising edge of every appearance, and four count bus add one, are added to 11 rear count bus zero clearings, and the count bus most significant digit is exactly needed clock LEDCLK, and output high-frequency clock CLKA is still 50MHz.
LEDCLK=CLK50M/12=4.17MHz
Synchronizing pulse/data generation module effect is clock SerCLK and the synchrodata SerData that produces synchronous communication between light curtain receiver and transmitter, and the input clock of synchronizing pulse/data generation module is LEDCLK, and frequency is 4.17MHz.
The course of work of synchronizing pulse/data generation module is described below:, at first take LEDCLK as clock, carry out mould 270 countings, produce count bus LEDCount[8..0]; Next judge LEDCount[8..0] numerical value, as LEDCount[8..0]=1 the time, synchrodata SerData is 1, all the other any count status SerData are 0, guarantee that like this output clock SerCLK is identical with input clock LEDCLK at instantaneous high level of initial appearance of each scan period.
The effect of light signal synthesis module is according to from the 16 tunnel light pulse digital signal Dig[15..0 of FPAA] and from clock SerCLK and the synchrodata SerData of synchronizing pulse/data generation module, adopt time-division multiplex technology, a synthetic road signal LightSign output that can represent 16 road photoelectric cell states.
The course of work of light signal synthesis module is described below: at first take SerCLK as clock, SerData is reset signal, produces and stops pattern 256 counters, produces count bus CLKCount[7..0]; Next judge CLKCount[7..0] numerical value.
As CLKCount[7..0]=1 the time, LightSign=Dig[0] (first via photoelectric cell signal);
As CLKCount[7..0]=5 the time, LightSign=Dig[1] (the second road photoelectric cell signal);
As CLKCount[7..0]=9 the time, LightSign=Dig[2] (Third Road photoelectric cell signal);
CLKCount[7..0] judgement numerical value constantly add four, by that analogy, thus a synthetic road signal LightSign output.
The detection module effect that puts in place is according to from the light pulse digital signal LightSign of light signal synthesis module, from the clock CLKA of clock frequency division module with from clock SerCLK and the synchrodata SerData of synchronizing pulse/data generation module, judge whether moving object occurs, export a switching value signal SwitchOut.
The input signal of edge detection module and the detection module that puts in place are identical, and it is the front and rear side edge of detecting moving object, the output expression is initial, the data SPosi[10..0 of end position], EPosi[10..0].
Digital communication and the effect of D/A transition drive signal generation module are according to from the SPosi[10..0 of edge detection module]/EPosi[10..0], from the clock CLKA of clock frequency division module with from the synchrodata SerData of synchronizing pulse/data generation module, output can drive clock ComCLK and the data ComData of Interface for digital communication chip, the ComData cycle period is 32 bits, comprises 8 bit initial datas, 11 bit SPosi[10..0], 11 bit EPosi[10..0] and 2 preliminary datas.Digital communication and D/A transition drive signal generation module also will be exported clock DACLK, data DAData and the latch signal DALatch that can drive the D/A conversion chip,, owing to will exporting the object front and rear side along two signals, therefore adopt two D/A conversion chip concatenated schemes.
In this device, put detection module in place as shown in Figure 8 in light curtain receiver fpga chip, by single beam start stop signal generation module, single beam judgement clock generating module, string and modular converter, data accumulation module, counting judge module, formed.Wherein:
The input signal of single beam start stop signal generation module is clock SerCLK and synchrodata SerData, take SerCLK as clock, SerData is reset signal, carry out mould 4 countings, produce count bus QA[1..0], SerCLK, QA[1], QA[0] three signals produce enabling signal EPulClr and the stop signal EPulLatch of single light pulse by combinational logic.
The input signal of single beam judgement clock generating module is high-frequency clock CLKA, clock SerCLK and synchrodata SerData, export the judgement clock JudgeCLK of single light pulse, the JudgeCLK signal is the twelvefold of optical pulse frequency, namely at single beam pulse valid period JudgeCLK, ten secondary lifting edges occur.
String and modular converter major function are that 12 bit strings and conversion are carried out in single light pulse in the LightSign signal, its input end of clock JudgeCLK adjudicates clock generating module from single beam, data input pin is light pulse signal LightSign, outputting ten two bit parallel bus EPulData[11..0].String and modular converter are worked according to the JudgeCLK rising edge, rising edge of every appearance, give parallel bus EPulData[11..0 with LightSign] lowest order, use simultaneously for circulation with EPulData[11..0] 12 bits of byte move to left one, realize string and translation function.
The input signal of data accumulation module is from single light pulse enabling signal EPulClr, the stop signal EPulLatch of single beam start stop signal generation module and from going here and there also 12 bit parallel bus EPulData[11..0 of modular converter], the output signal of data accumulation module is EPulFlag.
The course of work of data accumulation module is described below: when the enabling signal EPulClr of single light pulse was high level, the output signal of data accumulation module was that EPulFlag is low level; When rising edge appears in the stop signal EPulLatch of single light pulse, 12 bit parallel code EPulData[11..0 to string and modular converter output] cumulative by turn, and to adding up and judging, if it is greater than " 9 ", the output signal EPulFlag of data accumulation module is high level, otherwise EPulFlag is low level.Therefore, the basic thought of data accumulation module is: when each light pulse started, EPulFlag was low level; When each light pulse finished, if this light pulse position does not have object to block, EPulFlag was high level, otherwise is low level.For EPulData[11..0] cumulative, large number judgement by turn, be to disturb in order to prevent, signal filtering.
The input signal of counting judge module is synchrodata SerData and from the EPulFlag signal of data accumulation module, and the output signal of counting judge module is switching value control signal SwitchOut.
The course of work of counting judge module is described below: at first take EPulFlag as clock, SerData is reset signal, produces and stops pattern 17 counters, produces count bus EPulCount[4..0]; Next judge EPulCount[4..0] numerical value, if it equals 16, explanation receives photoelectric cell and has received 16 light pulses, do not have object to block in the middle of light curtain transmitter, receiver, counting judge module output signal SwitchOut is high level, otherwise be low level, realize the object measuring ability that puts in place.
In this device, in light curtain receiver fpga chip, the edge detection module as shown in Figure 9, is comprised of standard time clock generation module, standard time clock counting module, photo-impulses counting module, synchronous subtraction block, one period delay module, state machine judge module.Wherein:
The input signal of standard time clock generation module is clock SerCLK and synchrodata SerData, take SerCLK as clock, SerData is reset signal, carries out mould 4 countings, produce count bus QA[1..0], its most significant digit QA[1] be exactly the output signal CalcuCLK of standard time clock generation module.
The input signal of standard time clock counting module is synchrodata SerData and from the CalcuCLK of standard time clock generation module, and take CalcuCLK as clock, SerData is reset signal, carries out mould 2048 countings, produces count bus CalCLKCount[10..0].
The input signal of photo-impulses counting module is synchrodata SerData and light signal LightSign, and take LightSign as clock, SerData is reset signal, carries out mould 2048 countings, produces count bus RecDataCount[10..0].
The input signal of synchronous subtraction block be from the standard time clock generation module CalcuCLK, from the count bus CalCLKCount[10..0 of standard time clock counting module], from the count bus RecDataCount[10..0 of photo-impulses counting module], when CalcuCLK signal negative edge, count bus is carried out subtraction.
SubValA[10..0]=CalCLKCount[10..0]-RecDataCount[10..0]
SubValA[10..0 wherein] be the output signal of synchronous subtraction block.
The input signal of one period delay module for from the CalcuCLK of standard time clock generation module, carry out the SubValA[10..0 of motor synchronizing subtraction block], postpone a CalcuCLK and produce the output signal SubValB[10..0 of one period delay module after the clock period].
The input signal of state machine judge module is the SubValA[10..0 that carrys out the motor synchronizing subtraction block] and from one period delay module SubValB[10..0], these two groups of bus states are judged.
As SubValA[10..0]=1 the time, SPosi[10..0]=CalCLKCount[10..0];
Illustrate that the anterior edge of object occurs, then edge, judgment object rear portion.
As SubValA[10..0]=SubValB[10..0] time,
EPosi[10..0]=CalCLKCount[10..0]-1；
The output signal SPosi[10..0 of state machine judge module] and EPosi[10..0] be exactly the front and rear side edge of object.
Figure 10 is the wave simulation figure that object edge detects, and in Fig. 9, involved each signal all represents with waveform is clear in Figure 10.In Figure 10, analog optical signal LightSign is blocked by object from the 5th～the 8th light beam, through edge detection module object front and rear side along data SPosi[10..0], EPosi[10..0] be respectively 5,8.
In sum, the present invention has adopted following technical scheme:
(1) infrared transmitting tube and reception photoelectric cell do not adopt traditional light curtain lineal layout form, but adopt the staggered plane distribution of biserial, have overcome like this restriction of sensor own vol, improve measuring accuracy;
(2) for preventing the long electromagnetic compatibility problem that causes of pcb board, the monolithic sensor board is installed 64 circuit components, adopts signal cascade between integrated circuit board, realizes detecting on a large scale;
(3) cause number of sensors and I/O interface number to double owing to improving measuring accuracy, traditional MCU, mimic channel can't be realized, so the system core is based on two kinds of ultra-large digital-to-analog integrated circuit of FPGA/FPAA;
(4) light curtain transmitter portion drives infrared transmitting tube by FPGA, realizes the high-speed optical pulse emission, and be Microsecond grade the launch time of light signal;
(5) light curtain receiver part photoelectric cell is received light signal, be converted to faint electric signal, amplify by the amplifier signal, output digit signals is given FPGA after comparer again, because device count is numerous, this signal conditioning circuit uses FPAA(field-programmable analog device) design, realize the on-the-spot restructural of mimic channel, the real-time reception of FPGA algorithm gated sweep formula multi beam infrared light, realize that putting in place of high-speed moving object detected and edge detects.
Technique scheme makes the present invention have that data processing speed is high, system response time is fast, antijamming capability is strong, upgrading is convenient, can be used for various industrial rugged surroundings, be specially adapted to metallurgical industry Bar Plant screw-thread steel production line, can be to light curtain system small, that the high-speed moving object realization puts detection, dimensional measurement in place.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention.All any modifications of doing within the spirit and principles in the present invention, be equal to and replace and improvement etc., within all should being included in protection scope of the present invention.
Claims (5)
1. the light of the high-speed, high precision based on a FPGA and FPAA curtain pick-up unit, comprise light curtain transmitter and light curtain receiver, is provided with infrared transmitting tube on light curtain transmitter, is provided with the reception photoelectric cell on light curtain receiver, it is characterized in that:
Described infrared transmitting tube and reception photoelectric cell are the staggered plane distribution of biserial;
The system core of described light curtain transmitter and light curtain receiver is based on two kinds of ultra-large digital-to-analog integrated circuit of FPGA/FPAA: described light curtain transmitter drives infrared transmitting tube by the FPGA functional module and realizes the high-speed optical pulse emission; Described light curtain receiver is used for photoelectric cell is received that light signal is converted to faint electric signal, amplify by the amplifier signal, again after comparer output digit signals to the FPGA functional module, signal conditioning circuit adopts FPAA to realize the on-the-spot restructural of mimic channel, light curtain receiver, by the real-time reception of FPGA functional module gated sweep formula multi beam infrared light, realizes that putting in place of high-speed moving object detected and edge detects.
2. a kind of light of high-speed, high precision based on FPGA and FPAA curtain pick-up unit according to claim 1, it is characterized in that: the FPGA functional module in described light curtain transmitter comprises clock frequency division module, string and modular converter, loss of clock judging module, the initial generation module of light pulse, reliable light pulse output module, wherein:
The input clock CLK50M of clock frequency division module is from the active crystal oscillator of 50M, and its output terminal of clock JudgeCLK links the input end of clock of string and modular converter;
String and modular converter are used for the SerCLK signal is gone here and there and changed, and its input end of clock JudgeCLK is from clock frequency division module, and its data input pin is linked the input pin SerCLK of FPGA, output 8 bit parallel bus InCLKPara[7..0];
The bus input of loss of clock judging module is from the parallel data output InCLKPara[7..0 of string and modular converter], its output control signal SignCt;
The initial generation module of light pulse is for generation of the conducting control signal of 16 road infrared transmitting tubes, the input clock of the initial generation module of light pulse is SerCLK, incoming sync pulse is SerData, and the output signal of the initial generation module of light pulse is the conducting control signal LightTA[15..0 of 16 road infrared transmitting tubes];
The input signal that reliable light pulse output module forms is respectively from the LightTA[15..0 of the initial generation module of light pulse and loss of clock judging module] and SignCt, reliable light pulse output module judgement SignCt high-low level, thereby output LightTB[15..0] signal.
3. a kind of light of high-speed, high precision based on FPGA and FPAA curtain pick-up unit according to claim 1, it is characterized in that: the FPGA functional module in described light curtain receiver comprises clock frequency division module, synchronizing pulse/data generation module, light signal synthesis module, the detection module that puts in place, edge detection module, digital communication and D/A transition drive signal generation module, wherein:
The input clock CLK50M of clock frequency division module is from the active crystal oscillator of 50M, its high-frequency clock output terminal CLKA links respectively the input end of clock of the detection module that puts in place, edge detection module, digital communication and D/A transition drive signal generation module, and another output terminal of clock LEDCLK of clock frequency division module links the input end of clock of synchronizing pulse/data generation module;
Synchronizing pulse/data generation module is for generation of clock SerCLK and the synchrodata SerData of synchronous communication between light curtain receiver and light curtain transmitter, and the input clock of synchronizing pulse/data generation module is that LEDCLK, frequency are 4.17MHz.
The light signal synthesis module is used for according to 16 tunnel light pulse digital signal Dig[15..0 from FPAA] and from clock SerCLK and the synchrodata SerData of synchronizing pulse/data generation module, adopt time-division multiplex technology, a synthetic road signal LightSign output that can represent 16 road photoelectric cell states.
The detection module that puts in place is used for according to the light pulse digital signal LightSign from the light signal synthesis module, from the clock CLKA of clock frequency division module with from clock SerCLK and the synchrodata SerData of synchronizing pulse/data generation module, judge whether moving object occurs, export a switching value signal SwitchOut;
The edge detection module is for detection of the front and rear side edge of moving object, and its input signal is identical with the input signal of the detection module that puts in place, output expression is initial, the data SPosi[10..0 of end position], EPosi[10..0];
Digital communication and D/A transition drive signal generation module are used for according to the SPosi[10..0 from the edge detection module] or EPosi[10..0], from the clock CLKA of clock frequency division module with from the synchrodata SerData of synchronizing pulse/data generation module, output can drive clock ComCLK and the data ComData of Interface for digital communication chip, and output can drive clock DACLK, data DAData and the latch signal DALatch of D/A conversion chip.
4. a kind of light of high-speed, high precision based on FPGA and FPAA curtain pick-up unit according to claim 3, it is characterized in that: the described detection module that puts in place comprises single beam start stop signal generation module, single beam judgement clock generating module, string and modular converter, data accumulation module, counting judge module, wherein:
The input signal of single beam start stop signal generation module is clock SerCLK and synchrodata SerData, take SerCLK as clock, SerData is reset signal, carry out mould 4 countings, produce count bus QA[1..0], and with SerCLK, QA[1], QA[0] three signals produce enabling signal EPulClr and the stop signal EPulLatch of single light pulse by combinational logic;
The input signal of single beam judgement clock generating module is high-frequency clock CLKA, clock SerCLK and synchrodata SerData, the judgement clock JudgeCLK of the single light pulse of output;
String and modular converter are used for the single light pulse to the LightSign signal and carry out 12 bit strings and conversion, its input end of clock JudgeCLK adjudicates clock generating module from single beam, data input pin is light pulse signal LightSign, outputting ten two bit parallel bus EPulData[11..0];
The input signal of data accumulation module is from single light pulse enabling signal EPulClr, the stop signal EPulLatch of single beam start stop signal generation module and from going here and there also 12 bit parallel bus EPulData[11..0 of modular converter], the output signal of data accumulation module is EPulFlag;
The input signal of counting judge module is synchrodata SerData and from the EPulFlag signal of data accumulation module, and the output signal of counting judge module is switching value control signal SwitchOut.
5. a kind of light of high-speed, high precision based on FPGA and FPAA curtain pick-up unit according to claim 3, it is characterized in that: described edge detection module comprises standard time clock generation module, standard time clock counting module, photo-impulses counting module, synchronous subtraction block, one period delay module, state machine judge module, wherein:
The input signal of standard time clock generation module is clock SerCLK and synchrodata SerData, take SerCLK as clock, SerData is reset signal, carries out mould 4 countings, produce count bus QA[1..0], its most significant digit QA[1] be exactly the output signal CalcuCLK of standard time clock generation module;
The input signal of standard time clock counting module is synchrodata SerData and from the CalcuCLK of standard time clock generation module, and take CalcuCLK as clock, SerData is reset signal, carries out mould 2048 countings, produces count bus CalCLKCount[10..0];
The input signal of photo-impulses counting module is synchrodata SerData and light signal LightSign, and take LightSign as clock, SerData is reset signal, carries out mould 2048 countings, produces count bus RecDataCount[10..0];
The input signal of synchronous subtraction block be from the standard time clock generation module CalcuCLK, from the count bus CalCLKCount[10..0 of standard time clock counting module], from the count bus RecDataCount[10..0 of photo-impulses counting module], when CalcuCLK signal negative edge, count bus is carried out subtraction, be SubValA[10..0]=CalCLKCount[10..0]-RecDataCount[10..0], SubValA[10..0 wherein] and be the output signal of synchronous subtraction block;
The input signal of one period delay module for from the CalcuCLK of standard time clock generation module, carry out the SubValA[10..0 of motor synchronizing subtraction block], postpone a CalcuCLK and produce the output signal SubValB[10..0 of one period delay module after the clock period];
The input signal of state machine judge module is the SubValA[10..0 that carrys out the motor synchronizing subtraction block] and from one period delay module SubValB[10..0], these two groups of bus states are judged: as SubValA[10..0]=1 the time, SPosi[10..0]=CalCLKCount[10..0], the anterior edge of expression object occurs, follows edge, judgment object rear portion; As SubValA[10..0]=SubValB[10..0] time, EPosi[10..0]=CalCLKCount[10..0] – 1; The output signal SPosi[10..0 of state machine judge module] and EPosi[10..0] be exactly the front and rear side edge of object.
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