CN103383932A - 用于提高芯片电性能的封装结构 - Google Patents

用于提高芯片电性能的封装结构 Download PDF

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CN103383932A
CN103383932A CN2013102933827A CN201310293382A CN103383932A CN 103383932 A CN103383932 A CN 103383932A CN 2013102933827 A CN2013102933827 A CN 2013102933827A CN 201310293382 A CN201310293382 A CN 201310293382A CN 103383932 A CN103383932 A CN 103383932A
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welding
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张雄杰
何洪运
程琳
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Suzhou Good Ark Electronics Co Ltd
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Abstract

本发明一种用于提高芯片电性能的封装结构，其第一引线条一端的支撑区连接到整流芯片下表面，该整流芯片下表面通过焊锡膏与该第一引线条的支撑区电连接；位于第二引线条一端的焊接区与连接片的第一焊接面连接；连接片第二焊接面与整流芯片上表面通过焊锡膏电连接；连接片的第一焊接面和第二焊接面之间具有一中间区，此中间区与第一焊接面和第二焊接面之间分别设有第一折弯处和第二折弯处，所述连接片的第二焊接面相对的两侧端面均具有条状缺口。本发明封装结构可以自适应吸收多余的焊料，既保证了焊接区域铺展有足够面积的焊料，又避免了因为焊料量多而溢出可焊接区造成产品失效，提高了产品电性、可靠性和良率。

Description

用于提高芯片电性能的封装结构
技术领域
本发明涉及一种半导体封装器件，尤其涉及一种用于提高芯片电性能的封装结构。
背景技术
整流器是利用二极管的单向导电特性对交流电进行整流，故被广泛应用于交流电转换成直流电的电路中。
在设计开发连接片结构半导体产品时，为了提升大功率器件芯片表面的导电性能暨提升器件的关键电特性，需要把连接片与芯片焊接部分的面积设计的足够大。连接片与芯片上表面通过焊料焊接在一起。受限于连接片-芯片焊接区域和芯片上表面面积的匹配，焊料用量的控制成为关键工艺参数。焊料偏少会导致器件电特性不良，焊料过多会导致器件短路或早期可靠性失效。现有技术往往存在随着时间的延长，会出现各种电性能下降。
因此，如何研发一种整流芯片封装结构，能解决上述问题，便成为本领域技术人员努力的方向。
发明内容
本发明目的是提供一种用于提高芯片电性能的封装结构，该封装结构可以自适应吸收多余的焊料，既保证了焊接区域铺展有足够面积的焊料，又避免了因为焊料量多而溢出可焊接区造成产品失效，提高了产品电性、可靠性和良率。
为达到上述目的，本发明采用的技术方案是：一种用于提高芯片电性能的封装结构，包括位于环氧封装体内的第一引线条、第二引线条、连接片和整流芯片，该第一引线条一端的支撑区连接到所述整流芯片下表面，该整流芯片下表面通过焊锡膏与该第一引线条的支撑区电连接，第一引线条另一端作为器件电流传输的引脚区；
位于所述第二引线条一端的焊接区与连接片的第一焊接面连接，该第二引线条另一端作为器件电流传输的引脚区；所述连接片第二焊接面与整流芯片上表面通过焊锡膏电连接；
所述连接片的第一焊接面和第二焊接面之间具有一中间区，此中间区与第一焊接面和第二焊接面之间分别设有第一折弯处和第二折弯处，从而使得中间区高度高于第一焊接面和第二焊接面，所述连接片的第二焊接面相对的两侧端面均具有条状缺口；所述第二焊接面均匀分布有若干个通孔。
上述技术方案中进一步改进的方案如下：
1. 上述方案中，所述连接片的第一焊接面高度低于所述第二焊接面高度。
2. 上述方案中，所述第一折弯处、第二折弯处与中间区夹角为125°~145°。
由于上述技术方案运用，本发明与现有技术相比具有下列优点和效果：
1. 本发明用于提高芯片电性能的封装结构，其连接片的第一焊接面和第二焊接面之间具有一中间区，此中间区与第一焊接面和第二焊接面之间分别设有第一折弯处和第二折弯处，从而使得中间区高度高于第一焊接面和第二焊接面，所述连接片的第二焊接面相对的两侧端面均具有条状缺口，在保证不降低接触面积和增加电阻的情况下，可以自适应吸收多余的焊料，从而防止焊料进入非焊接区，既保证了焊接区域铺展有足够面积的焊料，又避免了因为焊料量多而溢出可焊接区造成产品失效、短路，提高了产品电性和可靠性大大提高了良率。
2. 本发明用于提高芯片电性能的封装结构，其连接片的第一焊接面和第二焊接面之间具有一中间区，此中间区与第一焊接面和第二焊接面之间分别设有第一折弯处和第二折弯处，从而使得中间区高度高于第一焊接面和第二焊接面，所述连接片的第二焊接面相对的两侧端面均具有条状缺口；所述第二焊接面均匀分布有若干个通孔；既可防止焊料进入非焊接区，避免了因为焊料量多而溢出可焊接区造成产品失效、短路，提高了产品电性和可靠性大大提高了良率，第二焊接面均匀分布有若干个通孔由于通孔覆盖溢出的焊料，防止焊料在焊接面边缘溢出，且利用了连接片中第一通孔的侧面积，减小了接触电阻和响应时间，降低了功耗，也加强了连接片与整流芯片的连接强度。
附图说明
附图1为现有技术封装结构示意图一；
附图2为现有技术封装结构示意图二；
附图3为本发明用于提高芯片电性能的封装结构结构示意图；
附图4为附图3中A-A剖面结构示意图。
以上附图中：1、第一引线条；11、支撑区；2、第二引线条；21、焊接区；3、连接片；31、第一焊接面；32、第二焊接面；33、中间区；34、第一折弯处；35、第二折弯处；4、整流芯片；5、引脚区；6、条状缺口；7、通孔；8、焊料。
具体实施方式
下面结合附图及实施例对本发明作进一步描述：
实施例：一种用于提高芯片电性能的封装结构，包括位于环氧封装体内的第一引线条1、第二引线条2、连接片3和整流芯片4，该第一引线条1一端的支撑区11连接到所述整流芯片4下表面，该整流芯片4下表面通过焊锡膏与该第一引线条1的支撑区11电连接，第一引线条1另一端作为器件电流传输的引脚区5；
位于所述第二引线条2一端的焊接区21与连接片3的第一焊接面31连接，该第二引线条2另一端作为器件电流传输的引脚区5；所述连接片3第二焊接面32与整流芯片4上表面通过焊锡膏电连接；
所述连接片3的第一焊接面31和第二焊接面32之间具有一中间区33，此中间区33与第一焊接面31和第二焊接面32之间分别设有第一折弯处34和第二折弯处35，从而使得中间区33高度高于第一焊接面31和第二焊接面32，所述连接片3的第二焊接面相对的两侧端面均具有条状缺口6；所述第二焊接面32均匀分布有若干个通孔7。
上述连接片3的第一焊接面31高度低于所述第二焊接面32高度。
上述第一折弯处34、第二折弯处35与中间区33夹角为125°或者130°或者145°。
采用上述用于提高芯片电性能的封装结构时，其连接片的第一焊接面和第二焊接面之间具有一中间区，此中间区与第一焊接面和第二焊接面之间分别设有第一折弯处和第二折弯处，从而使得中间区高度高于第一焊接面和第二焊接面，所述连接片的第二焊接面相对的两侧端面均具有条状缺口，在保证不降低接触面积和增加电阻的情况下，可以自适应吸收多余的焊料，从而防止焊料8进入非焊接区，既保证了焊接区域铺展有足够面积的焊料，又避免了因为焊料8量多而溢出可焊接区造成产品失效、短路，提高了产品电性和可靠性大大提高了良率；其次，其连接片的第一焊接面和第二焊接面之间具有一中间区，此中间区与第一焊接面和第二焊接面之间分别设有第一折弯处和第二折弯处，从而使得中间区高度高于第一焊接面和第二焊接面，所述连接片的第二焊接面相对的两侧端面均具有条状缺口；所述第二焊接面均匀分布有若干个通孔；既可防止焊料8进入非焊接区，避免了因为焊料量多而溢出可焊接区造成产品失效、短路，提高了产品电性和可靠性大大提高了良率，第二焊接面均匀分布有若干个第二通孔由于通孔覆盖溢出的焊料，防止焊料8在焊接面边缘溢出，同时由于第二通孔的侧表面覆盖有溢出的焊料，减小了接触电阻，降低了功耗。
上述实施例只为说明本发明的技术构思及特点，其目的在于让熟悉此项技术的人士能够了解本发明的内容并据以实施，并不能以此限制本发明的保护范围。凡根据本发明精神实质所作的等效变化或修饰，都应涵盖在本发明的保护范围之内。

Claims (3)

1. 一种用于提高芯片电性能的封装结构，包括位于环氧封装体内的第一引线条（1）、第二引线条（2）、连接片（3）和整流芯片（4），该第一引线条（1）一端的支撑区（11）连接到所述整流芯片（4）下表面，该整流芯片（4）下表面通过焊锡膏与该第一引线条（1）的支撑区（11）电连接，第一引线条（1）另一端作为器件电流传输的引脚区（5）；
位于所述第二引线条（2）一端的焊接区（21）与连接片（3）的第一焊接面（31）连接，该第二引线条（2）另一端作为器件电流传输的引脚区（5）；所述连接片（3）第二焊接面（32）与整流芯片（4）上表面通过焊锡膏电连接；
其特征在于：所述连接片（3）的第一焊接面（31）和第二焊接面（32）之间具有一中间区（33），此中间区（33）与第一焊接面（31）和第二焊接面（32）之间分别设有第一折弯处（34）和第二折弯处（35），从而使得中间区（33）高度高于第一焊接面（31）和第二焊接面（32），所述连接片（3）的第二焊接面相对的两侧端面均具有条状缺口（6）；所述第二焊接面（32）均匀分布有若干个通孔（7）。
2. 根据权利要求1所述的封装结构，其特征在于：所述连接片（3）的第一焊接面（31）高度低于所述第二焊接面（32）高度。
3. 根据权利要求1所述的封装结构，其特征在于：所述第一折弯处（34）、第二折弯处（35）与中间区（33）夹角为125°~145°。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107204319A (zh) * 2015-01-19 2017-09-26 苏州固锝电子股份有限公司 小信号用稳压半导体器件
CN108598179A (zh) * 2015-01-19 2018-09-28 苏州固锝电子股份有限公司 电子产品用大电流整流芯片
CN110416101A (zh) * 2019-08-07 2019-11-05 深圳市顺益微电子有限公司 用烧结银浆作为粘接剂的电源模块铜片焊接工艺

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201699009U (zh) * 2010-06-08 2011-01-05 日立电线(苏州)精工有限公司 一种半导体封装结构
CN201750347U (zh) * 2010-08-02 2011-02-16 苏州固锝电子股份有限公司 一种二极管整流器
CN103117355A (zh) * 2013-02-01 2013-05-22 苏州固锝电子股份有限公司 贴片式二极管器件结构
CN203367267U (zh) * 2013-07-12 2013-12-25 苏州固锝电子股份有限公司 自适应焊料用量的整流器结构

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201699009U (zh) * 2010-06-08 2011-01-05 日立电线(苏州)精工有限公司 一种半导体封装结构
CN201750347U (zh) * 2010-08-02 2011-02-16 苏州固锝电子股份有限公司 一种二极管整流器
CN103117355A (zh) * 2013-02-01 2013-05-22 苏州固锝电子股份有限公司 贴片式二极管器件结构
CN203367267U (zh) * 2013-07-12 2013-12-25 苏州固锝电子股份有限公司 自适应焊料用量的整流器结构

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107204319A (zh) * 2015-01-19 2017-09-26 苏州固锝电子股份有限公司 小信号用稳压半导体器件
CN107221522A (zh) * 2015-01-19 2017-09-29 苏州固锝电子股份有限公司 高良率整流器件
CN107293530A (zh) * 2015-01-19 2017-10-24 苏州固锝电子股份有限公司 高精度高良率整流器件
CN108598179A (zh) * 2015-01-19 2018-09-28 苏州固锝电子股份有限公司 电子产品用大电流整流芯片
CN108598178A (zh) * 2015-01-19 2018-09-28 苏州固锝电子股份有限公司 高稳定性微电子器件
CN107293530B (zh) * 2015-01-19 2020-03-24 苏州固锝电子股份有限公司 高精度高良率整流器件
CN108598178B (zh) * 2015-01-19 2020-12-04 苏州固锝电子股份有限公司 微电子器件用整流芯片
CN110416101A (zh) * 2019-08-07 2019-11-05 深圳市顺益微电子有限公司 用烧结银浆作为粘接剂的电源模块铜片焊接工艺

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