CN103354237A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- CN103354237A CN103354237A CN2013102919567A CN201310291956A CN103354237A CN 103354237 A CN103354237 A CN 103354237A CN 2013102919567 A CN2013102919567 A CN 2013102919567A CN 201310291956 A CN201310291956 A CN 201310291956A CN 103354237 A CN103354237 A CN 103354237A
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Abstract
The invention relates to a semiconductor device, which comprises at least two grid electrodes, at least two source electrodes, a drain electrode, a channel region and a drift region, wherein the drift region surrounds the drain electrode, the channel region surrounds the drift region, the source electrodes are arranged outside the channel region, and the amount of the grid electrodes is the same with that of the source electrodes. According to the invention, two or more semiconductor devices can share the drain electrode and the drift region, so that layout and connecting wires of chips are optimized, device area is reduced, and production cost is decreased; requirements of a power switch system for control circuit with low standby power consumption is satisfied, so that power consumption of the chips is reduced; and based on compatibility with CMOS technology, the device is more practical.
Description
Technical field
The invention belongs to semiconductor design and manufacture field, relate to a kind of semiconductor device.
Background technology
Along with the development of semiconductor process techniques, Laterally Diffused Metal Oxide Semiconductor (LDMOS) and junction field effect transistor (JFET) production technology reach its maturity, and voltage endurance capability progressively improves.Due to the demand of switch power supply system for such semiconductor device, and with the compatibility of CMOS technique, such semiconductor device is just starting to be widely used in switch power supply system, especially can meet the environment protection switch power supply of strict Energy Efficiency Standard.
At present, in some application, for Limited Current, with semiconductor device, with the withstand voltage resistance of larger resistance, be connected, because the current limiting capacity of withstand voltage resistance is limited, cause the power loss of system larger; And semiconductor device and withstand voltage resistance all can occupy larger chip area, cause the cost of this series products higher.
Under the high-voltage applications environment, because requirement of withstand voltage improves and the general size of high-voltage semi-conductor manufacturing process and design rule are greater than general low pressure process, and under the high-voltage applications environment, electric current is larger, the negative effect that above-mentioned power consumption penalty and enlarged areas are caused is more remarkable.
Summary of the invention
Cause for overcoming existing technique design rule at high tension apparatus and high tension apparatus interval under the high-voltage applications environment technological deficiency that area is larger, the invention discloses a kind of semiconductor device.
Semiconductor device, comprise grid, source electrode, drain electrode (11) and channel region, described drain electrode and channel region also comprise respectively drain well and channel region trap, it is characterized in that, also comprise the drift region (12) that surrounds drain electrode, described channel region surrounds drift region, and the described channel region outside is source electrode, and described grid and source electrode are divided into respectively at least two.
Preferably, the quantity of described grid and source electrode is identical.
Preferably, described grid and source electrode are divided into identical at least two of shape.
Preferably, described drift region, channel region, source electrode are donut shape from inside to outside successively, and described gate shapes is corresponding with the channel region shape.
Further, described grid is divided into first grid (13) and second grid (23), and the central angle ratio of described first grid (13) and second grid (23) is 7:1.
Preferably, described source electrode also comprises source well.
Further, described source electrode well depth, drain electrode well depth, channel region well depth are all identical.
Preferably, also comprise substrate, between described source electrode, adopt isolation well to realize the electricity isolation, described isolation well is identical with substrate electric potential
.
Further, the described isolation well degree of depth, drain electrode well depth, channel region well depth are all identical.
Preferably, the spacing between described grid is more than 2 times of minimum design rule.
Adopt semiconductor device of the present invention, the drain terminal of two or more semiconductor device and drift region are shared, the line of laying out pattern and chip is optimized, and has reduced device area, reduce production costs; Meet the demand of switch power supply system to the low standby power loss control circuit, the power loss of chip is reduced; Developed this device on the CMOS technique compatible basis, made this device have more practicality.
The accompanying drawing explanation
Fig. 1 illustrates the plane figure schematic diagram of a kind of embodiment of semiconductor device of the present invention;
Fig. 2 illustrates the cutaway view of a kind of embodiment of semiconductor device of the present invention;
Fig. 3 illustrates the circuit diagram of a kind of embodiment of semiconductor device of the present invention;
In each figure, the Reference numeral name is called: 10-first device 11-drain electrode 12-drift region 13-first grid 14-first source electrode 20-second device 23-second grid 24-the second source electrode.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail.
Semiconductor device, comprise grid, source electrode, drain electrode and channel region, also comprises the drift region that surrounds drain electrode, and described channel region surrounds drift region, and the described channel region outside is source electrode, and described grid and source electrode are divided into identical at least two of quantity.
Semiconductor device of the present invention is actual comprises a plurality of devices, two devices of take are example, and the connected mode of these two devices should be circuit structure as shown in Figure 3, and two metal-oxide-semiconductors of take in Fig. 3 are example, the drain electrode of these two MOS links together, and source electrode and grid are independent respectively.In the present invention, around drain electrode, be drift region, drift region is a kind of common structure in the high-voltage semi-conductor manufacturing process, the common doping content in drift region is lower than source region or raceway groove, and the top, drift region does not have polysilicon gate simultaneously, can not transoid, resistance is larger, bears high voltage in high tension apparatus.Drift region is positioned at the drain electrode outside and surrounds whole drain electrode, and the outside, drift region is channel region and source electrode, due to separating of grid and source electrode, has realized the shared device of drain electrode more than two.Channel region surrounds drift region, and drift region surrounds the structure of drain electrode, objectively disperseed to take power line that drain electrode is end points in drift region, the distribution of channel region and source electrode.Improved the voltage endurance capability of device, the while, because drain electrode and drift region shares, has also been dwindled device area.
Preferably, described drift region, channel region, source electrode are donut shape from inside to outside successively, and described gate shapes is corresponding with the channel region shape.Adopt toroidal, be conducive to being uniformly distributed of electric field line, improve the withstand voltage properties of device.
Those skilled in the art are known, and the active area of grid below is channel region, makes the active area transoid when grid voltage changes
Form raceway groove, if some particular device, grid also can be from active area below process, the zone that can cause transoid at gate charge, the corresponding channel region that forms.
For the specific embodiment of the present invention better is described, with specific embodiment of the present invention Fig. 1 to 2 illustrate.
The plane that Fig. 1 is this specific embodiment shows figure, this semiconductor structure is divided into two devices, the first device 10 is enhancement mode N-type LDMOS pipe, its structure is symmetrical structure, drain electrode 11 is circular, drift region 12 is annular, and first grid 13 is about 7/8 annulus, 7 sections annulus that the first source electrode 14 is the dispersion of evenly arranging.The second device 20 is depletion type N-type LDMOS pipe, its structure is also symmetrical structure, drain electrode shares with the first device, a complete annulus of the common formation in the drift region of drift region and the first device, second grid 23 is about 1/8 annulus, the grid lead that the second source electrode 24 is highlighted is divided into 2 sections annulus, and grid lead is outstanding is for convenient punching contact.In Fig. 1, the spacing between first grid and second grid is preferably got more than 2 times of minimum design rule, obtains withstand voltage effect and matching effect preferably.
For convenience of subsequent technique, revise, save the quantity of revising reticle, described grid and source class can be divided into multistage, quantity can be identical, also can be different, when needs are regulated the device breadth length ratio, utilize the upper strata metal routing optionally to connect in the wherein part of grid pole that is divided into multistage or source electrode punching, can in the situation that do not change each layer photoetching version of semiconductor front end technique, can realize the adjusting to the device breadth length ratio.The shape of grid and source electrode segmentation can be identical, also can be different, according to the designer, consider, and for example can be divided into identical some sections of length, also can be divided into Length Ratio and be some sections of Geometric Sequence, realize that the breadth length ratio of different demands is regulated.
Provide the profile of the semiconductor structure described in Fig. 1 along the AA line in Fig. 2, semiconductor device comprises the first device 10 in the dotted line frame of the right and the second interior device 20 of left side dotted line frame in Fig. 2, wherein the first device is enhancement mode N-type LDMOS pipe, and the second device is depletion type N-type LDMOS pipe.Two device architectures are basic identical, but subregion doping content difference, the channel region top of depletion type pipe has one deck NDD layer, NDD to mean light dope N-type threshold value adjustment district.In figure, each letter is known expression way in the semiconductor device technology field, and FOX means that field oxide, NW mean the N trap, and PW means the P trap, and HVNW means high pressure N trap, and N+ means the heavy doping N type semiconductor, and P-means doped with P type semiconductor.In Fig. 2, substrate is the P-layer, and substrate and the drift region of two devices are integrated, and drain electrode shares.Convenient for technique, the N trap is got consistent with the degree of depth of P trap.In Fig. 2, the P well depth degree of channel region, drain identical with the N well depth degree of source electrode, also can be consistent with it as the degree of depth of isolation well (not shown in FIG.) of the different source class of isolation.In Fig. 2, isolation well is the P trap, and forms excellent electric contact between the P-substrate, and the two current potential is consistent.Need explanation, source well is in order to increase the decision design of source electrode voltage endurance capability, in the situation that requirement of withstand voltage is not high, also can not adopt the source well design in Fig. 2.
In Fig. 2, the N+ of middle body is that shared drain electrode 11,13,23 is respectively first grid and second grid, and 14,24 are respectively the first source electrode and the second source electrode.
Previous embodiment is to be divided into two devices, the first device is enhancement mode N-type LDMOS pipe, the second device is that depletion type N-type LDMOS pipe is example, obvious the first device and the second device also can adopt other devices of P type device or N-type, as long as drain electrode and the drift region of the first device and the second device can share.And the division numbers of grid and source electrode also is not limited to two, be divided into three, four or more all can, division numbers is considered according to designer's circuit or device design.
In the semiconductor layout design, parallel transistor adopts the shared situation of drain electrode unrare, to for example common like this high tension apparatus of LDMOS, in the middle of many employing drain electrodes are positioned at, the drift region of two pipes is positioned at the drain electrode both sides, when a plurality of devices of needs are in parallel when realizing larger breadth length ratio, adopt the matrix form array devices, utilize multiple layer metal line cross wiring to realize in parallel, the shortcoming of doing like this is the cabling complexity, and under cabling complexity and high-pressure process, various design rules comprise live width, distance between centers of tracks, the increase of trap spacing etc., make the high tension apparatus volume of large breadth length ratio expand.
Adopt semiconductor structure of the present invention, utilize concentric geometry to realize that drain electrode and drift region share, relatively traditional matrix array devices, the original a plurality of devices large breadth length ratio devices use annulus that could realize in parallel is realized, a plurality of drift regions are merged, eliminated the spacing of the high pressure he design rules specify of drift region and relevant range, significantly reduced the shared area of device, and, because source class, grid are all realized interconnectedly on ring, also simplified metal routing.
Although the relatively original matrix arrangement mode of above-mentioned annulus mode is sacrificed to some extent on the matching of device, but in the less demanding occasion of some matching, two of previous embodiment devices for example, a device is as current limiting switch, in the situation of another device as current-limiting resistance, because the current-limiting resistance resistance is very low to the matching requirement, adopt semiconductor structure of the present invention still can reach the design effect of expection, and area reduce greatly.
For example, to the circuit shown in Fig. 3, when the drain electrode of two devices all connects high level, source ground or than electronegative potential, and two devices do not need under the application conditions of higher matching degree, because two devices all need high pressure resistantly, adopt two devices of usual manner to arrange respectively, the area occupied of drain electrode and drift region is larger, and adopting drain electrode of the present invention and drift region to share, drift region surrounds the implementation of drain electrode, can when realizing circuit function, significantly dwindle area.
Previously described is each preferred embodiment of the present invention, preferred implementation in each preferred embodiment is if not obviously contradictory or take a certain preferred implementation as prerequisite, each preferred implementation stack combinations is arbitrarily used, design parameter in described embodiment and embodiment is only the invention proof procedure for clear statement inventor, not in order to limit scope of patent protection of the present invention, scope of patent protection of the present invention still is as the criterion with its claims, the equivalent structure that every utilization specification of the present invention and accompanying drawing content are done changes, in like manner all should be included in protection scope of the present invention.
Claims (10)
1. semiconductor device, comprise grid, source electrode, drain electrode (11) and channel region, described drain electrode and channel region also comprise respectively drain well and channel region trap, it is characterized in that, also comprise the drift region (12) that surrounds drain electrode, described channel region surrounds drift region, and the described channel region outside is source electrode, and described grid and source electrode are divided into respectively at least two.
2. semiconductor device as claimed in claim 1, is characterized in that, the quantity of described grid and source electrode is identical.
3. semiconductor device as claimed in claim 1, is characterized in that, described grid and source electrode are divided into identical at least two of shape.
4. semiconductor device as claimed in claim 1, is characterized in that, described drift region, channel region, source electrode are donut shape from inside to outside successively, and described gate shapes is corresponding with the channel region shape.
5. semiconductor device as claimed in claim 4, is characterized in that, described grid is divided into first grid (13) and second grid (23), and the central angle ratio of described first grid (13) and second grid (23) is 7:1.
6. semiconductor device as claimed in claim 1, is characterized in that, described source electrode also comprises source well.
7. semiconductor device as claimed in claim 6, is characterized in that, described source electrode well depth, drain electrode well depth, channel region well depth are all identical.
8. semiconductor device as claimed in claim 1, also comprise substrate, it is characterized in that, between described source electrode, adopts isolation well to realize the electricity isolation, and described isolation well is identical with substrate electric potential
.
9. semiconductor device as claimed in claim 8, is characterized in that, the described isolation well degree of depth, drain electrode well depth, channel region well depth are all identical.
10. semiconductor device as claimed in claim 1, is characterized in that, the spacing between described grid is more than 2 times of minimum design rule.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104979389A (en) * | 2014-04-01 | 2015-10-14 | 世界先进积体电路股份有限公司 | Semiconductor device and manufacturing method thereof |
| CN108269857A (en) * | 2016-12-30 | 2018-07-10 | 无锡华润上华科技有限公司 | Junction field effect transistor and preparation method thereof |
| CN108766965A (en) * | 2018-08-03 | 2018-11-06 | 淄博汉林半导体有限公司 | A kind of plough groove type pair MOS transistor device and manufacturing method that drain electrode is shared |
| CN113990942A (en) * | 2021-12-28 | 2022-01-28 | 北京芯可鉴科技有限公司 | LDMOS device with circularly symmetric structure and preparation method thereof |
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| JP2000332243A (en) * | 1999-05-21 | 2000-11-30 | Nissan Motor Co Ltd | Semiconductor device |
| CN101771084A (en) * | 2010-01-20 | 2010-07-07 | 电子科技大学 | Layout structure of transverse power components |
| CN101916778A (en) * | 2010-07-20 | 2010-12-15 | 上海新进半导体制造有限公司 | High-voltage semiconductor device and manufacturing method thereof |
| US20120132956A1 (en) * | 2005-07-27 | 2012-05-31 | Infineon Technologies Ag | Semiconductor component with high breakthrough tension and low forward resistance |
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2013
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2000332243A (en) * | 1999-05-21 | 2000-11-30 | Nissan Motor Co Ltd | Semiconductor device |
| US20120132956A1 (en) * | 2005-07-27 | 2012-05-31 | Infineon Technologies Ag | Semiconductor component with high breakthrough tension and low forward resistance |
| CN101771084A (en) * | 2010-01-20 | 2010-07-07 | 电子科技大学 | Layout structure of transverse power components |
| CN101916778A (en) * | 2010-07-20 | 2010-12-15 | 上海新进半导体制造有限公司 | High-voltage semiconductor device and manufacturing method thereof |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104979389A (en) * | 2014-04-01 | 2015-10-14 | 世界先进积体电路股份有限公司 | Semiconductor device and manufacturing method thereof |
| CN108269857A (en) * | 2016-12-30 | 2018-07-10 | 无锡华润上华科技有限公司 | Junction field effect transistor and preparation method thereof |
| CN108269857B (en) * | 2016-12-30 | 2020-09-04 | 无锡华润上华科技有限公司 | Junction field effect transistor and manufacturing method thereof |
| CN108766965A (en) * | 2018-08-03 | 2018-11-06 | 淄博汉林半导体有限公司 | A kind of plough groove type pair MOS transistor device and manufacturing method that drain electrode is shared |
| CN113990942A (en) * | 2021-12-28 | 2022-01-28 | 北京芯可鉴科技有限公司 | LDMOS device with circularly symmetric structure and preparation method thereof |
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| CN103354237B (en) | 2016-01-27 |
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Address after: 610000 Chengdu province high tech Zone, West core road, No. 4, No. Patentee after: Chengdu Qi Chen electronic Limited by Share Ltd Address before: 610000 Chengdu province high tech Zone, West core road, No. 4, No. Patentee before: Chengdu Chip-Rail Microelectronic Co., Ltd. |