CN103325820A

CN103325820A - Double-gate SOI-LIGBT device with P-type buried layer

Info

Publication number: CN103325820A
Application number: CN2013102347549A
Authority: CN
Inventors: 孙镇; 黄勇
Original assignee: Sichuan Changhong Electric Co Ltd
Current assignee: Sichuan Changhong Electric Co Ltd
Priority date: 2013-06-14
Filing date: 2013-06-14
Publication date: 2013-09-25

Abstract

The invention relates to a semiconductor device and discloses a double-gate SOI-LIGBT device with a P-type buried layer. Under the condition that voltage resistance is ensured, the current capacity of the device is enhanced. According to the double-gate SOI-LIGBT device, the P-type buried layer is additionally arranged, traditional bulk silicon is changed into polycrystalline silicon for serving as filling materials of a separation groove, the separation groove is connected with a gate end electrode through a metal structure and accordingly serves as a gate electrode in the lateral direction of the device. The double-gate SOI-LIGBT device not only can serve as a gate field plate to be shrunk into an electric field near a channel region for meeting the voltage resistance requirement. Meanwhile, the double-gate SOI-LIGBT device can serve as a longitudinal gate electrode so that the current can stream on the surface and can also stream below the P-type buried layer in a device body area, the current capacity is enhanced, on-resistance is reduced, and therefore the size of the device in the width direction can be shortened under the condition that the voltage resistance is ensured. The double-gate SOI-LIGBT device with the P-type buried layer is suitable for a PDP scanning driving chip.

Description

With the double gate SOI of p type buried layer-LIGBT device

Technical field

The present invention relates to a kind of semiconductor device, relate to specifically a kind of a kind of novel double gate SOI with p type buried layer that in the PDP scanning drive chip, uses-LIGBT(silicon-on-insulator-lateral insulated gate transistor) device.

Background technology

Wide and dynamic response has obtained large-scale application to plasma display soon because of its colour gamut.Wherein line scanning drives the transversal line scanning that chip is used for display, belongs to the critical component of plasma display.Line scanning drives in the chip design, need output 96 passage independence high pressure, output stage comprises and pulls up transistor and pull-down transistor, the current capacity of pull-down transistor need to reach 1.5A, the withstand voltage 200V of OFF state, so its transistorized Width is larger, 96 tunnel drop-down LIGBT (lateral insulated gate transistor) gross areas reach the comprehensive area 30% of chip.

Traditional SOI-LIGBT has introduced the RESURF(RESURF) technology to be to realize realizing that in the finite length direction 200V's is withstand voltage.In its turn off process, the surface metal field plate has improved the peak value of electric field, so that device can have is higher withstand voltage, and in the ON state process, the electric current line can only concentrate on device surface.

Traditional SOI-LIGBT device architecture as shown in Figure 1, it comprises N-type buffering area 1, P type tagma 2, deep-well region 3, an oxidation and gate oxide (hereinafter to be referred as oxide layer) 4; Draw drain terminal electrode 5 from described N-type buffering area 1, the end of grid termination electrode 7 is positioned on the oxide layer 4 and with oxide layer 4 and contacts; Draw source electrode 6 from described deep-well region 3; In addition, this SOI-LIGBT device also comprise the outside that is located at deep-well region 3 and and deep-well region 3 between spaced isolation channel 8, and the epitaxial loayer 9 adjacent with isolation channel 8.

In order to realize the highly integrated of chip, further reduce the area of chip, dwindle the SOI-LIGBT device is a good settling mode in the size of Width as far as possible, yet, at present will be in the situation that the further size of reduction of device on Width of its withstand voltage condition of assurance, just can only realize by the current capacity that increases device, good solution not yet occur at present.

Summary of the invention

Technical problem to be solved by this invention is: propose a kind of novel double gate SOI with p type buried layer-LIGBT device, in the situation that guarantee withstand voltage condition, increase the current capacity of device.

The scheme that the present invention solves the problems of the technologies described above employing is: with the double gate SOI of p type buried layer-LIGBT device, comprise N-type buffering area 1, P type tagma 2, deep-well region 3, oxide layer 4, be located at deep-well region 3 the outside and and deep-well region 3 between spaced isolation channel 8 and the epitaxial loayer 9 adjacent with isolation channel 8; The end of grid termination electrode 7 is positioned on the oxide layer 4 and with oxide layer 4 and contacts; From described N-type buffering area 1, draw drain terminal electrode 5; Draw source electrode 6 from described deep-well region 3; Below described P type tagma 2, also be provided with the p type buried layer 11 that contacts with described deep-well region 3 with P type tagma 2; Described isolation channel 8 links to each other with described grid termination electrode 7 by metal structure 10.

Further, adopt polysilicon to fill in the described isolation channel 8.

The invention has the beneficial effects as follows: by increasing p type buried layer, and the filling material in the isolation channel is converted to the filling polysilicon by the body silicon in the tradition, isolation channel is linked to each other with the grid termination electrode by metal structure, thereby with its gate electrode as the device-side direction, make it both can be used as a kind of grid field plate, near the electric field that dwindles channel region reaches withstand voltage requirement, simultaneously conduct is gate electrode longitudinally, so that electric current is except flowing on the surface, also can below the p type buried layer in device tagma, flow, increase current capacity, reduce conducting resistance, and then can guarantee that reduction of device is in the size of Width under the withstand voltage condition.

Description of drawings

Fig. 1 is the SOI-LIGBT device architecture schematic diagram in the conventional art;

Fig. 2 is the SOI-LIGBT device architecture schematic diagram in the embodiment of the invention;

Among the figure, 1 is that N-type buffering area, 2 is that P type tagma, 3 is that deep-well region, 4 is that oxide layer, 5 is that drain terminal electrode, 6 is that source electrode, 7 is that grid termination electrode, 8 is that isolation channel, 9 is that epitaxial loayer, 10 is that metal structure, 11 is p type buried layer.

Embodiment

Traditional LIGBT device is by introducing the RESURF technology, and the field plate of its source, leakage, grid carries out smoothly the high peak electric field of the formation such as oxygen place, device surface field, place, drift region, so that electric field convergence distributed rectangular more, realizes higher withstand voltage; But in the ON state process, the electric current line mainly flows from device surface, and the electric current in its tagma is less, has caused certain waste; For this problem, the present invention proposes a kind of novel SOI-LIGBT device, by increasing p type buried layer, and the filling material in the isolation channel is converted to the filling polysilicon by the body silicon in the tradition, isolation channel is linked to each other with the grid termination electrode by metal structure, thereby with its gate electrode as the device-side direction, make it both can be used as a kind of grid field plate, near the electric field that dwindles channel region reaches withstand voltage requirement, simultaneously conduct is gate electrode longitudinally, so that electric current is except flowing on the surface, also can below the p type buried layer in device tagma, flow, increase current capacity, reduce conducting resistance, and then can guarantee that reduction of device is in the size of Width under the withstand voltage condition.

The solution of the present invention is further described below in conjunction with drawings and Examples:

SOI-LIGBT device in this example is 11um at epitaxy layer thickness, and oxygen buried layer thickness is on SOI (silicon-on-insulator) material of 1um, uses 0.5 μ m high pressure CDMOS technique and realizes.As shown in Figure 2, it comprise N-type buffering area 1, P type tagma 2, deep-well region 3, oxide layer 4, be located at deep-well region 3 the outside and and deep-well region 3 between spaced isolation channel 8 and the epitaxial loayer 9 adjacent with isolation channel 8; Draw drain terminal electrode 5 from described N-type buffering area 1, the end of grid termination electrode 7 is positioned on the oxide layer 4 and with oxide layer 4 and contacts; Draw source electrode 6 from described deep-well region 3; Below described P type tagma 2, also be provided with the buried regions 11 that contacts with described deep-well region 3 with P type tagma 2; Described isolation channel 8 links to each other with described grid termination electrode 7 by metal structure 10; Adopt polysilicon to fill in the described isolation channel 8.

Its operation principle is: in OFF state, isolation channel and grid are all received earth potential, so the withstand voltage and traditional LIGBT of this structure is basically identical, isolation channel can serve as the field plate of side direction for improving near the electric field of channel region longitudinally; In ON state, isolation channel and grid are received the 5V power supply, and this moment, the channel region that grid is opened P type tagma formed transversal I GBT at horizontal direction, and electric current flows through from the surface, and is similar with traditional LIGBT; Simultaneously, because isolation channel has served as the second gate level, at longitudinal direction, formed equally an IGBT structure, voltage is opened vertical IGBT raceway groove of P type tagma and deep-well region formation in the isolation channel, and electric current flows through the tagma from the p type buried layer below; Be that device architecture in this example has formed two electric current lines, thereby in ON state, stronger current capacity can be arranged;

Need to prove, the length of p type buried layer, thickness and position also can obviously have influence on the characteristic of device in this structure, need to be optimized in real process.

Claims

1. with the double gate SOI of p type buried layer-LIGBT device, comprise N-type buffering area (1), P type tagma (2), deep-well region (3), oxide layer (4), be located at deep-well region (3) the outside and and deep-well region (3) between spaced isolation channel (8) and the epitaxial loayer (9) adjacent with isolation channel (8); The end of grid termination electrode (7) is positioned at oxide layer (4) and upward and with oxide layer (4) contacts; From described N-type buffering area (1), draw drain terminal electrode (5); Draw source electrode (6) from described deep-well region (3); It is characterized in that, also be provided with the p type buried layer (11) that contacts with described deep-well region (3) with P type tagma (2) in the below in described P type tagma (2); Described isolation channel (8) links to each other with described grid termination electrode (7) by metal structure (10).

2. the double gate SOI with p type buried layer as claimed in claim 1-LIGBT device is characterized in that, adopts polysilicon to fill in the described isolation channel (8).