CN103309645B - A kind of method of additional turn function in computer digital animation instruction and CPU module - Google Patents
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Abstract
The present invention discloses a kind of method and CPU module thereof of additional turn function in computer digital animation instruction, anti-condition code and redirect vector are set in the data structure of data processing instructions, and in the instruction address calculating unit of CPU, add the treatment circuit of anti-condition code and redirect vector, achieve and data processing instructions and jump instruction are united two into one, data processing instructions is made to have turn function, make full use of the feature of instruction address calculating unit and data processor parallel work-flow, for CPU can be rapidly, executive routine code provides a kind of effective solution efficiently.The inventive method not only improves the operational efficiency of cpu resource utilization factor and program, but also makes program code compacter.
Description
Technical field
The invention belongs to computer realm, being specifically related to a kind of method of additional turn function in computer digital animation instruction, making computing machine also can synchronously perform direct redirect when performing data processing operation.The invention still further relates to the CPU module using the method.
Background technology
The CPU ware circuit of current complete set is mainly made up of parts such as ROM, instruction fetch module, order register, command decoder, program address arithmetical unit, program status register, data processing module, data read-write module and RAM, as shown in Figure 1.In FIG: (1) is ROM, for depositing programmed instruction.(2) be instruction read module, for reading the instruction that will perform from ROM.(3) be order register, for depositing the instruction performed, it is made up of operational code, condition code and several operands.(4) be command decoder, for carrying out decoding to the instruction of leaving in order register, produce instruction and performing the control signal needed.(5) be data processing module, it is under the effect of the control signal of command decoder decoding output, completes the operation of data transmission and data operation.(6) be two input AND circuit.(7) be PSW, i.e. program status register, the various status codes after the store data process of the inside.(8) whether be executive condition comparer, it is the status code of condition code in comparison order register (3) and PSW, export control signal RUN_EN and control to allow to perform instruction.(9) be alternative data selector, perform according to command request selecting sequence or redirect execution under the control of code translator (4).(10) be totalizer.(11) be alternative data selector.(12) be PC, what the inside was deposited is next instruction address.(13) be data read-write module.(14) be RAM, what the inside was deposited is data.In some CPU, order register does not have condition code in (3), and it is that condition code is lain in the middle of command decoder, and its condition code is obtained from command decoder index by the operational code in order register.Found out by Fig. 1, it is worked in coordination with by the circuit block such as (3), (4), (6), (7), (8), (9), (10) that instruction address calculates, in order to express easily, instruction address calculating unit is referred to as in the combination of these (3), (4), (6), (7), (8), (9), (10) circuit block, it has been instruction address calculation function, and its result of calculation is stored in PC(12 by data selector (11)) in.Performing data processing is completed by data processing module (5).From circuit structure, above-mentioned instruction address arithmetic unit and data processing module are parallel relationship, from theory, if by specific design, be that the operation of the operation and data processing that CPU can be made to perform direct redirect is synchronously carried out, but existing CPU hardware circuit and order set all cannot realize operation that CPU performs direct redirect and the operation that performs data processing is synchronously carried out.
Existing often overlapping in the repertoire of computer is all made up of two large class instructions, and they are jump instruction and data processing instructions.Wherein jump instruction is divided into again direct jump instruction, subroutine call instruction; And data processing instructions is divided into data movement instruction, data operation instruction.These instructions division of labor is very clear and definite, function singleness.Application program is required to combine according to programmed logic computing by the instruction of these function singlenesses.As the simple C programmer code of this section below:
if(a<b)a=b+c;
else a=d+e;
f++;
In order to easy-to-understand, use popular MCS-51 assembly language to translate this section of C programmer code at this, obtain assembly routine example 1 as follows:
Assembly routine example 1:
Line number label assembly instruction (wherein A is totalizer, and C is carry flag)
1 C001: MOV A,a,
2 C002: CLR C;
3 C003: SUBB A,b;
4 C004: JNC C009;
5 C005: MOV A,b;
6 C006: ADD A,c;
7 C007: MOV a,A，
8 C008: JMP C00C;
9 C009: MOV A,d;
10 C00A: ADD A,e;
11 C00B: MOV a,A;
12 C00C: INC f;
As can be seen from assembly routine example the 1,1st above, 2,3,5,6,7,9,10,11,12 row are data processing instructions, these data processing instructions can only allow CPU do relevant data and transmit and the operation of data operation, and can only sequentially perform; 4th row and eighth row are jump instructions, and this jump instruction can only do the operation of programming jump, and programmed logic needs the place of redirect that jump instruction will be used, and CPU data processing module when performing jump instruction is idle, and resource has wasted.
Summary of the invention
The first object of the present invention is a kind of method providing additional turn function in computer digital animation instruction, making CPU also can synchronously perform direct redirect when performing data processing operation, the feature of instruction address arithmetic unit and data processing module parallel work-flow can be made full use of.
The second object of the present invention is to provide the cpu circuit module realizing said method, solves the deficiency that existing computer instruction execution efficiency is low.
First object of the present invention realizes by following technical measures: a kind of method of additional turn function in computer digital animation instruction, sets up an anti-condition code and a redirect vector in the data structure of the data processing instructions of active computer;
Condition code is included in the data structure of the data processing instructions of active computer, described condition code is the executive condition of data processing operation, only at PSW(program status register) in status code when mating the condition code of this instruction, data processing operation could perform, otherwise data processing operation just can not perform, this condition code and anti-condition code are formed in the executive condition of turn function additional in data processing instructions jointly;
The executive condition that described anti-condition code is used to indicate turn function additional in data processing instructions is identical or contrary with the condition code in this instruction, if the same represents same conditional jump, if contrary, represents anti-conditional jump;
And the signal of the status code of described anti-condition code and PSW whether matching condition code will follow the logical operation relation in truth table 1, deciding turn function additional in data processing instructions is that order performs or redirect performs;
Truth table 1
| Anti-condition code PSW status code whether matching condition code | Turn function performs selection |
| Do not mate with condition | Order performs |
| Same Condition Matching | Redirect |
| Anti-condition is not mated | Redirect |
| Anti-Condition Matching | Order performs |
Described redirect vector is for changing the numerical value of programmable counter (i.e. PC), and it for adding direction and the distance that turn function provides redirect in data processing instructions.
Second object of the present invention realizes by following technical measures: a kind of CPU module using said method, the treatment circuit of anti-condition code and redirect vector is set up in the instruction address calculating unit of CPU, allow the instruction address calculating unit of CPU can with perform the circuit block parallel work-flow of data processing operation, and instruction address calculating unit presses the logical operation in truth table 1;
Truth table 1
| Anti-condition code PSW status code whether matching condition code | Turn function performs selection |
| Do not mate with condition | Order performs |
| Same Condition Matching | Redirect |
| Anti-condition is not mated | Redirect |
| Anti-Condition Matching | Order performs |
The present invention is ingenious arranges anti-condition code and redirect vector in the data structure of data processing instructions, and in the instruction address calculating unit of CPU, add the treatment circuit of anti-condition code and redirect vector, achieve and data processing instructions and jump instruction are united two into one, data processing instructions is made to have turn function, make full use of the feature of instruction address calculating unit and data processor parallel work-flow, for CPU can rapidly, efficiently executive routine code a kind of effective solution is provided.The inventive method not only improves the operational efficiency of cpu resource utilization factor and program, but also makes program code compacter.
Accompanying drawing explanation
Fig. 1 is existing CPU ware circuit theory of constitution schematic diagram;
Fig. 2 is the CPU ware circuit theory of constitution schematic diagram using the inventive method.
Embodiment
The inventive method specifically comprises: 1, in the data structure of the data processing instructions of computing machine, set up the operand that is called as redirect vector, this redirect vector is for changing PC(and programmable counter) numerical value, thus provide direction and the distance of redirect for turn function additional in data processing instructions; The operand of condition code is included in the data structure of 2, the data processing instructions of active computer, only at PSW(program status register) in status code when mating the condition code of this instruction, data processing operation could perform, and this condition code is also one of executive condition of additional turn function in data processing instructions; 3, in the data structure of the data processing instructions of computing machine, the operand that one is called as anti-condition code is set up, the executive condition that this anti-condition code is used to indicate turn function additional in data processing instructions is identical or contrary with the condition code in this instruction, if the same same conditional jump is represented, if contrary, represent anti-conditional jump, this condition code and anti-condition code are formed in the executive condition of turn function additional in data processing instructions jointly; 4, operational code, condition code, anti-condition code, redirect vector and other several operands should be included in the data structure of data processing instructions; The signal of 5, described anti-condition code and PSW status code whether matching condition code will follow the logical operation relation in truth table 1, and deciding turn function additional in data processing instructions is that order performs or redirect performs;
Truth table 1
| Anti-condition code PSW status code whether matching condition code | Turn function executable operations |
| Do not mate with condition | Order performs |
| Same Condition Matching | Redirect |
| Anti-condition is not mated | Redirect |
| Anti-Condition Matching | Order performs |
after above-mentioned technical method process, data processing instructions has not been the data processing instructions of simple function, and should be referred to as the data processing instructions with turn function.Now this data structure with the data processing instructions of turn function is as shown in table 2.
Table 2 has the data processing instructions data structure of turn function
| Operational code | Condition code | F | Operand 1 | Operand 2 | Operand 3 | Redirect vector |
Wherein F is anti-condition code, and redirect vector is the vector of relative PC redirect, and operand more than 3, also may may be less than 3 according to the requirement of reality.
In table 2, because this has the limited bits of the redirect vector in the data processing instructions of turn function, cannot do long apart from direct redirect, so need long special length still will be used to have come apart from direct jump instruction apart from the occasion of direct redirect running into, these special length just do redirect apart from direct jump instruction, do not do data processing, therefore can the operand 1 in the instructions data structures in above-mentioned table 2, operand 2, operand 3 and redirect vector are combined and form long jump vector, thus can realize long apart from direct redirect, these length comprise special direct jump instruction and subroutine call instruction apart from direct jump instruction, its instructions data structures is as shown in table 3.
The instruction of table 3 long jump and subroutine call instruction data structure
| Operational code | Condition code | F | Long jump vector |
Wherein F is anti-condition code, and must be same conditional jump, and long jump vector is the vector of relative PC redirect.
In addition, although interrupt service routine call instruction, subroutine return instruction and interrupt service routine link order are all belong to indirect redirect, but its essence is the category belonging to data movement instruction, the destination register that just data transmit is PC, so these instructions belong to data processing instructions, its data structure is identical with table 2.
According to truth table 1, if definition F=0 is expressed as same conditional jump, F=1 is expressed as anti-conditional jump, RUN_EN=0 is expressed as PSW status code mismatch condition code, RUN_EN=1 is expressed as PSW status code matching condition code, it is 0 that turn function selecting sequence performs, and it is 1 that turn function selects redirect to perform, then can obtain truth table 4. by truth table 1
Truth table 4
| FRUN_EN | Turn function executable operations |
| 00 | 0 |
| 01 | 1 |
| 10 | 1 |
| 11 | 0 |
Corresponding to the data structure of table 2, table 3 and the logical relation of truth table 4, the treatment circuit having anti-condition code and redirect vector is increased in the instruction address calculating unit of CPU ware circuit, allow the instruction address calculating unit of CPU can with perform the circuit block parallel work-flow of data processing, and the logical operation making instruction address arithmetic unit can realize in truth table 4.Its CPU ware circuit as shown in Figure 2.
In fig. 2, form CPU hardware circuit parts to have: (1) is ROM, for depositing programmed instruction.(2) be instruction read module, for reading the instruction that will perform from ROM.(3) be order register, for depositing the instruction performed, it is made up of operational code, several operands, redirect vector, condition code and anti-condition code F, its data structure and table 2, table 3 correspondence.(4) be command decoder, for carrying out decoding to the operational code left in order register, produce instruction and performing the control signal needed.(5) be data processing module, it is under the effect of the control signal of command decoder output, completes transmission and the arithmetic operation of data.(6) be two inputs and door.(7) be PSW, i.e. program status register, the various status codes after the store data process of the inside.(8) be executive condition comparer, it judges PSW status code whether matching condition code, if PSW status code matching condition code, then and the control signal RUN_EN=1 that exports of executive condition comparer, otherwise the control signal RUN_EN=0 that executive condition comparer exports.(9) be alternative data selector, the redirect vector that the PC increment performed for selecting sequence or redirect perform.(10) be totalizer, it has been the signed number additional calculation of instruction address.(11) be alternative data selector, the instruction address value that the instruction address value exported for selecting totalizer (10) or data processing module (5) export.(12) be PC, what the inside was deposited is next instruction address.(13) be data read-write module.(14) be RAM, what the inside was deposited is data.(15) be alternative data selector.(16) be two input XOR gate.Wherein, instruction address calculating unit is made up of the circuit block such as (3), (4), (6), (7), (8), (9), (10), (15), (16).The treatment circuit of anti-condition code and redirect vector is included in this instruction address calculating unit, and make the instruction address calculating unit of CPU can with perform the circuit block parallel work-flow of data processing, and instruction address arithmetic unit can realize the logical operation in truth table 4.
In fig. 2, the processing procedure with the data processing instructions of turn function is: by PC(12) instruction address that provides, instruction fetch module (2) read be stored in ROM(1) in computer instruction and deliver in order register (3), wherein the opcode field of order register (3) is used for index instruction code translator (4), is provided the execution control signal of this instruction by command decoder (4); The condition-code field of order register (3) and PSW(program status register) status code of (7) is sent to executive condition comparer (8), to judge at PSW(7) in the condition code of status code whether in matching instruction register (3), if PSW status code matching condition code, then control signal RUN_EN=1, otherwise control signal RUN_EN=0.Data processing module (5) is delivered on this RUN_EN signal one tunnel, whether can perform data processing operation with control data processing module (5); Another road RUN_EN signal and command decoder (4) export direct redirect control signal and deliver to two inputs and door (6), jointly to determine the selection of redirect vector: if instruction is special jump instruction, then data selector (15) will select long jump vector (being namely made up of the operand 1 of order register, operand 2, the field such as operand 3 and redirect vector); If data processing instructions, then the redirect vector field in data selector (15) selection instruction register (3), the operand 1 of order register (3), operand 2, operand 3 deliver to data processing module, carry out data processing operation.The anti-condition-code field of a road RUN_EN signal and order register (3) delivers to two input XOR gate (16) again, jointly to determine that instruction is that order performs or redirect performs: if anti-condition code is same conditional jump (i.e. F=0), and status code does not mate this condition code (i.e. RUN_EN=0), then data selector (9) will choose the order provided by command decoder (4) to perform PC increment; If anti-condition code is same conditional jump (i.e. F=0), and status code mates this condition code (i.e. RUN_EN=1), then data selector (9) will choose the redirect vector that data selector (15) exports; If anti-condition code is anti-conditional jump (i.e. F=1), and status code does not mate this condition code (i.e. RUN_EN=0), then data selector (9) will choose the redirect vector exported by data selector (15); If anti-condition code is anti-conditional jump (i.e. F=1), and status code mates this condition code (i.e. RUN_EN=1), then data selector (9) will choose the order provided by command decoder (4) to perform PC increment.The instruction address that the vector PC register (12) exported by data selector (9) exports is delivered to totalizer (10) and is carried out signed number additive operation, obtains direction and the distance of relative PC redirect.If instruction is not indirect jump instruction, then data selector (11) will choose the data that totalizer (10) exports, and send into PC register (12), otherwise, if instruction is indirect jump instruction, then data selector (11) will choose the data that data processing module (5) exports, and send in PC register (12).
Here must illustrate: if F and RUN_EN adopts other level to define in truth table 4, then affect the logic form of circuit (16), but the logical relation in truth table 1 will be followed; Further, if the instruction length uniform specification of all computing machines, then order performs PC increment will be a constant.
After being implemented by above-mentioned technical method, corresponding to the instructions data structures of table 2, these assembly language formats with the data processing instructions of turn function are as follows:
Operational code [condition code] [operand 1], [operand 2], [operand 3], [F] [JMP label]
Note observing this assembly instruction form, find to have had more " [F] [JMP label] " field than now traditional data processing instructions assembly language format, this field is exactly for describing turn function.Wherein F is anti-condition code memonic symbol, and JMP is redirect memonic symbol, and label is that PC wants the instruction address label of redirect (noting: label herein simply can not be equal to the redirect vector in table 3).If F is concealed, then represent same conditional jump, namely redirect executive condition is identical with the condition code of operational code suffix; If F is manifested, then represent anti-conditional jump, namely the condition code of redirect executive condition and operational code suffix is contrary.If have ready conditions code in data processing instructions operational code suffix, then must there is " [F] JMP label " field, because the data processing instructions affirmative Shi You branch redirect of code of having ready conditions; If do not have condition-code field in data processing instructions operational code suffix, then represent that the operation of operational code instruction always performs, programmer should determine whether retaining " [F] JMP label " field the need of redirect according to program.
In order to correct understanding has the meaning of " [F] [JMP label] " field in the assembly language format of the data processing instructions of turn function, present connected applications example, and according to the logical relation in truth table 1, listing 4 kinds may the usage of this assembly language format in situations:
Situation 1: code of having ready conditions, same to conditional jump.
How to use under illustrating this situation:
Example (1): MOVC A, b, JMP C009;
Being meant to of this statement: if condition C equals 1 establishment, then synchronously perform MOV A, b and JMP C009; Be false if condition C equals 1, then do not perform MOV A, b, also do not perform JMP C009, PC automatically sensing order perform next instruction.
Situation 2: code of having ready conditions, anti-conditional jump.
How to use under illustrating this situation:
Example (2): MOVC A, b, FJMP C009;
Being meant to of this statement: if condition C equals 1 establishment, then only perform MOV A, b, does not perform FJMP C009, and PC next instruction of performing of sensing order automatically; Be false if condition C equals 1, then do not perform MOV A, b, only perform FJMP C009.
Situation 3: unconditional code, same to conditional jump.
In this case operational code suffix does not have condition code, and presentation directives always performs.How to use under illustrating this situation:
Example (3): MOV A, b, JMP C009;
Being meant to of this statement: always synchronously perform MOV A, b and JMP C009.
Situation 4: unconditional code, anti-conditional jump.
How to use under illustrating this situation:
Example (4): MOV A, b, FJMP C009;
This situation needs special instruction, owing to being that operational code suffix does not have condition code, be meant to not limit by condition, so its anti-condition is exactly the completely limited meaning, so being meant to of this statement: unconditionally perform MOV A, b, PC next instruction of performing of sensing order automatically, performs FJMP C009 never.In this case, for the ease of reading, " FJMP label " field in assembly instruction memonic symbol need not have been write, but the anti-condition code in this instructions data structures remains 1, namely represents anti-conditional jump.Assembly instruction memonic symbol in example (4) can be write as: MOV A, b.
The assembly language format amendment assembly routine example 1 of what present use was above-mentioned the have data processing instructions of turn function, obtains assembly routine example 2.
Assembly routine example 2:
Line number label assembly instruction (wherein A is totalizer, and C is carry flag)
1 C001: MOV A,a,
2 C002: CLR C;
3 C003: SUBB A,b;
4 C005:MOVC A, b, FJMP C009; / * notes: MOVC be not herein MCS-51 instruction set MOVC*/
5 C006: ADD A,c;
6 C007: MOV a,A，JMP C00C;
7 C009: MOV A,d;
8 C00A: ADD A,e;
9 C00B: MOV a,A;
10 C00C: INC f;
Analyze assembly routine example 2 above, and contrast assembly routine example 1, can find out that the 4th row instruction of assembly routine example 2 is merged by the 4th row of assembly routine example 1 and the 5th row to get; 6th row instruction of assembly routine example 2 is merged by the 7th row of assembly routine example 1 and eighth row to get, and programmed logic does not change, but has used 2 jump instructions less.As can be seen here, after using technical scheme of the present invention, program code becomes compact, and execution efficiency also improves.
After being implemented by above-mentioned technical method, corresponding to the instructions data structures of table 3, the assembly language format of these long jump instructions is as follows:
Operational code [condition code] label
Because long jump instruction comprises direct jump instruction and subroutine call instruction, below illustrate the usage of these long distance jump instructions.
For direct jump instruction, its example application is:
Example (5): JC C009;
Being meant to of this statement: if condition C equals 1 establishment, then perform J C009, and namely current PC jumps to C009 place relatively; Be false if condition C equals 1, then PC automatically sensing order perform next instruction.
For subroutine call instruction, its example application is:
Example (6): CALLZ C009;
Being meant to of this statement: if condition Z equals 1 establishment, then perform CALL C009, and namely current PC calls C009 virgin program relatively; Be false if Z equals 1, then PC automatically sensing order perform next instruction.
Although interrupt service routine call instruction, subroutine return instruction and interrupt service routine link order are all belong to indirect redirect, but its essence is the category belonging to data movement instruction, the destination register that just data transmit is PC, so these instructions are also belong to data processing instructions, its data structure is identical with the above-mentioned data structure (table 2) with the data processing instructions of turn function, assembly language format is also the same, just need not list one by one at this.
Embodiments of the present invention are not limited thereto; according to foregoing of the present invention; utilize ordinary technical knowledge and the customary means of this area; do not departing under above-mentioned basic fundamental thought prerequisite of the present invention; the present invention can also make the amendment of other various ways, replacement or change, all drops within rights protection scope of the present invention.
Claims (2)
1. in computer digital animation instruction, add a method for turn function, it is characterized in that:
An anti-condition code and a redirect vector is set up in the data structure of the data processing instructions of active computer;
Condition code is included in the data structure of the data processing instructions of active computer, described condition code is the executive condition of data processing instructions, when status code only in program status register mates the condition code of this instruction, data processing instructions could perform, otherwise data processing instructions just can not perform, this condition code and described anti-condition code are formed in the executive condition of turn function additional in data processing instructions jointly;
The executive condition that described anti-condition code is used to indicate turn function additional in data processing instructions is identical or contrary with the condition code in this instruction, if the executive condition of turn function is identical with the condition code in this instruction, represent same conditional jump, if the executive condition of turn function and the condition code in this instruction are on the contrary, represent anti-conditional jump;
And the signal of status code in described anti-condition code and program status register whether matching condition code will follow the logical operation relation in truth table 1, deciding turn function additional in data processing instructions is that order performs or redirect performs;
Truth table 1
Described redirect vector for changing the numerical value of programmable counter, for turn function additional in data processing instructions provides direction and the distance of redirect.
2. one kind realizes the CPU module of method described in claim 1, it is characterized in that: the treatment circuit setting up anti-condition code and redirect vector in the instruction address calculating unit of CPU, allow the instruction address calculating unit of CPU can with perform the circuit block parallel work-flow of data processing instructions, and instruction address calculating unit presses the logical operation in truth table 1;
Truth table 1
。
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| CN101493762A (en) * | 2008-01-23 | 2009-07-29 | Arm有限公司 | Instruction pre-decoding of multiple instruction sets |
| CN102708088A (en) * | 2012-05-08 | 2012-10-03 | 北京理工大学 | CPU/GPU (Central Processing Unit/ Graphic Processing Unit) cooperative processing method oriented to mass data high-performance computation |
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