CN103309645A - Method of appending skip function in computer data processing instruction and CPU (Central Processing Unit) module - Google Patents
Method of appending skip function in computer data processing instruction and CPU (Central Processing Unit) module Download PDFInfo
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Abstract
The invention discloses a method of appending a skip function in a computer data processing instruction and a CPU (Central Processing Unit) module. A reverse condition code and a skip vector are arranged in a data structure of the data processing instruction, and a processing circuit of the reverse condition code and the skip vector is added in an instruction address computation part of the CPU, so that the data processing instruction and the skip instruction are combined, thus the data processing instruction has a skip function, and parallel operation of the instruction address computation part and a data processing part is fully utilized to provide an effective solution for executing a procedure code quickly and effectively. According to the method provided by the invention, the resource utilization rate of the CPU and the operating efficiency of the procedure are improved, and the procedure code is more compact.
Description
Technical field
The invention belongs to computer realm, be specifically related to a kind of method of in the computer data processing instruction, adding turn function, make computing machine when carrying out data processing operation, also can carry out direct redirect synchronously.The invention still further relates to the CPU module of this method of use.
Background technology
When the complete CPU ware circuit of last cover mainly is by ROM, instructs parts such as read module, order register, command decoder, program address arithmetical unit, program status register, data processing module, data read-write module and RAM to constitute, as shown in Figure 1.In Fig. 1: (1) is ROM, is used for depositing programmed instruction.(2) be the instruction read module, be used for reading the instruction that to carry out from ROM.(3) be the instruction register, be used for depositing the instruction of carrying out that it is to be made of operational code, condition code and several operands.(4) be the instruction code translator, be used for the instruction of leaving order register in is deciphered, produce the control signal that instruction is carried out to be needed.(5) be data processing module, it is under the effect of the control signal of command decoder decoding output, finishes the operation of data transmission and data operation.(6) be two input AND circuit.(7) be PSW, i.e. program status register, the various status codes after the inside store data is handled.(8) be the executive condition comparer, it is condition code in the comparison order register (3) and the status code of PSW, and output control signal RUN_EN controls whether allow execution command.(9) be the alternative data selector, under the control of code translator (4), carry out still redirect according to the command request selecting sequence and carry out.(10) be totalizer.(11) be the alternative data selector.(12) be PC, what deposited the inside is next bar instruction address.(13) be data read-write module.(14) be RAM, what deposited the inside is data.In some CPU, order register does not have condition code in (3), and it is that condition code is lain in the middle of the command decoder, and its condition code is obtained from the command decoder index by the operational code in the order register.Found out by Fig. 1, it is to be worked in coordination with to finish by circuit blocks such as (3), (4), (6), (7), (8), (9), (10) that instruction address is calculated, in order to express easily, combination at these (3), (4), (6), (7), (8), (9), (10) circuit block is referred to as the instruction address calculating unit, it is to finish the instruction address calculation function, and its result of calculation is stored in PC(12 by data selector (11)) in.Carrying out the data processing is to be finished by data processing module (5).From circuit structure, above-mentioned instruction address arithmetic unit and data processing module are relations in parallel, from theory, if by specific design, be can be so that CPU carries out the operation that the operation of direct redirect and data handle to carry out synchronously, but existing C PU hardware circuit and order set all can't be realized CPU and carry out the operation of direct redirect and carry out the operation that data handle and carry out synchronously.
All be made of two big class instructions in existing every cover repertoire of computer, they are jump instruction and data processing instructions.Wherein jump instruction is divided into direct jump instruction, subroutine call instruction again; And data processing instructions is divided into data movement instruction, data operation instruction.These instruction division of labor are very clear and definite, function singleness.Computing requires to combine application program according to programmed logic by the instruction of these function singlenesses.As the simple C programmer code of following this section:
if(a<b)a=b+c;
else a=d+e;
f++;
For easy-to-understand, use popular MCS-51 assembly language at this and translate this section C programmer code, it is as follows to obtain assembly routine example 1:
Assembly routine example 1:
Row label assembly instruction (wherein A is totalizer, and C is carry flag)
1 C001: MOV A,a,
2 C002: CLR C;
3 C003: SUBB A,b;
4 C004: JNC C009;
5 C005: MOV A,b;
6 C006: ADD A,c;
7 C007: MOV a,A，
8 C008: JMP C00C;
9 C009: MOV A,d;
10 C00A: ADD A,e;
11 C00B: MOV a,A;
12 C00C: INC f;
From top assembly routine example 1 as can be seen, the 1st, 2,3,5,6,7,9,10,11,12 row are data processing instructions, and these data processing instructions can only allow CPU do the operation of relevant data transmission and data operation, and can only carry out in proper order; The 4th row and eighth row are jump instructions, and this jump instruction can only be done the operation of program redirect, and programmed logic needs the place of redirect will use jump instruction to finish, and CPU data processing module when carrying out jump instruction leaves unused, and resource has wasted.
Summary of the invention
First purpose of the present invention is to provide a kind of method of adding turn function in the computer data processing instruction, make CPU when carrying out data processing operation, also can carry out direct redirect synchronously, can take full advantage of the characteristics of instruction address arithmetic unit and data processing module parallel work-flow.
Second purpose of the present invention is the cpu circuit module that realizes said method is provided, and solves the deficiency that existing computer instruction is carried out inefficiency.
First purpose of the present invention can realize by following technical measures: a kind of in the computer data processing instruction method of additional turn function, in the data structure of the data processing instructions of active computer, set up an anti-condition code and a redirect vector;
Include condition code in the data structure of the data processing instructions of active computer, described condition code is the executive condition of data processing operation, only at the PSW(program status register) in status code when mating the condition code of this instruction, data processing operation could be carried out, otherwise data processing operation just can not be carried out, and this condition code and anti-condition code are formed in the executive condition of turn function additional in the data processing instructions jointly;
It is identical or on the contrary that described anti-condition code is used to indicate in data processing instructions the executive condition of additional turn function and the condition code in this instruction, if identical then represent with the condition redirect, if on the contrary then represent anti-condition redirect;
And the status code of described anti-condition code and the PSW whether signal of matching condition sign indicating number will be followed logical operation relation in the truth table 1, and deciding turn function additional in data processing instructions is that order is carried out or redirect is carried out;
Truth table 1
| Whether anti-condition code PSW status code the matching condition sign indicating number | Turn function is carried out and is selected |
| Do not match with condition | Order is carried out |
| Mate with condition | Redirect |
| Anti-condition does not match | Redirect |
| Anti-condition coupling | Order is carried out |
Described redirect vector is used for the numerical value of change programmable counter (being PC), and it provides direction and the distance of redirect for additional turn function in data processing instructions.
Second purpose of the present invention can realize by following technical measures: a kind of CPU module of using said method, in the instruction address calculating unit of CPU, set up the treatment circuit of anti-condition code and redirect vector, allow CPU the instruction address calculating unit can with the circuit block parallel work-flow of carrying out data processing operation, and the instruction address calculating unit is pressed the logical operation in the truth table 1;
Truth table 1
| Whether anti-condition code PSW status code the matching condition sign indicating number | Turn function is carried out and is selected |
| Do not match with condition | Order is carried out |
| Mate with condition | Redirect |
[0035]
| Anti-condition does not match | Redirect |
| Anti-condition coupling | Order is carried out |
Ingenious anti-condition code and the redirect vector of in the data structure of data processing instructions, arranging of the present invention, and in the instruction address calculating unit of CPU, increased the treatment circuit of anti-condition code and redirect vector, realized data processing instructions and jump instruction are united two into one, make data processing instructions have turn function, take full advantage of the characteristics of instruction address calculating unit and data processor parallel work-flow, for CPU can be rapidly, the executive routine code provides a kind of effective solution efficiently.The inventive method not only improves the operational efficiency of cpu resource utilization factor and program, but also makes program code compacter.
Description of drawings
Fig. 1 is existing CPU ware circuit theory of constitution synoptic diagram;
Fig. 2 is for using the CPU ware circuit theory of constitution synoptic diagram of the inventive method.
Embodiment
The inventive method specifically comprises: 1, set up an operand that is called as the redirect vector in the data structure of the data processing instructions of computing machine, it is programmable counter that this redirect vector is used for change PC() numerical value, thereby provide direction and the distance of redirect for additional turn function in data processing instructions; 2, the operand that includes condition code in the data structure of the data processing instructions of active computer, only at the PSW(program status register) in status code when mating the condition code of this instruction, data processing operation could be carried out, and this condition code also is one of executive condition of additional turn function in data processing instructions; 3, in the data structure of the data processing instructions of computing machine, set up an operand that is called as anti-condition code, it is identical or on the contrary that this anti-condition code is used to indicate in data processing instructions the executive condition of additional turn function and the condition code in this instruction, if it is identical then represent with the condition redirect, if on the contrary then represent anti-condition redirect, this condition code and anti-condition code are formed in the executive condition of turn function additional in the data processing instructions jointly; 4, in the data structure of data processing instructions, should include operational code, condition code, anti-condition code, redirect vector and other several operands; 5, described anti-condition code and PSW status code whether the signal of matching condition sign indicating number to follow logical operation relation in the truth table 1, deciding turn function additional in data processing instructions is that order is carried out or redirect is carried out;
Truth table 1
| Whether anti-condition code PSW status code the matching condition sign indicating number | The turn function executable operations |
| Do not match with condition | Order is carried out |
| Mate with condition | Redirect |
| Anti-condition does not match | Redirect |
| Anti-condition coupling | Order is carried out |
[0042]After above-mentioned technical method processing, data processing instructions has not been the data processing instructions of simple function, and should be referred to as to have the data processing instructions of turn function.This moment, this data structure of data processing instructions with turn function was as shown in table 2.
Table 2 has the data processing instructions data structure of turn function
| Operational code | Condition code | F | Operand 1 | Operand 2 | Operand 3 | The redirect vector |
Wherein F is anti-condition code, and the redirect vector is the vector of relative PC redirect, and operand may also may be less than 3 more than 3 according to the requirement of reality.
In table 2, because this has the limited bits of the redirect vector in the data processing instructions of turn function, can't do the directly redirect of long distance, so running into and length still will use special length to finish apart from direct jump instruction apart from the occasion of directly redirect, these special long distances directly jump instruction are just done redirect, not doing data handles, therefore can be the operand 1 in the director data structure in the above-mentioned table 2, operand 2, operand 3 and redirect vector merge formation long jump vector, thereby can realize the directly redirect of long distance, these long distances directly jump instruction comprise special direct jump instruction and subroutine call instruction, and its director data structure is as shown in table 3.
The instruction of table 3 long jump and subroutine call instruction data structure
| Operational code | Condition code | F | The long jump vector |
Wherein F is anti-condition code, and must be with the condition redirect, and the long jump vector is the vector of relative PC redirect.
In addition, though interrupt service routine call instruction, subroutine return instruction and interrupt service routine link order all are to belong to indirect redirect, but its essence is the category that belongs to data movement instruction, just the destination register of data transmission is PC, so these instructions belong to data processing instructions, its data structure is identical with table 2.
According to truth table 1, if definition F=0 is expressed as with the condition redirect, F=1 is expressed as anti-condition redirect, RUN_EN=0 is expressed as PSW status code mismatch condition sign indicating number, RUN_EN=1 is expressed as PSW status code matching condition sign indicating number, the turn function selecting sequence is implemented as 0, and turn function selects redirect to be implemented as 1, then can obtain truth table 4. by truth table 1
Truth table 4
| FRUN_EN | The turn function executable operations |
| 00 | 0 |
| 01 | 1 |
| 10 | 1 |
| 11 | 0 |
Corresponding to the data structure of table 2, table 3 and the logical relation of truth table 4, in the instruction address calculating unit of CPU ware circuit, increase the treatment circuit that anti-condition code and redirect vector are arranged, allow CPU the instruction address calculating unit can with carry out the circuit block parallel work-flow that data are handled, and make the instruction address arithmetic unit can realize the logical operation in the truth table 4.Its CPU ware circuit as shown in Figure 2.
In Fig. 2, forming CPU hardware circuit parts has: (1) is ROM, is used for depositing programmed instruction.(2) be the instruction read module, be used for reading the instruction that to carry out from ROM.(3) be the instruction register, be used for depositing the instruction of carrying out that it is to be made of operational code, several operands, redirect vector, condition code and anti-condition code F, its data structure and table 2, table 3 correspondence.(4) be the instruction code translator, be used for the operational code that leaves order register in is deciphered, produce the control signal that instruction is carried out to be needed.(5) be data processing module, it is under the effect of the control signal of command decoder output, finishes transmission and the arithmetic operation of data.(6) be two inputs and door.(7) be PSW, i.e. program status register, the various status codes after the inside store data is handled.(8) be the executive condition comparer, it is to judge whether matching condition sign indicating number of PSW status code, if PSW status code matching condition sign indicating number, the control signal RUN_EN=1 of executive condition comparer output then, otherwise the control signal RUN_EN=0 of executive condition comparer output.(9) be the alternative data selector, the PC increment that is used for the selecting sequence execution still is the redirect vector that redirect is carried out.(10) be totalizer, it is the signed number additional calculation of finishing instruction address.(11) be the alternative data selector, being used for selecting the instruction address value of totalizer (10) output still is the instruction address value of data processing module (5) output.(12) be PC, what deposited the inside is next bar instruction address.(13) be data read-write module.(14) be RAM, what deposited the inside is data.(15) be the alternative data selector.(16) be two input XOR gate.Wherein, the instruction address calculating unit is made up of circuit blocks such as (3), (4), (6), (7), (8), (9), (10), (15), (16).The treatment circuit that in this instruction address calculating unit, includes anti-condition code and redirect vector, and make CPU the instruction address calculating unit can with carry out the circuit block parallel work-flow that data are handled, and the instruction address arithmetic unit can be realized the logical operation in the truth table 4.
In Fig. 2, processing procedure with data processing instructions of turn function is: by PC(12) instruction address that provides, the instruction read module (2) read be stored in ROM(1) in computer instruction and deliver in the order register (3), wherein the opcode field of order register (3) is used for index instruction code translator (4), and the execution control signal of this instruction is provided by command decoder (4); The condition-code field of order register (3) and PSW(program status register) status code of (7) is sent to executive condition comparer (8), to judge at PSW(7) in the status code condition code in the matching instruction register (3) whether, if PSW status code matching condition sign indicating number, control signal RUN_EN=1 then, otherwise control signal RUN_EN=0.This RUN_EN signal one tunnel is delivered to data processing module (5), whether can carry out data processing operation with control data processing module (5); Another road RUN_EN signal and the direct redirect control signal of command decoder (4) output are delivered to two inputs and door (6), selection with common decision redirect vector: if instruction is special jump instruction, then data selector (15) will be selected long jump vector (namely being made up of the fields such as operand 1, operand 2, operand 3 and redirect vector of order register); If data processing instructions, the redirect vector field in data selector (15) the selection instruction register (3) then, the operand 1 of order register (3), operand 2, operand 3 are delivered to data processing module, carry out data processing operation.The anti-condition-code field of one road RUN_EN signal and order register (3) is delivered to two input XOR gate (16) again, instructing with common decision is that order is carried out or redirect is carried out: if anti-condition code is with condition redirect (being F=0), and status code this condition code (being RUN_EN=0) that do not match, then data selector (9) will choose the order that is provided by command decoder (4) to carry out the PC increment; If anti-condition code is with condition redirect (being F=0), and status code mates this condition code (being RUN_EN=1), and then data selector (9) will be chosen the redirect vector of data selector (15) output; If anti-condition code is anti-condition redirect (being F=1), and status code this condition code (being RUN_EN=0) that do not match, then data selector (9) will be chosen the redirect vector by data selector (15) output; If anti-condition code is anti-condition redirect (being F=1), and status code mates this condition code (being RUN_EN=1), and then data selector (9) will choose the order that is provided by command decoder (4) to carry out the PC increment.Deliver to totalizer (10) by the instruction address of the vector of data selector (9) output and PC register (12) output and carry out the signed number additive operation, obtain direction and the distance of relative PC redirect.If instruction is not indirect jump instruction, then data selector (11) will be chosen the data of totalizer (10) output, and send into PC register (12), otherwise, if instruction is indirect jump instruction, then data selector (11) will be chosen the data of data processing module (5) output, and send in the PC register (12).
Here must specify: if F and RUN_EN adopt other level definition in the truth table 4, then influence the logic form of circuit (16), but will follow the logical relation in the truth table 1; Also have, if the instruction length uniform specification of all computing machines, then carrying out the PC increment in proper order will be a constant.
After implementing by above-mentioned technical method, corresponding to the director data structure of table 2, these assembly language formats of data processing instructions with turn function are as follows:
Operational code [condition code] [operand 1], [operand 2], [operand 3], [F] [JMP label]
Note observing this assembly instruction form, find to have had more " [F] [JMP label] " field than present traditional data processing instructions assembly language format, this field is exactly to be used for describing turn function.Wherein F is anti-condition code memonic symbol, and JMP is the redirect memonic symbol, and label is the instruction address label (note: label herein can not simply be equal to the redirect vector in the table 3) that PC wants redirect.If F is concealed, represent then that with the condition redirect namely the redirect executive condition is identical with the condition code of operational code suffix; If F is manifested, then represent anti-condition redirect, namely the condition code of redirect executive condition and operational code suffix is opposite.If have ready conditions sign indicating number in the data processing instructions operational code suffix, " [F] JMP label " field then must be arranged, because the data processing instructions of the sign indicating number of having ready conditions has branch's redirect certainly; If do not have condition-code field in the data processing instructions operational code suffix, represent that then the operation of operational code indication is always carried out, the programmer should whether the needs redirect determines whether keeping " [F] JMP label " field according to program.
The meaning that has " [F] [JMP label] " field in the assembly language format of data processing instructions of turn function for correct understanding, now in conjunction with application example, and according to the logical relation in the truth table 1, list the usage of this assembly language format under 4 kinds of possibility situations:
Situation 1: the sign indicating number of having ready conditions, with the condition redirect.
Illustrate under this situation and how to use:
Example (1): MOVC A, b, JMP C009;
The meaning of this statement is: set up if condition C equals 1, then carry out MOV A synchronously, b and JMP C009; Be false if condition C equals 1, then do not carry out MOV A, b does not carry out JMP C009 yet, PC next bar instruction of carrying out in proper order of sensing automatically.
Situation 2: the sign indicating number of having ready conditions, anti-condition redirect.
Illustrate under this situation and how to use:
Example (2): MOVC A, b, FJMP C009;
The meaning of this statement is: set up if condition C equals 1, then only carry out MOV A, b does not carry out FJMP C009, and PC next bar instruction of carrying out in proper order of sensing automatically; Be false if condition C equals 1, then do not carry out MOV A, b only carries out FJMP C009.
Situation 3: unconditional sign indicating number, with the condition redirect.
The operational code suffix does not have condition code in this case, and presentation directives always carries out.Illustrate under this situation and how to use:
Example (3): MOV A, b, JMP C009;
The meaning of this statement is: always carry out MOV A synchronously, b and JMP C009.
Situation 4: unconditional sign indicating number, anti-condition redirect.
Illustrate under this situation and how to use:
Example (4): MOV A, b, FJMP C009;
This situation needs to specify, owing to be that the operational code suffix does not have condition code, the meaning is not to be subjected to condition restriction, so its anti-condition is exactly the complete limited meaning, the meaning of this statement is so: unconditionally carry out MOV A, FJMP C009 is carried out in b, PC next bar instruction of carrying out in proper order of sensing automatically never.In this case, for the ease of reading, " FJMP label " field in the assembly instruction memonic symbol need not have been write, but the anti-condition code in this director data structure remains 1, namely represents anti-condition redirect.Assembly instruction memonic symbol in the example (4) can be write as: MOV A, b.
Use the assembly language format of the above-mentioned data processing instructions with turn function to revise assembly routine example 1 now, obtain assembly routine example 2.
Assembly routine example 2:
Row label assembly instruction (wherein A is totalizer, and C is carry flag)
1 C001: MOV A,a,
2 C002: CLR C;
3 C003: SUBB A,b;
4 C005:MOVC A, b, FJMP C009; / * notes: MOVC herein be not the MCS-51 instruction set MOVC*/
5 C006: ADD A,c;
6 C007: MOV a,A，JMP C00C;
7 C009: MOV A,d;
8 C00A: ADD A,e;
9 C00B: MOV a,A;
10 C00C: INC f;
Analyze top assembly routine example 2, and contrast assembly routine example 1, the 4th of assembly routine example 2 the row instruction is to be gone to merge by the 4th row and the 5th of assembly routine example 1 to get as can be seen; The 6th row instruction of assembly routine example 2 is to be merged by the 7th row of assembly routine example 1 and eighth row to get, and programmed logic does not change, but has used 2 jump instructions less.This shows, use that program code has become compact after the technical scheme of the present invention, carry out efficient and also improved.
After above-mentioned technical method enforcement, corresponding to the director data structure of table 3, the assembly language format of these long jumps instructions is as follows:
Operational code [condition code] label
Because the long jump instruction comprises direct jump instruction and subroutine call instruction, below illustrate these long usages apart from jump instruction.
For direct jump instruction, its example application is:
Example (5): JC C009;
The meaning of this statement is: set up if condition C equals 1, then carry out J C009, namely current PC jumps to the C009 place relatively; , condition C is false then PC next bar instruction of carrying out in proper order of sensing automatically if equaling 1.
For subroutine call instruction, its example application is:
Example (6): CALLZ C009;
The meaning of this statement is: set up if condition Z equals 1, then carry out CALL C009, namely current PC is called C009 virgin program relatively; , Z is false then PC next bar instruction of carrying out in proper order of sensing automatically if equaling 1.
Though interrupt service routine call instruction, subroutine return instruction and interrupt service routine link order all are to belong to indirect redirect, but its essence is the category that belongs to data movement instruction, just the destination register of data transmission is PC, so these instructions also are to belong to data processing instructions, the data structure (table 2) of its data structure and the above-mentioned data processing instructions with turn function is identical, assembly language format also is the same, just need not list one by one at this.
Embodiments of the present invention are not limited thereto; according to foregoing of the present invention; utilize ordinary skill knowledge and the customary means of this area; do not breaking away under the above-mentioned basic fundamental thought prerequisite of the present invention; the present invention can also make modification, replacement or the change of other various ways, all drops within the rights protection scope of the present invention.
Claims (2)
1. the method for an additional turn function in the computer data processing instruction is characterized in that:
In the data structure of the data processing instructions of active computer, set up an anti-condition code and a redirect vector;
Include condition code in the data structure of the data processing instructions of active computer, described condition code is the executive condition of data processing operation, when only the status code in program status register is mated the condition code of this instruction, data processing operation could be carried out, otherwise data processing operation just can not be carried out, and this condition code and described anti-condition code are formed in the executive condition of turn function additional in the data processing instructions jointly;
It is identical or on the contrary that described anti-condition code is used to indicate in data processing instructions the executive condition of additional turn function and the condition code in this instruction, if the executive condition of turn function is identical with condition code in this instruction then represent with the condition redirect, if the condition code in the executive condition of turn function and this instruction on the contrary then represent anti-condition redirect;
And the status code in described anti-condition code and the program status register whether signal of matching condition sign indicating number will be followed logical operation relation in the truth table 1, and deciding turn function additional in data processing instructions is that order is carried out or redirect is carried out;
Truth table 1
Described redirect vector is used for the numerical value of change programmable counter, for additional turn function in data processing instructions provides direction and the distance of redirect.
2. CPU module that realizes the described method of claim 1, it is characterized in that: the treatment circuit of in the instruction address calculating unit of CPU, setting up anti-condition code and redirect vector, allow CPU the instruction address calculating unit can with the circuit block parallel work-flow of carrying out data processing instructions, and the instruction address calculating unit is pressed the logical operation in the truth table 1;
Truth table 1
。
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