CN103293728A - Liquid crystal display - Google Patents
Liquid crystal display Download PDFInfo
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- CN103293728A CN103293728A CN2012103759043A CN201210375904A CN103293728A CN 103293728 A CN103293728 A CN 103293728A CN 2012103759043 A CN2012103759043 A CN 2012103759043A CN 201210375904 A CN201210375904 A CN 201210375904A CN 103293728 A CN103293728 A CN 103293728A
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- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 53
- 230000002093 peripheral effect Effects 0.000 claims abstract description 244
- 238000009413 insulation Methods 0.000 claims abstract description 83
- 229910052751 metal Inorganic materials 0.000 claims description 81
- 239000002184 metal Substances 0.000 claims description 81
- 239000000758 substrate Substances 0.000 claims description 21
- 230000000694 effects Effects 0.000 abstract description 10
- 239000003990 capacitor Substances 0.000 abstract description 3
- 230000001934 delay Effects 0.000 abstract 2
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 238000000034 method Methods 0.000 description 7
- 239000010409 thin film Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000002294 plasma sputter deposition Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical group [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000013077 target material Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
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Abstract
The invention discloses a liquid crystal display which comprises control capacitance electrodes, wherein an insulation layer is arranged between the control capacitance electrodes and peripheral leads; the control capacitance electrodes, the peripheral leads and the insulation layer between the control capacitance electrodes and the peripheral leads form control capacitors; and the capacitance of the ith control capacitor formed by the ith peripheral lead and the corresponding control capacitance electrode is Ci0, can compensate the signal delay of the ith peripheral lead, so that the signal delays of the ith peripheral lead and the longest nth peripheral lead are the same, finally the signal delays of all the peripheral leads and the signal delay of the longest nth peripheral lead are the same, the liquid crystal display is prevented from cross grains, and the display effect is improved.
Description
Technical field
The invention belongs to field of liquid crystal display, relate in particular to a kind of liquid crystal indicator.
Background technology
Informationized society more and more needs frivolous portable display device, and the most ripe current product be exactly liquid crystal indicator (Liquid Crystal Display, LCD).
But, existing LCD in display frame, the time regular meeting band appears, reduced the display effect of LCD.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of liquid crystal indicator, band occurs, the problem that display effect is not good to solve existing liquid crystal indicator.
This liquid crystal indicator comprises:
Viewing area and outer peripheral areas, be provided with many drive wires and pel array in described viewing area, be provided with many peripheral leads in described outer peripheral areas, described many drive wires are connected with peripheral leads respectively, described many peripheral leads are respectively the 1st peripheral leads, the 2nd peripheral leads, the 3rd peripheral leads ... the i peripheral leads ... the n peripheral leads, described n peripheral leads is the longest peripheral leads of length, corresponding with it, described many drive wires are respectively the 1st drive wire, the 2nd drive wire, the 3rd drive wire ... the i drive wire ... the n drive wire, it is characterized in that, also comprise:
Adjust capacitance electrode, be provided with insulation course between described adjustment capacitance electrode and the peripheral leads, described adjustment capacitance electrode, peripheral leads and the insulation course between the two constitute adjusts electric capacity, and the capacitance that the i that described i peripheral leads and corresponding adjustment capacitance electrode constitute adjusts electric capacity is C
I0, and
Wherein, described l
nBe the length of n peripheral leads, described l
N'Be the length of n drive wire, described l
iBe the length of i peripheral leads, described l
I'Be the length of i drive wire, the width of all peripheral leads is w, and the width of all drive wires is w ', and the stray capacitance of all drive wires is C
N '
Preferably, described peripheral leads is arranged on the first metal layer, and described adjustment capacitance electrode is arranged on second metal level, and is provided with first insulation course between described the first metal layer and second metal level.
Preferably, described peripheral leads is arranged on second metal level, and described adjustment capacitance electrode is arranged on the first metal layer, and is provided with first insulation course between described the first metal layer and second metal level.
Preferably, described the first metal layer is arranged on the substrate surface, and described insulation course is first insulation course.
Preferably, described peripheral leads is arranged on the first metal layer, and described adjustment capacitance electrode is arranged on transparency conducting layer, and be disposed with first insulation course between described the first metal layer and the transparency conducting layer, second metal level and second insulation course.
Preferably, described the first metal layer is arranged on the substrate surface, and described insulation course comprises first insulation course and second insulation course.
Preferably, described peripheral leads is arranged on second metal level, and described adjustment capacitance electrode is arranged on transparency conducting layer, and is provided with second insulation course between described second metal level and the transparency conducting layer.
Preferably, described second metal level is arranged on first surface of insulating layer, and described insulation course is second insulation course.
Preferably, described peripheral leads is arranged on the first metal layer and second metal level, described adjustment capacitance electrode is arranged on transparency conducting layer, and is provided with first insulation course between described the first metal layer and second metal level, is provided with second insulation course between described second metal level and the transparency conducting layer.
Preferably, described the first metal layer is arranged on the substrate surface, and described insulation course is second insulation course.
Preferably, described peripheral leads is divided into grid peripheral leads and data peripheral leads, and described grid peripheral leads all is connected with the driving chip with the data peripheral leads.
Preferably, described peripheral leads is divided into grid peripheral leads and data peripheral leads, and described grid peripheral leads is connected with grid drive chip, and described data peripheral leads is connected with data driving chip.
Preferably, the width of described adjustment capacitance electrode is not less than w.
Preferably, described adjustment capacitance electrode is to utilize the making step of described pel array to form.
By such scheme as can be known, the liquid crystal indicator that the application provides also comprises, adjust capacitance electrode, and be provided with insulation course between described adjustment capacitance electrode and the peripheral leads, described adjustment capacitance electrode, peripheral leads and the insulation course between the two constitute adjusts electric capacity, and the capacitance that the i that described i peripheral leads and corresponding adjustment capacitance electrode constitute adjusts electric capacity is C
I0, and
Then the capacitance of described i adjustment electric capacity is C
I0Can compensate the signal delay amount of i peripheral leads, make that the signal delay amount of i peripheral leads is suitable with the signal delay amount of the longest n peripheral leads, all the signal delay amount with the longest n peripheral leads is suitable finally to make the signal delay amount of all peripheral leads, prevent that band from appearring in liquid crystal indicator, improve display effect.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do to introduce simply to the required accompanying drawing that will use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is a kind of liquid crystal indicator synoptic diagram that the embodiment of the present application provides;
Fig. 2 is the sectional view of a kind of liquid crystal indicator of providing of the embodiment of the present application;
Fig. 3 is the sectional view of the another kind of liquid crystal indicator that provides of the embodiment of the present application;
Fig. 4 is the sectional view of another liquid crystal indicator of providing of the embodiment of the present application;
Fig. 5 is the sectional view of another liquid crystal indicator of providing of the embodiment of the present application;
Fig. 6 is the sectional view of another liquid crystal indicator of providing of the embodiment of the present application.
Embodiment
For purpose, technical scheme and the advantage of the embodiment of the invention is clearer, below in conjunction with the accompanying drawing in the embodiment of the invention, technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
Just as stated in the Background Art, existing LCD in display frame, the time regular meeting band appears, reduced the display effect of LCD.
The inventor finds after deliberation, existing liquid crystal indicator comprises viewing area and outer peripheral areas, be provided with many drive wires and pel array in described viewing area, be provided with many peripheral leads in described outer peripheral areas, described many drive wires are connected with peripheral leads respectively, because path difference, the length difference of described peripheral leads, then the meeting of the resistance of peripheral leads and electric capacity is variant, and the resistance of described peripheral leads and electric capacity are along with the increase of the increase of length.And the signal delay amount of pel array is
Wherein, R is the all-in resistance of respective peripheral lead-in wire and the drive wire that is attached thereto, C is the total capacitance of respective peripheral lead-in wire and the drive wire that is attached thereto, and the electric capacity of all drive wires is all identical and fixing with resistance, therefore, the signal delay amount of peripheral leads can be along with the increase of the resistance of peripheral leads and electric capacity and is increased, so the signal delay amount of pel array can be called the signal delay amount of peripheral leads again.Because the difference of signal delay amount, then the demonstration of viewing area also can produce band along with the difference of signal delay amount, and then has reduced display effect.
Therefore, the inventor has proposed a kind of liquid crystal indicator, this liquid crystal indicator comprises: viewing area and outer peripheral areas, be provided with many drive wires and pel array in described viewing area, be provided with many peripheral leads in described outer peripheral areas, described many drive wires are connected with peripheral leads respectively, described many peripheral leads are respectively the 1st peripheral leads, the 2nd peripheral leads, the 3rd peripheral leads ... the i peripheral leads ... the n peripheral leads, described n peripheral leads is the longest peripheral leads of length, corresponding with it, described many drive wires are respectively the 1st drive wire, the 2nd drive wire, the 3rd drive wire ... the i drive wire ... the n drive wire, and described liquid crystal indicator also comprises:
Adjust capacitance electrode, be provided with insulation course between described adjustment capacitance electrode and the peripheral leads, described adjustment capacitance electrode, peripheral leads and the insulation course between the two constitute adjusts electric capacity, and the capacitance that the i that described i peripheral leads and corresponding adjustment capacitance electrode constitute adjusts electric capacity is C
I0, and
Wherein, described l
nBe the length of n peripheral leads, described l
N'Be the length of n drive wire, described li is the length of i peripheral leads, and described li' is the length of i drive wire, and the width of all peripheral leads is w, and the width of all drive wires is w ', and the stray capacitance of all drive wires is Cn '.
Then the capacitance of described i adjustment electric capacity is the signal delay amount that Ci0 can compensate the i peripheral leads, make that the signal delay amount of i peripheral leads is suitable with the signal delay amount of the longest n peripheral leads, all the signal delay amount with the longest n peripheral leads is suitable finally to make the signal delay amount of all peripheral leads, prevent that band from appearring in liquid crystal indicator, improve display effect.
It more than is the application's core concept, below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that obtains under the creative work prerequisite,
All belong to the scope of protection of the invention.
A lot of details have been set forth in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here and implement, those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public specific embodiment.
The embodiment of the invention discloses a kind of liquid crystal indicator, as shown in Figure 1, this LCD comprises:
Adjust capacitance electrode, described adjustment capacitance electrode is corresponding one by one with the 1st ~ (n-1) peripheral leads, is respectively that the 1st whole capacitance electrode S1, the 2nd whole capacitance electrode, the 3rd are adjusted capacitance electrode accordingly ... i adjusts capacitance electrode Si ... (n-1) adjusts capacitance electrode.
Be provided with insulation course between described adjustment capacitance electrode and the peripheral leads, and described adjustment capacitance electrode, peripheral leads and the insulation course between the two constitute adjusts electric capacity, and the capacitance that the i that described i peripheral leads Li and corresponding i adjustment capacitance electrode Si constitute adjusts electric capacity is C
I0, and
Wherein, described l
nBe the length of n peripheral leads Ln, described l
N 'Be the length of n drive wire Ln ', described l
iBe the length of i peripheral leads Li, described l
I 'Be the length of i drive wire Li ', the width of all peripheral leads is w, and the width of all drive wires is w', and the stray capacitance of all drive wires is C
N'
Because the signal delay amount of pel array is
And R is the all-in resistance of i peripheral leads Li and the i drive wire Li' that is attached thereto, and C is the total capacitance that i peripheral leads Li and the i corresponding with i peripheral leads Li adjust capacitance electrode Si and i drive wire Li ', then R=R
i+ R
I ', C=C
i+ C
I'+ C
I0
Wherein, R
iBe the resistance of i peripheral leads Li, R
I'Be the resistance of i drive wire Li ', C
I 'Be the electric capacity of i peripheral leads Li, C
I'Be the electric capacity of i drive wire Li ', and the electric capacity of all drive wires is C
N ', C then
I'=C
N'
The i.e. signal delay amount of i peripheral leads Li
The adjustment capacitance electrode that n peripheral leads Ln is not corresponding, therefore the signal delay amount of n peripheral leads Ln
And, the electric capacity of peripheral leads be by form between the peripheral leads or peripheral leads and viewing area in transparency electrode on the color filter film form, spacing is generally about 3 μ m ~ 4 μ m between them; And the electric capacity of drive wire is that other electrodes of thin film transistor (TFT) form in drive wire and the viewing area, the spacing order of magnitude is 2000 dusts ~ 5000 dusts, namely about 0.2 μ m ~ 0.5 μ m, as seen, the electrode separation of peripheral leads electric capacity generally is tens times of electrode separation that show drive wire electric capacity, therefore, and in actual computation, according to the electric capacity computing formula, peripheral leads electric capacity can be ignored.
The signal delay amount of i peripheral leads Li then
The signal delay amount of n peripheral leads Ln
And the resistivity of peripheral leads and drive wire metal is ρ, and the thickness of n peripheral leads Ln is d
n, the thickness of i peripheral leads Li is d
i, the thickness of n drive wire Ln ' is d
N ', the thickness of i drive wire Li' is d
I', and d
n=d
i=d
N'=d
I', the resistance of n peripheral leads Ln then
The resistance of i peripheral leads Li
The resistance of n drive wire Ln '
The resistance of i drive wire Li'
And because
Then
Namely
τ then
i=τ
n, namely the signal delay amount of i peripheral leads Li equates with the signal delay amount of n peripheral leads Ln.
As seen, the capacitance of described i adjustment electric capacity is C
I0Can compensate the signal delay amount of i peripheral leads, make that the signal delay amount of i peripheral leads is suitable with the signal delay amount of the longest n peripheral leads, all the signal delay amount with the longest n peripheral leads is suitable finally to make the signal delay amount of all peripheral leads, prevent that band from appearring in liquid crystal indicator, improve display effect.
Another embodiment of the application discloses a kind of concrete liquid crystal indicator, and as shown in Figure 2, this liquid crystal indicator comprises:
Be arranged on a substrate 1 lip-deep the first metal layer, in outer peripheral areas, peripheral leads is divided into grid peripheral leads and data peripheral leads, described grid peripheral leads is connected with grid drive chip, described data peripheral leads is connected with data driving chip, perhaps, described grid peripheral leads all is connected with the driving chip with the data peripheral leads, and described driving chip has the function of grid drive chip and data driving chip concurrently.And described peripheral leads (being illustrated as i peripheral leads Li) is arranged on the first metal layer.In the viewing area, the grid of pel array and many drive wires also are arranged on the first metal layer, and the grid of described peripheral leads, pel array and many drive wires form through identical deposition and lithography step simultaneously.
Cover lip-deep first insulation course 2 of described the first metal layer.
Be arranged on described first insulation course, 2 lip-deep second metal levels, in outer peripheral areas, described adjustment capacitance electrode (be illustrated as i and adjust capacitance electrode Si) is arranged on second metal level, and described i adjusts capacitance electrode Si and described i peripheral leads Li overlaps mutually, and the width of described adjustment capacitance electrode is not less than the width w of peripheral leads, then the overlapping width of described adjustment capacitance electrode and respective peripheral lead-in wire is w, and described adjustment capacitance electrode is to utilize the making step of described pel array to form, concrete, data line (or the source electrode of described adjustment capacitance electrode and pel array, drain electrode) forms through identical deposition and lithography step simultaneously.
Described i adjusts capacitance electrode Si and described i peripheral leads Li and first insulation course 2 between the two and constitutes i adjustment capacitor C
I0, and
Wherein, described l
nBe the length of n peripheral leads, described l
N'Be the length of n drive wire, described l
iBe the length of i peripheral leads Li, described l
I'Be the length of i drive wire Li ', the width of all peripheral leads is w, and the width of all drive wires is w', and the stray capacitance of all drive wires is C
N '
If the specific inductive capacity of the insulation course (being first insulation course 2 in the present embodiment) between described peripheral leads and the adjustment capacitance electrode is ξ, the thickness of first insulation course 2 is that d(is that the distance that i adjusts between capacitance electrode Si and the i peripheral leads Li is d), the width that i adjusts capacitance electrode Si is w, and described i adjusts capacitance electrode Si and described i peripheral leads Li is overlapping fully, because
Then the length L of described i adjustment capacitance electrode Si satisfies:
Wherein, be ξ
0Be permittivity of vacuum.That is, described i adjusts the satisfied then τ of length L of capacitance electrode Si
i=τ
nCondition, namely the signal delay amount of i peripheral leads Li equates with the signal delay amount of n peripheral leads.
Then the capacitance of described i adjustment electric capacity is C
I0Can compensate the signal delay amount of i peripheral leads, make that the signal delay amount of i peripheral leads is suitable with the signal delay amount of the longest n peripheral leads, all the signal delay amount with the longest n peripheral leads is suitable finally to make the signal delay amount of all peripheral leads, prevent that band from appearring in liquid crystal indicator, improve display effect.
In addition, described liquid crystal indicator also comprises second insulation course 3 that is arranged on described second layer on surface of metal, and described second insulation course 3 surfaces are provided with transparency conducting layer 4.
The another embodiment of the application discloses another liquid crystal indicator, and this liquid crystal indicator comprises:
Be arranged on the first metal layer on the substrate surface;
Be arranged on lip-deep first insulation course of described the first metal layer;
Be arranged on second metal level on described first surface of insulating layer;
Be arranged on second insulation course and the transparency conducting layer that is arranged on described second surface of insulating layer on described second layer on surface of metal.
Be with above-described embodiment difference:
As shown in Figure 3, the peripheral leads of the disclosed liquid crystal indicator of present embodiment (as i peripheral leads Li) is arranged on second metal level, and described adjustment capacitance electrode (adjusting capacitance electrode Si as i) is arranged on the first metal layer.And the insulation course between described adjustment capacitance electrode and the peripheral leads is for being arranged on lip-deep first insulation course of described the first metal layer.
Perhaps, as shown in Figure 4, described peripheral leads (as i peripheral leads Li) is arranged on the first metal layer, and described adjustment capacitance electrode (adjusting capacitance electrode Si as i) is arranged on transparency conducting layer, and be disposed with first insulation course, second metal level and second insulation course between described the first metal layer and the transparency conducting layer, and described second metal level and peripheral leads and adjustment capacitance electrode there is no overlapping, therefore, the insulation course between described peripheral leads and the adjustment capacitance electrode comprises first insulation course and second insulation course.
Perhaps, as shown in Figure 5, described peripheral leads (as i peripheral leads Li) is arranged on second metal level, and described adjustment capacitance electrode (adjusting capacitance electrode Si as i) is arranged on transparency conducting layer, and described second insulation course is the insulation course between peripheral leads and the adjustment capacitance electrode.
Perhaps, as shown in Figure 6, described peripheral leads is arranged on the first metal layer and second metal level, Li is arranged on the first metal layer as the i peripheral leads, (i+1) peripheral leads L(i+1) is arranged on second metal level, then under the certain situation of peripheral leads sum, described peripheral leads is arranged on the first metal layer and second metal level can reduce the shared space of peripheral leads, makes the frame of described liquid crystal indicator narrower.Described adjustment capacitance electrode (adjusting capacitance electrode Si and (i+1) adjustment capacitance electrode S(i+1 as i)) is arranged on transparency conducting layer, then the insulation course between described adjustment capacitance electrode and peripheral leads is second insulation course, or the insulation course between described adjustment capacitance electrode and peripheral leads comprises first insulation course and second insulation course.
In above-described embodiment, described adjustment capacitance electrode is to utilize the making step of described pel array to form.
The another embodiment of the application discloses a kind of method for making of above-mentioned liquid crystal indicator, is arranged on the first metal layer with peripheral leads, and adjusting capacitance electrode, to be arranged on second metal level be example, and this method comprises:
Substrate is provided, forms the first metal layer at described substrate surface, and the first metal layer is carried out etching, form gate line and grid in the viewing area, form peripheral leads in outer peripheral areas.
Concrete, described substrate is glass substrate or the substrate of other materials.
Forming gate line, grid and peripheral leads at described substrate surface specifically comprises:
Adopt the plasma sputtering mode to form the first metal layer at described substrate surface, namely at first described substrate is put into reaction chamber, energetic particle hits has highly purified target material solid plate, by the physical process knock-on atom, these are passed vacuum by knocking-on atom, be deposited on substrate surface at last, obtain the first metal layer.But the formation of the first metal layer is not limited in the plasma sputtering mode, can also utilize other physical vapor deposition mode to form, and is not described in detail at this.And then the first metal layer carried out photoetching, i.e. spin coating photoresist on described the first metal layer, form photoresist layer, utilization has gate line, the mask of grid and peripheral leads pattern exposes, form gate line at photoresist layer, grid and peripheral leads pattern, after developing, form gate line at photoresist layer, grid and peripheral leads figure, to have gate line, the photoresist layer of grid and peripheral leads figure is mask, obtain gate line through technologies such as dry etching or wet etchings, grid and peripheral leads, namely described peripheral leads forms through identical step simultaneously with gate line and the grid of viewing area pel array.
Need to prove, " gate line, grid and peripheral leads pattern " described in the present embodiment is gate line, grid and the peripheral leads pattern in the lip-deep two dimension of photoresist layer, area of the pattern is only limited to the photoresist layer surface and does not extend under the surface, does not have three-dimensional shape; Described " gate line, grid and peripheral leads figure " for to have the three-dimensional picture of three-dimensional shape, the thickness of this figure is the thickness of photoresist layer.
Form first insulation course at gate line, grid, peripheral leads and substrate surface, position corresponding with grid on described first surface of insulating layer forms semiconductor layer.
Concrete, adopt the chemical vapor deposition mode to form first insulation course at described gate line, grid, peripheral leads and substrate surface, namely the substrate that at first surface is provided with gate line, grid and peripheral leads is put into reaction chamber, gas precursors is transferred to substrate surface and carries out suction-operated and reaction, accessory substance with reaction removes then, obtains first insulation course.But the formation of first insulation course is not limited in the chemical vapor deposition mode, can also utilize other modes such as physical vapor deposition to form, and is not described in detail at this.Described first insulation course is silicon nitride layer, and forms amorphous silicon layer by identical technology at first surface of insulating layer, and amorphous silicon layer is carried out photoetching, forms semiconductor layer in the position corresponding with grid.
Form second metal level at semiconductor layer and first surface of insulating layer, and second metal level is carried out etching, form data line, source electrode, drain electrode, public electrode wire and adjustment capacitance electrode.
Described source electrode and drain electrode electricity are isolated, described source electrode, drain electrode and described semiconductor layer, grid has constituted the thin film transistor (TFT) in the pel array together, every data line is electrically connected with the source electrode of two thin film transistor (TFT)s respectively, wherein, the thin film transistor (TFT) difference that different data lines is electrically connected, the grid of two thin film transistor (TFT)s that are electrically connected with same data line is electrically connected with different gate line respectively, and, article three, data line and two gate lines intersections have surrounded two main pixel regions and two six pixel regions that main pixel region is included, two main pixel regions are arranged along first direction, three pixel regions in each main pixel region are arranged along second direction, article two, public electrode wire corresponds respectively to two main pixel regions, a plurality of main pixel regions have formed the pel array in the liquid crystal indicator viewing area, and described peripheral leads is connected with gate line with described data line, and namely described data line and gate line are the drive wire in the liquid crystal indicator viewing area.Described adjustment capacitance electrode and peripheral leads be corresponding (except the longest peripheral leads) one by one, and the two is overlapping fully, and namely the width of described adjustment capacitance electrode and respective peripheral lead-in wire is w, and the length L that described i adjusts capacitance electrode satisfies:
Wherein, be ξ
0Be permittivity of vacuum, ξ is described peripheral leads and the specific inductive capacity of adjusting the insulation course (being first insulation course in the present embodiment) between the capacitance electrode, d is described peripheral leads and the thickness of adjusting the insulation course (being first insulation course in the present embodiment) between the capacitance electrode, described l
nBe the length of n peripheral leads (the longest peripheral leads), described l
N'Be the length of n drive wire (drive wire corresponding with described n peripheral leads can be gate line or data line in the present embodiment), described l
iBe the length of i peripheral leads, described l
I'Be the length of i drive wire, the width of all drive wires is w ', and the stray capacitance of all drive wires is C
N'
Then described i adjusts the satisfied then τ of length L of capacitance electrode Si
i=τ
nCondition, namely the signal delay amount of i peripheral leads Li equates with the signal delay amount of n peripheral leads Ln.That is, the capacitance of described i adjustment electric capacity is C
I0Can compensate the signal delay amount of i peripheral leads, make that the signal delay amount of i peripheral leads is suitable with the signal delay amount of the longest n peripheral leads, all the signal delay amount with the longest n peripheral leads is suitable finally to make the signal delay amount of all peripheral leads, prevent that band from appearring in liquid crystal indicator, improve display effect.
Form second insulation course described according to line, source electrode, drain electrode, public electrode wire, adjustment capacitance electrode and first surface of insulating layer, described second insulation course is carried out etching, form via hole.
Concrete, adopt chemical vapor deposition method to form second insulation course described according to line, source electrode, drain electrode, public electrode wire, adjustment capacitance electrode and first surface of insulating layer, afterwards, adopt photoetching process to form via hole in described second insulation course, described via hole is positioned at second insulation course of drain electrode top.
Form transparent electrode layer at described second surface of insulating layer, described transparent electrode layer is carried out etching, form pixel electrode.
Concrete, adopt physical vapor deposition process to form transparent electrode layer at described second surface of insulating layer, described transparent electrode layer is preferably indium tin oxide layer or indium zinc oxide layer, afterwards, adopt photoetching process to form pixel electrode at transparent electrode layer, described pixel electrode is electrically connected with described drain electrode by the via hole that is positioned at second insulation course.
Various piece adopts the mode of going forward one by one to describe in this instructions, and what each part stressed is and the difference of other parts that identical similar part is mutually referring to getting final product between the various piece.
To the above-mentioned explanation of the disclosed embodiments, this area professional and technical personnel can be realized maybe will using the present invention.Multiple modification to these embodiment will be apparent concerning those skilled in the art, and defined General Principle can realize under the situation that does not break away from the spirit or scope of the present invention in other embodiments herein.Therefore, the present invention will can not be restricted to embodiment illustrated herein, but will meet the wideest scope consistent with principle disclosed herein and features of novelty.
Claims (14)
1. liquid crystal indicator, comprise: viewing area and outer peripheral areas, be provided with many drive wires and pel array in described viewing area, be provided with many peripheral leads in described outer peripheral areas, described many drive wires are connected with peripheral leads respectively, described many peripheral leads are respectively the 1st peripheral leads, the 2nd peripheral leads, the 3rd peripheral leads ... the i peripheral leads ... the n peripheral leads, described n peripheral leads is the longest peripheral leads of length, corresponding with it, described many drive wires are respectively the 1st drive wire, the 2nd drive wire, the 3rd drive wire ... the i drive wire ... the n drive wire, it is characterized in that, also comprise:
Adjust capacitance electrode, be provided with insulation course between described adjustment capacitance electrode and the peripheral leads, described adjustment capacitance electrode, peripheral leads and the insulation course between the two constitute adjusts electric capacity, and the capacitance that the i that described i peripheral leads and corresponding adjustment capacitance electrode constitute adjusts electric capacity is C
I0, and
Wherein, described l
nBe the length of n peripheral leads, described l
N 'Be the length of n drive wire, described l
iBe the length of i peripheral leads, described l
I'Be the length of i drive wire, the width of all peripheral leads is w, and the width of all drive wires is w ', and the stray capacitance of all drive wires is C
N '
2. according to the described liquid crystal indicator of claim 1, it is characterized in that described peripheral leads is arranged on the first metal layer, described adjustment capacitance electrode is arranged on second metal level, and is provided with first insulation course between described the first metal layer and second metal level.
3. according to the described liquid crystal indicator of claim 1, it is characterized in that described peripheral leads is arranged on second metal level, described adjustment capacitance electrode is arranged on the first metal layer, and is provided with first insulation course between described the first metal layer and second metal level.
4. according to claim 2 or 3 described liquid crystal indicators, it is characterized in that described the first metal layer is arranged on the substrate surface, and described insulation course is first insulation course.
5. according to the described liquid crystal indicator of claim 1, it is characterized in that, described peripheral leads is arranged on the first metal layer, and described adjustment capacitance electrode is arranged on transparency conducting layer, and be disposed with first insulation course between described the first metal layer and the transparency conducting layer, second metal level and second insulation course.
6. according to the described liquid crystal indicator of claim 5, it is characterized in that described the first metal layer is arranged on the substrate surface, and described insulation course comprises first insulation course and second insulation course.
7. according to the described liquid crystal indicator of claim 1, it is characterized in that described peripheral leads is arranged on second metal level, described adjustment capacitance electrode is arranged on transparency conducting layer, and is provided with second insulation course between described second metal level and the transparency conducting layer.
8. according to the described liquid crystal indicator of claim 7, it is characterized in that described second metal level is arranged on first surface of insulating layer, and described insulation course is second insulation course.
9. according to the described liquid crystal indicator of claim 1, it is characterized in that, described peripheral leads is arranged on the first metal layer and second metal level, described adjustment capacitance electrode is arranged on transparency conducting layer, and be provided with first insulation course between described the first metal layer and second metal level, be provided with second insulation course between described second metal level and the transparency conducting layer.
10. according to the described liquid crystal indicator of claim 9, it is characterized in that described the first metal layer is arranged on the substrate surface, described insulation course is second insulation course.
11., it is characterized in that described peripheral leads is divided into grid peripheral leads and data peripheral leads according to the described liquid crystal indicator of claim 1, and described grid peripheral leads is connected with the driving chip all with the data peripheral leads.
12. according to the described liquid crystal indicator of claim 1, it is characterized in that, described peripheral leads is divided into grid peripheral leads and data peripheral leads, and described grid peripheral leads is connected with grid drive chip, and described data peripheral leads is connected with data driving chip.
13., it is characterized in that the width of described adjustment capacitance electrode is not less than w according to the described liquid crystal indicator of claim 1.
14., it is characterized in that described adjustment capacitance electrode is to utilize the making step of described pel array to form according to the described liquid crystal indicator of claim 1.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017118076A1 (en) * | 2016-01-04 | 2017-07-13 | 京东方科技集团股份有限公司 | Array substrate, display panel, display apparatus and display method |
| CN107291283A (en) * | 2016-04-05 | 2017-10-24 | 上海和辉光电有限公司 | Contact panel and display device for display device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000056724A (en) * | 1998-08-04 | 2000-02-25 | Fujitsu Ltd | Display device |
| JP2002049055A (en) * | 2001-06-13 | 2002-02-15 | Hitachi Ltd | Liquid crystal display device |
| CN1628263A (en) * | 2002-06-07 | 2005-06-15 | 三星电子株式会社 | Thin film transistor array panel |
| CN101477976A (en) * | 2009-01-23 | 2009-07-08 | 友达光电股份有限公司 | Display panel with signal reaction time homogenized and manufacturing method thereof |
| CN101847639A (en) * | 2009-03-27 | 2010-09-29 | 北京京东方光电科技有限公司 | Array substrate and manufacturing method thereof |
-
2012
- 2012-09-28 CN CN201210375904.3A patent/CN103293728B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000056724A (en) * | 1998-08-04 | 2000-02-25 | Fujitsu Ltd | Display device |
| JP2002049055A (en) * | 2001-06-13 | 2002-02-15 | Hitachi Ltd | Liquid crystal display device |
| CN1628263A (en) * | 2002-06-07 | 2005-06-15 | 三星电子株式会社 | Thin film transistor array panel |
| CN101477976A (en) * | 2009-01-23 | 2009-07-08 | 友达光电股份有限公司 | Display panel with signal reaction time homogenized and manufacturing method thereof |
| CN101847639A (en) * | 2009-03-27 | 2010-09-29 | 北京京东方光电科技有限公司 | Array substrate and manufacturing method thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017118076A1 (en) * | 2016-01-04 | 2017-07-13 | 京东方科技集团股份有限公司 | Array substrate, display panel, display apparatus and display method |
| US10311814B2 (en) | 2016-01-04 | 2019-06-04 | Boe Technology Group Co., Ltd. | Array substrate, display panel, display device and display method |
| CN107291283A (en) * | 2016-04-05 | 2017-10-24 | 上海和辉光电有限公司 | Contact panel and display device for display device |
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| CN103293728B (en) | 2016-08-31 |
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