CN103280176A - Vertical shifting register, control method thereof, IC (Integrated Circuit) chip and TFT (Thin Film Transistor) panel - Google Patents
Vertical shifting register, control method thereof, IC (Integrated Circuit) chip and TFT (Thin Film Transistor) panel Download PDFInfo
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Abstract
The embodiment of the invention provides a vertical shifting register, a control method thereof, an IC (Integrated Circuit) chip and a TFT (Thin Film Transistor) panel. The vertical shifting register can be connected with the IC chip through a control line; an initial shifting signal required by a level-one shifting register unit of the vertical shifting register can be directly provided by the control line; and reset signals required by a level-two shifting register unit to a level-N shifting register unit of the vertical shifting register can be provided by the control line through an inverter. Therefore, the control line quantity is reduced; the occupied space for layout and wiring design is decreased; and moreover, the arrangement of the control line on the outermost side of a VSR (Vertical Shift Register) circuit can be prevented, so that the generation of ESD (Electronic Static Discharge) is effectively prevented.
Description
Technical field
The present invention relates to Thin Film Transistor (TFT) LCD (TFT-LCD) technical field, relate in particular to a kind of vertical transfer register and control method thereof, IC chip and TFT panel.
Background technology
At present, on Thin Film Transistor (TFT) (TFT) panel, can include: comprise a plurality of pixel electrodes effective display area (AA) district (can represent with AA), be used for the TFT that each pixel electrode of AA district connects is carried out vertical transfer register (VSR) that switch controls and for VSR provides integrated circuit (IC) chip (can represent with IC) of signal, the structure of TFT panel can be as shown in Figure 1.
The structural representation of existing VSR can be as shown in Figure 2, VSR can comprise the shift register cell (SR) of a plurality of cascades, and in each SR, included reset circuit, so VSR needs the IC chip that initial shift signal (GSP) and reset signal (RESET) are provided.In the prior art, the IC chip is respectively VSR by two signal line GSP signal and RESET signal is provided, and therefore can cause taking more placement-and-routing design (Layout) space.When the placement-and-routing that carries out the VSR circuit designed, the GSP signal wire can be arranged on the outermost of VSR circuit, causes the generation of electrostatic discharge (ESD) easily.
Simultaneously, because the device that existing VSR uses is more, cause circuit power consumption bigger, and can cause TFT panel periphery circuit light transmission rate less, if adopt no shadow glue (UV glue) as fluid sealant (Seal glue), can make the curing of UV glue be affected, exist UV glue to solidify fully, perhaps, though can solidify fully, reach and solidify the long problem of time that needs fully.
Summary of the invention
The embodiment of the invention provides a kind of vertical transfer register and control method, IC chip and TFT panel, is used for reducing taking of VSR circuit layout wires design space, reduces the generation of ESD.
A kind of vertical transfer register, described vertical transfer register comprise that described N is the positive integer greater than 1 from the 1st grade of shift register cell to the N level shift register cell N level shift register cell of cascade successively, wherein:
The shift signal input end of the 1st grade of shift register cell is connected by the output terminal of control line with the integrated circuit (IC) chip;
Each grade shift register cell in the 2nd grade of shift register cell to the N level shift register cell, reset terminal is connected with the output terminal of reverser, and the input end of reverser is connected by the output terminal of described control line with the integrated circuit (IC) chip.
A kind of method that aforesaid vertical transfer register is controlled, described method comprises:
The control signal of the output terminal of integrated circuit (IC) chip output is imported the shift signal input end of the 1st grade of shift register cell as initial shift signal, the signal of this control signal after reverse imported the reset terminal of the 2nd grade of every grade of shift register cell in shift register cell to the N level shift register cell as reset signal.
A kind of integrated circuit (IC) chip, the output terminal of described IC chip connects aforesaid vertical transfer register, provides control signal to described vertical transfer register.
A kind of Thin Film Transistor (TFT) TFT panel, described TFT panel comprises aforesaid vertical transfer register.
The scheme that provides according to the embodiment of the invention, vertical transfer register can be connected with the IC chip by a control line, the initial shift signal that the 1st grade of shift register cell of vertical transfer register needs can directly be provided by this control line, the reset signal that the 2nd grade of shift register cell to the N level of vertical transfer register shift register cell needs can be provided through reverser by this control line, thereby reduce control line quantity, reduce taking of placement-and-routing design space, and can avoid control line is arranged on the outermost of VSR circuit, prevent that effectively ESD from producing.
Description of drawings
The TFT panel construction synoptic diagram that Fig. 1 provides for prior art;
The structural representation of the VSR that Fig. 2 provides for prior art;
The structural representation of the VSR that Fig. 3 provides for the embodiment of the invention one;
The connection diagram of the VSR that Fig. 4 provides for the embodiment of the invention one;
The circuit diagram symbol that Fig. 5 provides for the embodiment of the invention one;
The circuit diagram symbol that Fig. 6 provides for the embodiment of the invention one;
The 1st grade of shift register cell structural representation that Fig. 7 provides for the embodiment of the invention one;
The j level shift register cell structural representation that Fig. 8 provides for the embodiment of the invention one;
The i level shift register cell structural representation that Fig. 9 provides for the embodiment of the invention one;
The sequential synoptic diagram that Figure 10 provides for the embodiment of the invention two.
Embodiment
Need two signal wires to provide reset signal and initial shift signal to VSR respectively at IC chip in the prior art, cause taking more Layout space, and when designing in the placement-and-routing that carries out the VSR circuit, the GSP signal wire can be arranged on the outermost of VSR circuit, the problem that causes the generation of ESD easily, the embodiment of the invention proposes and can provide reset signal and initial shift signal in conjunction with reverser to VSR by a signal wire by the IC chip, thereby reduce signal wire quantity, reduce the Layout space hold, and avoid signal wire is arranged on the outermost of VSR circuit, reduce the generation of ESD.
Describe below in conjunction with Figure of description and the present invention program of each embodiment.
Embodiment one,
The embodiment of the invention one provides a kind of vertical transfer register, the structure of this vertical transfer register can be as shown in Figure 3, comprise from the 1st grade of shift register cell to the N level shift register cell N level shift register cell of cascade successively and (use SR1 successively, SR2 ... SRN represents), described N is the positive integer greater than 1, wherein:
The shift signal input end of the 1st grade of shift register cell is connected by the output terminal of control line with integrated circuit (IC) chip (can represent with IC);
Each grade shift register cell in the 2nd grade of shift register cell to the N level shift register cell, reset terminal is connected with the reverser output terminal of (can represent with INV) (being the tip of Nverter circuit schematic symbol among Fig. 3), and the input end of reverser (being the wide end of Nverter circuit schematic symbol among Fig. 3) is connected by the output terminal of described control line with the integrated circuit (IC) chip.
Concrete, the connection diagram of the vertical transfer register that present embodiment provides can (specifically provide the connection diagram of 4 grades of shift register cells of the 1st grade of shift register cell to the of vertical transfer register) as shown in Figure 4 among Fig. 4, wherein, the output terminal of IC chip can be used S﹠amp by the signal that control line provides; R represents that first clock signal input terminal represents that with CLKA first clock signal represents that with CLK1 the second clock signal input part represents that with CLKB the second clock signal is represented with CLK2:
The first clock signal input terminal CLKA of described the 1st grade of shift register cell receives first clock signal clk 1, and second clock signal input part CLKB receives second clock signal CLK2.Certainly, the shift signal input end of the 1st grade of shift register cell (can represent with In1) is connected by the output terminal of control line with the integrated circuit (IC) chip.As shown in Figure 4, in the present embodiment, the drive output of the 1st grade of shift register cell can be represented with GOUT1.
I level shift register cell in described the 2nd grade of shift register cell to the N level shift register cell, the shift signal input end of each i level shift register cell (can represent with Ini) is connected with the shift signal output terminal (can represent with NEXTi-1) of i-1 level shift register cell, the first clock signal input terminal CLKA receives first clock signal clk 1, second clock signal input part CLKB receives second clock signal CLK2, wherein, i is for greater than 1 odd number that is not more than N.Certainly, the reset terminal of each i level shift register cell (reset terminal can be represented with XRESET) is connected with the output terminal of reverser (can represent with INV), and the input end of reverser is connected by the output terminal of described control line with the integrated circuit (IC) chip.As shown in Figure 4, in the present embodiment, the drive output of i level shift register cell can be represented with GOUTi.
J level shift register cell in the 2nd grade of shift register cell to the N level shift register cell, the shift signal input end of each j level shift register cell (can represent with Inj) is connected with the shift signal output terminal (can represent with NEXTj-1) of j-1 level shift register cell, the first clock signal input terminal CLKA receives second clock signal CLK2, second clock signal input part CLKB receives first clock signal clk 1, wherein, j is greater than 1 even number that is not more than N.Certainly, the reset terminal of each j level shift register cell is connected with the output terminal of reverser, and the input end of reverser is connected by the output terminal of described control line with the integrated circuit (IC) chip.As shown in Figure 4, in the present embodiment, the drive output of j level shift register cell can be represented with GOUTj.
In the present embodiment, the 1st grade of shift register cell need not to comprise reset terminal, the circuit diagram symbol of the 1st grade of shift register cell can be as shown in Figure 5, wherein, first clock signal input terminal represents that with CLKA the second clock signal input part represents that with CLKB the shift signal input end is represented with IN, the shift signal output terminal represents that with NEXT drive output is represented with GOUT.
And because the 1st grade of shift register cell need not to comprise reset terminal, can reduce the device that VSR uses, the device that solves existing VSR use is more, causes circuit power consumption bigger, and can cause TFT panel periphery circuit light transmission rate less, if adopt no shadow glue (UV glue) as fluid sealant (Seal glue), can make the curing of UV glue be affected, exist UV glue to solidify fully, perhaps, though can solidify fully, reach and solidify the long problem of time that needs fully.
The circuit diagram symbol of each grade shift register cell in the 2nd grade of shift register cell to the N level shift register cell can be as shown in Figure 6, wherein, first clock signal input terminal is represented with CLKA, the second clock signal input part is represented with CLKB, the shift signal input end is represented with IN, the shift signal output terminal represents that with NEXT drive output represents that with GOUT reset terminal is represented with XRESET.
Need to prove, in order to guarantee the operate as normal of vertical transfer register, the duration of the duration of an interior high level of clock period of second clock signal and an interior high level of clock period of first clock signal is identical, interior low level duration of clock period of second clock signal is identical with interior low level duration of clock period of first clock signal, the duration of second clock signal high level in clock period is less than half of clock period, and the initial moment of first high level of second clock signal is than initial 1/2nd clock cycles of the delay moment of first high level of first clock signal.Thereby make:
Under the effect of signal, first clock signal and the second clock signal of the output of the output terminal of IC chip, the drive output of the 1st grade of shift register cell is exported high level in the second clock signal is exported the duration of the 1st high level;
Under the effect of signal, first clock signal and the second clock signal of the output of the output terminal of IC chip, the drive output of i level shift register cell is exported high level in the second clock signal is exported the duration of 2i-1 high level;
Under the effect of signal, first clock signal and the second clock signal of the output of the output terminal of IC chip, the drive output of j level shift register cell is exported high level in first clock signal is exported the duration of j/2 high level.
More excellent, in the present embodiment, the structure of the 1st grade of shift register cell can be as shown in Figure 7, comprise the first sub-reverser (can represent with INV1), the second sub-reverser (can represent with INV2), first period of the day from 11 p.m. to 1 a.m clock reverser (can represent with CKINV1), second period of the day from 11 p.m. to 1 a.m clock reverser (can represent with CKINV2), Sheffer stroke gate (can represent with NAND) and the 3rd sub-reverser (can represent with INV3), the N1 point is reduction point, wherein:
The input end of the first sub-reverser INV1 is connected with the output terminal of first period of the day from 11 p.m. to 1 a.m clock reverser CKINV1, and be connected with the output terminal of second period of the day from 11 p.m. to 1 a.m clock reverser CKINV2, the output terminal of the first sub-reverser INV1 is the shift signal output terminal, and is connected with the input end of second period of the day from 11 p.m. to 1 a.m clock reverser CKINV2;
The input end of the second sub-reverser INV2 is first clock signal input terminal, be connected with the output terminal that the first clock signal signal source is provided, the output terminal of the second sub-reverser INV2 is connected with the disable end of first period of the day from 11 p.m. to 1 a.m clock reverser CKINV1, and is connected with the Enable Pin of second period of the day from 11 p.m. to 1 a.m clock reverser CKINV2;
The input end of first period of the day from 11 p.m. to 1 a.m clock reverser CKINV1 is the shift signal input end, is connected with the output terminal of integrated circuit (IC) chip, and the Enable Pin of first period of the day from 11 p.m. to 1 a.m clock reverser CKINV1 is connected with the output terminal that the first clock signal signal source is provided;
The disable end of second period of the day from 11 p.m. to 1 a.m clock reverser CKINV2 is connected with the output terminal that the first clock signal signal source is provided;
The first input end of Sheffer stroke gate NAND is the second clock signal input part, is connected with the output terminal that second clock signal source is provided, and second input end is connected with the output terminal of the first sub-reverser INV1;
The input end of the 3rd sub-reverser INV3 is connected with the output terminal of Sheffer stroke gate NAND, and the output terminal of the 3rd sub-reverser INV3 is drive output.
More excellent, in the present embodiment, the structure of j level shift register cell can be as shown in Figure 8, comprise the first sub-reverser (can represent with INV1), the second sub-reverser (can represent with INV2), first period of the day from 11 p.m. to 1 a.m clock reverser (can represent with CKINV1), second period of the day from 11 p.m. to 1 a.m clock reverser (can represent with CKINV2), Sheffer stroke gate (can represent with NAND) and the 3rd sub-reverser (can represent with INV3) and the Thin Film Transistor (TFT) PTFT(that resets for the signal to the output of shift signal output terminal can represent with MP), the N1 point is reduction point, wherein:
The source class of PTFT is connected with the input end of first reverser, the output terminal of first period of the day from 11 p.m. to 1 a.m clock reverser CKINV1 and the output terminal of second period of the day from 11 p.m. to 1 a.m clock reverser CKINV2, the grid of PTFT is reset terminal, be connected with the output terminal of reverser, the input end of reverser is connected with the output terminal of IC chip, and the drain electrode of PTFT connects the given voltage source;
The output terminal of the first sub-reverser INV1 is the shift signal output terminal, and is connected with the input end of second period of the day from 11 p.m. to 1 a.m clock reverser CKINV2;
The input end of the second sub-reverser INV2 is first clock signal input terminal, be connected with the output terminal that second clock signal source is provided, the output terminal of the second sub-reverser INV2 is connected with the disable end of first period of the day from 11 p.m. to 1 a.m clock reverser CKINV1, and is connected with the Enable Pin of second period of the day from 11 p.m. to 1 a.m clock reverser CKINV2;
The input end of first period of the day from 11 p.m. to 1 a.m clock reverser CKINV1 is the shift signal input end, is connected with the output terminal of integrated circuit (IC) chip, and the Enable Pin of first period of the day from 11 p.m. to 1 a.m clock reverser CKINV1 is connected with the output terminal that the first clock signal signal source is provided;
The disable end of second period of the day from 11 p.m. to 1 a.m clock reverser CKINV2 is connected with the output terminal that the first clock signal signal source is provided;
The first input end of Sheffer stroke gate NAND is the second clock signal input part, is connected with the output terminal that the first clock signal signal source is provided, and second input end of Sheffer stroke gate NAND is connected with the output terminal of the first sub-reverser INV1;
The input end of the 3rd sub-reverser INV3 is connected with the output terminal of Sheffer stroke gate NAND, and the output terminal of the 3rd sub-reverser INV3 is drive output.
More excellent, in the present embodiment, the structure of i level shift register cell is (can be identical with the structure of j level shift register cell) as shown in Figure 9, comprise the first sub-reverser (can represent with INV1), the second sub-reverser (can represent with INV2), first period of the day from 11 p.m. to 1 a.m clock reverser (can represent with CKINV1), second period of the day from 11 p.m. to 1 a.m clock reverser (can represent with CKINV2), Sheffer stroke gate (can represent with NAND) and the 3rd sub-reverser (can represent with INV3) and the Thin Film Transistor (TFT) PTFT(that resets for the signal to the output of shift signal output terminal can represent with MP), the N1 point is reduction point, wherein:
The source class of PTFT is connected with the input end of first reverser, the output terminal of first period of the day from 11 p.m. to 1 a.m clock reverser CKINV1 and the output terminal of second period of the day from 11 p.m. to 1 a.m clock reverser CKINV2, the grid of PTFT is reset terminal, be connected with the output terminal of reverser, the input end of reverser is connected with the output terminal of IC chip, and the drain electrode of PTFT connects the given voltage source;
The output terminal of the first sub-reverser INV1 is the shift signal output terminal, and is connected with the input end of second period of the day from 11 p.m. to 1 a.m clock reverser CKINV2;
The input end of the second sub-reverser INV2 is first clock signal input terminal, the input end of the second sub-reverser INV2 is connected with the output terminal that the first clock signal signal source is provided, the output terminal of the second sub-reverser INV2 is connected with the disable end of first period of the day from 11 p.m. to 1 a.m clock reverser CKINV1, and is connected with the Enable Pin of second period of the day from 11 p.m. to 1 a.m clock reverser CKINV2;
The input end of first period of the day from 11 p.m. to 1 a.m clock reverser CKINV1 is the shift signal input end, is connected with the output terminal of integrated circuit (IC) chip, and the Enable Pin of first period of the day from 11 p.m. to 1 a.m clock reverser CKINV1 is connected with the output terminal that the first clock signal signal source is provided;
The disable end of second period of the day from 11 p.m. to 1 a.m clock reverser CKINV2 is connected with the output terminal that the first clock signal signal source is provided;
The first input end of Sheffer stroke gate NAND is the second clock signal input part, and the first input end of Sheffer stroke gate NAND is connected with the output terminal that second clock signal source is provided, and second input end of Sheffer stroke gate NAND is connected with the output terminal of the first sub-reverser INV1;
The input end of the 3rd sub-reverser INV3 is connected with the output terminal of Sheffer stroke gate NAND, and the output terminal of the 3rd sub-reverser INV3 is drive output.
The method of the vertical transfer register that provides below by two couples of embodiment control embodiment one describes.
Embodiment two,
The embodiment of the invention two provides a kind of control method of vertical transfer register, and the vertical transfer register that embodiment one provides is controlled, and comprising:
The control signal of the output terminal of integrated circuit (IC) chip output is imported the shift signal input end of the 1st grade of shift register cell as initial shift signal, the signal of this control signal after reverse imported the reset terminal of the 2nd grade of every grade of shift register cell in shift register cell to the N level shift register cell as reset signal.
In the method, if the 1st grade of shift register cell employing structure as shown in Figure 7, j level shift register cell adopts structure as shown in Figure 8, and i level shift register cell adopts structure as shown in Figure 9, and control signal (can be used S﹠amp; R represents), the signal of control signal after oppositely (can use xS﹠amp; R represents), the sequential relationship of first clock signal (can represent with CLK1), second clock signal (can represent with CLK2) can be as shown in figure 10.The initial moment of high level is prior to the initial moment of first high level in first clock signal in the control signal; Be later than the finish time of first high level in first clock signal finish time of control signal high level, prior to the initial moment of second high level in first clock signal, and prior to initial moment of first high level in the second clock signal.When control signal provides initial shift signal (control signal is that high level is effective) to the 1st grade of shift register cell of VSR, the signal of control signal after oppositely provides reset signal (control signal is that low level is effective) to each grade shift register cell in the 2nd grade of shift register cell to the N level shift register cell of VSR, N1 point to each grade shift register cell in the 2nd grade of shift register cell to the N level shift register cell resets, and makes the shift signal output terminal of each grade shift register cell in the 2nd grade of shift register cell to the N level shift register cell determine output low level.And the shift signal output terminal of the 1st grade of shift register cell just can determine to export high level when first clock signal is exported first high level, and making that the 1st grade of shift register cell need not reset circuit also can operate as normal.Thereby realized providing reset signal and initial shift signal to VSR simultaneously by a signal wire.In Figure 10,4 grades of shift register cells that comprise cascade successively with vertical transfer register are example, give the sequential relationship of the signal of the signal of every grade of vertical transfer register shift signal output terminal output and drive output output and control signal, first clock signal, second clock signal.
Further, the vertical transfer register that provides based on the embodiment of the invention one, the embodiment of the invention can also provide a kind of IC chip, and the vertical transfer register that provides as embodiment one is provided the output terminal of described IC chip, provides control signal to described vertical transfer register.
Further, based on the vertical transfer register that the embodiment of the invention one provides, the embodiment of the invention can also provide a kind of TFT panel, and the vertical transfer register that provides as embodiment one is provided described TFT panel.
Although described the application's preferred embodiment, in a single day those skilled in the art get the basic creative concept of cicada, then can make other change and modification to these embodiment.So claims are intended to all changes and the modification that are interpreted as comprising preferred embodiment and fall into the application's scope.
Obviously, those skilled in the art can carry out various changes and modification and the spirit and scope that do not break away from the application to the application.Like this, if these of the application are revised and modification belongs within the scope of the application's claim and equivalent technologies thereof, then the application also is intended to comprise these changes and modification interior.
Claims (10)
1. a vertical transfer register is characterized in that, described vertical transfer register comprises that described N is the positive integer greater than 1 from the 1st grade of shift register cell to the N level shift register cell N level shift register cell of cascade successively, wherein:
The shift signal input end of the 1st grade of shift register cell is connected by the output terminal of control line with the integrated circuit (IC) chip;
Each grade shift register cell in the 2nd grade of shift register cell to the N level shift register cell, reset terminal is connected with the output terminal of reverser, and the input end of reverser is connected by the output terminal of described control line with the integrated circuit (IC) chip.
2. vertical transfer register as claimed in claim 1 is characterized in that,
First clock signal input terminal of described the 1st grade of shift register cell receives first clock signal, and the second clock signal input part receives the second clock signal;
I level shift register cell in described the 2nd grade of shift register cell to the N level shift register cell, the shift signal input end of each i level shift register cell is connected with the shift signal output terminal of i-1 level shift register cell, first clock signal input terminal receives first clock signal, the second clock signal input part receives the second clock signal, wherein, i is for greater than 1 odd number that is not more than N;
J level shift register cell in described the 2nd grade of shift register cell to the N level shift register cell, the shift signal input end of each j level shift register cell is connected with the shift signal output terminal of j-1 level shift register cell, first clock signal input terminal receives the second clock signal, the second clock signal input part receives first clock signal, wherein, j is greater than 1 even number that is not more than N.
3. vertical transfer register as claimed in claim 2 is characterized in that,
Under the effect of signal, first clock signal and the second clock signal of the output of the output terminal of IC chip, the drive output of the 1st grade of shift register cell is exported high level in the second clock signal is exported the duration of the 1st high level;
Under the effect of signal, first clock signal and the second clock signal of the output of the output terminal of IC chip, the drive output of i level shift register cell is exported high level in the second clock signal is exported the duration of 2i-1 high level;
Under the effect of signal, first clock signal and the second clock signal of the output of the output terminal of IC chip, the drive output of j level shift register cell is exported high level in first clock signal is exported the duration of j/2 high level;
Wherein, the duration of the duration of an interior high level of clock period of second clock signal and an interior high level of clock period of first clock signal is identical, interior low level duration of clock period of second clock signal is identical with interior low level duration of clock period of first clock signal, the duration of second clock signal high level in clock period is less than half of clock period, and the initial moment of first high level of second clock signal is than initial 1/2nd clock cycles of the delay moment of first high level of first clock signal.
4. as claim 2 or 3 described vertical transfer registers, it is characterized in that, the 1st grade of shift register cell comprises the first sub-reverser, the second sub-reverser, first period of the day from 11 p.m. to 1 a.m clock reverser, second period of the day from 11 p.m. to 1 a.m clock reverser, Sheffer stroke gate and the 3rd sub-reverser, wherein:
The input end of the first sub-reverser is connected with the output terminal of first period of the day from 11 p.m. to 1 a.m clock reverser, and is connected with the output terminal of second period of the day from 11 p.m. to 1 a.m clock reverser, and the output terminal of the first sub-reverser is the shift signal output terminal, and is connected with the input end of second period of the day from 11 p.m. to 1 a.m clock reverser;
The input end of the second sub-reverser is first clock signal input terminal, be connected with the output terminal that the first clock signal signal source is provided, the output terminal of the second sub-reverser is connected with the disable end of first period of the day from 11 p.m. to 1 a.m clock reverser, and is connected with the Enable Pin of second period of the day from 11 p.m. to 1 a.m clock reverser;
The input end of first period of the day from 11 p.m. to 1 a.m clock reverser is the shift signal input end, is connected with the output terminal of integrated circuit (IC) chip, and the Enable Pin of first period of the day from 11 p.m. to 1 a.m clock reverser is connected with the output terminal that the first clock signal signal source is provided;
The disable end of second period of the day from 11 p.m. to 1 a.m clock reverser is connected with the output terminal that the first clock signal signal source is provided;
The first input end of Sheffer stroke gate is the second clock signal input part, is connected with the output terminal that second clock signal source is provided, and second input end is connected with the output terminal of the first sub-reverser;
The input end of the 3rd sub-reverser is connected with the output terminal of Sheffer stroke gate, and the output terminal of the 3rd sub-reverser is drive output.
5. as claim 2 or 3 described vertical transfer registers, it is characterized in that, j level shift register cell, the Thin Film Transistor (TFT) PTFT that comprises the first sub-reverser, the second sub-reverser, first period of the day from 11 p.m. to 1 a.m clock reverser, second period of the day from 11 p.m. to 1 a.m clock reverser, Sheffer stroke gate, the 3rd sub-reverser and be used for the signal that the shift signal output terminal is exported is resetted, wherein:
The source class of PTFT is connected with the input end of first reverser, the output terminal of first period of the day from 11 p.m. to 1 a.m clock reverser and the output terminal of second period of the day from 11 p.m. to 1 a.m clock reverser, the grid of PTFT is reset terminal, be connected with the output terminal of reverser, the input end of reverser is connected with the output terminal of IC chip, and the drain electrode of PTFT connects the given voltage source;
The output terminal of the first sub-reverser is the shift signal output terminal, and is connected with the input end of second period of the day from 11 p.m. to 1 a.m clock reverser;
The input end of the second sub-reverser is first clock signal input terminal, be connected with the output terminal that second clock signal source is provided, the output terminal of the second sub-reverser is connected with the disable end of first period of the day from 11 p.m. to 1 a.m clock reverser, and is connected with the Enable Pin of second period of the day from 11 p.m. to 1 a.m clock reverser;
The input end of first period of the day from 11 p.m. to 1 a.m clock reverser is the shift signal input end, is connected with the output terminal of integrated circuit (IC) chip, and the Enable Pin of first period of the day from 11 p.m. to 1 a.m clock reverser is connected with the output terminal that the first clock signal signal source is provided;
The disable end of second period of the day from 11 p.m. to 1 a.m clock reverser is connected with the output terminal that the first clock signal signal source is provided;
The first input end of Sheffer stroke gate is the second clock signal input part, is connected with the output terminal that the first clock signal signal source is provided, and second input end of Sheffer stroke gate is connected with the output terminal of the first sub-reverser;
The input end of the 3rd sub-reverser is connected with the output terminal of Sheffer stroke gate, and the output terminal of the 3rd sub-reverser is drive output.
6. as claim 2 or 3 described vertical transfer registers, it is characterized in that, i level shift register cell, the Thin Film Transistor (TFT) PTFT that comprises the first sub-reverser, the second sub-reverser, first period of the day from 11 p.m. to 1 a.m clock reverser, second period of the day from 11 p.m. to 1 a.m clock reverser, Sheffer stroke gate, the 3rd sub-reverser and be used for the signal that the shift signal output terminal is exported is resetted, wherein:
The source class of PTFT is connected with the input end of first reverser, the output terminal of first period of the day from 11 p.m. to 1 a.m clock reverser and the output terminal of second period of the day from 11 p.m. to 1 a.m clock reverser, the grid of PTFT is reset terminal, be connected with the output terminal of reverser, the input end of reverser is connected with the output terminal of IC chip, and the drain electrode of PTFT connects the given voltage source;
The output terminal of the first sub-reverser is the shift signal output terminal, and is connected with the input end of second period of the day from 11 p.m. to 1 a.m clock reverser;
The input end of the second sub-reverser is first clock signal input terminal, the input end of the second sub-reverser is connected with the output terminal that the first clock signal signal source is provided, the output terminal of the second sub-reverser is connected with the disable end of first period of the day from 11 p.m. to 1 a.m clock reverser, and is connected with the Enable Pin of second period of the day from 11 p.m. to 1 a.m clock reverser;
The input end of first period of the day from 11 p.m. to 1 a.m clock reverser is the shift signal input end, is connected with the output terminal of integrated circuit (IC) chip, and the Enable Pin of first period of the day from 11 p.m. to 1 a.m clock reverser is connected with the output terminal that the first clock signal signal source is provided;
The disable end of second period of the day from 11 p.m. to 1 a.m clock reverser is connected with the output terminal that the first clock signal signal source is provided;
The first input end of Sheffer stroke gate is the second clock signal input part, and the first input end of Sheffer stroke gate is connected with the output terminal that second clock signal source is provided, and second input end of Sheffer stroke gate is connected with the output terminal of the first sub-reverser;
The input end of the 3rd sub-reverser is connected with the output terminal of Sheffer stroke gate, and the output terminal of the 3rd sub-reverser is drive output.
7. method to controlling as the arbitrary described vertical transfer register of claim 1 ~ 6 is characterized in that described method comprises:
The control signal of the output terminal of integrated circuit (IC) chip output is imported the shift signal input end of the 1st grade of shift register cell as initial shift signal, the signal of this control signal after reverse imported the reset terminal of the 2nd grade of every grade of shift register cell in shift register cell to the N level shift register cell as reset signal.
8. method as claimed in claim 7 is characterized in that,
The initial moment of high level is prior to the initial moment of first high level in first clock signal in the control signal;
Be later than the finish time of first high level in first clock signal finish time of control signal high level, prior to the initial moment of second high level in first clock signal, and prior to initial moment of first high level in the second clock signal.
9. an integrated circuit (IC) chip is characterized in that, the output terminal of described IC chip connects as the arbitrary described vertical transfer register of claim 1 ~ 6, provides control signal to described vertical transfer register.
10. a Thin Film Transistor (TFT) TFT panel is characterized in that, described TFT panel comprises as the arbitrary described vertical transfer register of claim 1 ~ 6.
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