CN103279309B - Based on DDR control device and the method for FPGA - Google Patents
Based on DDR control device and the method for FPGA Download PDFInfo
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Abstract
The present invention proposes a kind of DDR control device based on FPGA and method, and wherein device comprises: input data buffer storage, output data buffer storage, Read-write Catrol module, DDR chip drives module and DDR chip I P core.DDR chip drives module and DDR chip I P core, Read-write Catrol module, input data buffer storage and export data buffer storage and be connected, work under DDR chip drives module work clock, for the initialization by DDR chip I P nuclear control DDR chip, according to write order or the read command of Read-write Catrol module, writing the on-chip memory write data of state from input data buffer storage, or at read states to the on-chip memory sense data exporting data buffer storage.According to the DDR control device based on FPGA of the embodiment of the present invention, simplify the operation of DDR chip, improve the work efficiency of DDR chip, increase the dirigibility of reading and writing data, make full use of the utilization that on-chip memory improves Resources on Chip.
Description
Technical field
The present invention relates to technical field of video processing, particularly propose a kind of DDR control device based on FPGA and method.
Background technology
Based on the real time video processing of FPGA, especially in the real-time process of HD video, because the content of video inputs successively, and the sheet memory space of FPGA is limited, be not enough to the data stored in a frame or even too much line number, cause utilizing the operation of previous frame data to realize, the bulk operations in even same frame such as filtering, up-sampling, down-sampling are also difficult to realize, when therefore needing better to improve Video processing effect, introducing DDR becomes a kind of selection.
The frequency of operation of DDR is different from data input and output frequency, general higher than data input and output frequency, operate many compared with RAM complexity on sheet, write reads generally also exists larger time delay, the read-write of irrational operation DDR chip can have a strong impact on the work efficiency of DDR chip, for various reasons, in comparatively complicated operation, directly use the IP kernel of DDR chip interface or DDR all not easily to realize, therefore need outside the calling of DDR control device simplification that general.
Summary of the invention
The present invention one of is intended to solve the problems of the technologies described above at least to a certain extent or at least provides a kind of useful business to select.For this reason, first object of the present invention is to propose a kind of DDR control device based on FPGA, and second object of the present invention is to propose a kind of DDR control method based on FPGA.
According to the DDR control device based on FPGA of the embodiment of the present invention, comprise: input data buffer storage, output data buffer storage, Read-write Catrol module, DDR chip drives module, DDR chip I P core, input data buffer storage, described input data buffer storage comprises at least one on-chip memory, work under input data clock, for input data bit width is converted to the data bit width of described DDR chip I P core, and stored in the on-chip memory of described input data buffer storage; Export data buffer storage, described output data buffer storage comprises at least one on-chip memory, work under output data clock, for by the on-chip memory of the data of described DDR chip I P core stored in described output data buffer storage, and the data bit width of described DDR chip I P core is converted to the wide output of outputs data bits; Read-write Catrol module, be connected with described DDR chip drives module with described input data buffer storage, described output data buffer storage, for receiving write order and read command, control described DDR chip drives module to the write of DDR chip or sense data, and read enable signal to described output data buffer storage transmission; And DDR chip drives module, described DDR chip drives module is connected with described output data buffer storage with described DDR chip I P core, described Read-write Catrol module, described input data buffer storage, work under DDR chip drives module work clock, for the initialization by DDR chip described in described DDR chip I P nuclear control, according to write order or the read command of described Read-write Catrol module, writing the on-chip memory write data of state from described input data buffer storage, or in the on-chip memory sense data of read states to described output data buffer storage.
In an embodiment of the present invention, described input data comprise input data signal, write enable signal, write finishing signal and write DDR start address low level, and described output data comprise outputting data signals and export useful signal.
In an embodiment of the present invention, described write order comprise described write enable signal, described in write finishing signal and write DDR start address, described read command comprises reading request signal, reads DDR start address, read data number and read channel numbering.
In an embodiment of the present invention, the described DDR of writing start address or described in read DDR start address and be divided into high-order and low level two parts, a described high position is for representing the address of described DDR chip-stored unit, and described low level is for representing the address of described data in described DDR chip-stored unit.
In an embodiment of the present invention, when writing state described in described DDR chip drives module enters from described idle state, described DDR chip drives module is first in and can not receives write order state, then jump to and can receive write order state, write order state can not be received described in again entering after receiving described write order, until no longer receive described write order in the described write order state that receives and complete current described write order, enter described idle state.
In an embodiment of the present invention, when described DDR chip drives module enters described read states from described idle state, described DDR chip drives module is first in and can not receives read command state, then jump to and can receive read command state, read command state can not be received described in again entering after receiving described read command, until no longer receive described read command in the described read command state that receives and complete current described read command, enter described idle state.
In an embodiment of the present invention, the number of described on-chip memory that comprises of the number of described on-chip memory that comprises of described input data buffer storage and described output data buffer storage is equal.
In an embodiment of the present invention, the input end data bit width of described input data buffer storage is identical with described input data bit width, output terminal data bit width is identical with described DDR chip I P core input end data bit width, and the input end data bit width of described output data buffer storage is identical with described DDR chip I P core output terminal data bit width, and output terminal data bit width is wide identical with described outputs data bits.
In an embodiment of the present invention, described DDR chip I P core input end data bit width is identical with output terminal data bit width.
In an embodiment of the present invention, described write enable signal, for judging that described input data are whether effective, described in write finishing signal, for judging whether described input data terminate, described output useful signal, whether effective for judging described output data.
According to the DDR control device based on FPGA of the embodiment of the present invention, simplify the operation of DDR chip, improve the work efficiency of DDR chip, increase the dirigibility of reading and writing data, make full use of the utilization that on-chip memory improves Resources on Chip.
A kind of DDR control method based on FPGA of the embodiment of the present invention, the DDR control device based on FPGA described in any one of claim 1-9 is adopted to control described DDR chip drives module, comprise the following steps: A: described Read-write Catrol module receives described write order and described read command, under input data clock, for input data bit width is converted to the data bit width of described DDR chip I P core, and stored in the on-chip memory of described input data buffer storage, B: described DDR chip drives module, works under DDR chip drives module work clock, by the initialization of DDR chip described in described DDR chip I P nuclear control, makes described DDR chip drives module enter idle state, C: when described DDR chip drives module enters idle state, according to described write order, enter the state of writing, described DDR chip is from the on-chip memory write data of described input data buffer storage under the control of described Read-write Catrol module, and then described DDR chip drives module enters described idle state, D: described Read-write Catrol module is according to described read command, send to described output data buffer storage and read enable signal, described DDR chip drives module enters read states, under DDR chip drives module work clock, described DDR chip is to the on-chip memory sense data of described output data buffer storage, described output data buffer storage is under output data clock, by the on-chip memory of the data of described DDR chip I P core stored in described output data buffer storage, and the data bit width of described DDR chip I P core is converted to the wide output of outputs data bits, then described DDR chip drives module enters described idle state.
In an embodiment of the present invention, described input data comprise input data signal, write enable signal, write finishing signal and write DDR start address low level, and described output data comprise outputting data signals and export useful signal.
In an embodiment of the present invention, described write order comprise described write enable signal, described in write finishing signal and write DDR start address, described read command comprises reading request signal, reads DDR start address, read data number and read channel numbering.
In an embodiment of the present invention, the described DDR of writing start address or described in read DDR start address and be divided into high-order and low level two parts, a described high position is for representing the address of described DDR chip-stored unit, and described low level is for representing the address of described data in described DDR chip-stored unit.
In an embodiment of the present invention, when writing state described in described DDR chip drives module enters from described idle state, described DDR chip drives module is first in and can not receives write order state, then jump to and can receive write order state, write order state can not be received described in again entering after receiving described write order, until no longer receive described write order in the described write order state that receives and complete current described write order, enter described idle state.
In an embodiment of the present invention, when described DDR chip drives module enters described read states from described idle state, described DDR chip drives module is first in and can not receives read command state, then jump to and can receive read command state, read command state can not be received described in again entering after receiving described read command, until no longer receive described read command in the described read command state that receives and complete current described read command, enter described idle state.
In an embodiment of the present invention, the number of described on-chip memory that comprises of the number of described on-chip memory that comprises of described input data buffer storage and described output data buffer storage is equal.
In an embodiment of the present invention, the input end data bit width of described input data buffer storage is identical with described input data bit width, output terminal data bit width is identical with described DDR chip I P core input end data bit width, and the input end data bit width of described output data buffer storage is identical with described DDR chip I P core output terminal data bit width, and output terminal data bit width is wide identical with described outputs data bits.
In an embodiment of the present invention, described DDR chip I P core input end data bit width is identical with output terminal data bit width.
In an embodiment of the present invention, described write enable signal, for judging that described input data are whether effective, described in write finishing signal, for judging whether described input data terminate, described output useful signal, whether effective for judging described output data.
According to the DDR control method based on FPGA of the embodiment of the present invention, simplify the operation of DDR chip, improve the work efficiency of DDR chip, increase the dirigibility of reading and writing data, make full use of the utilization that on-chip memory improves Resources on Chip.
Additional aspect of the present invention and advantage will part provide in the following description, and part will become obvious from the following description, or be recognized by practice of the present invention.
Accompanying drawing explanation
Above-mentioned and/or additional aspect of the present invention and advantage will become obvious and easy understand from accompanying drawing below combining to the description of embodiment, wherein:
Fig. 1 is the schematic diagram of the DDR control technology based on FPGA of the embodiment of the present invention;
Fig. 2 is the structural drawing of the DDR control device based on FPGA of the embodiment of the present invention;
Fig. 3 is the process flow diagram of the DDR control method based on FPGA of the embodiment of the present invention.
Embodiment
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Be exemplary below by the embodiment be described with reference to the drawings, be intended to for explaining the present invention, and can not limitation of the present invention be interpreted as.
In describing the invention, it will be appreciated that, term " " center ", " longitudinal direction ", " transverse direction ", " length ", " width ", " thickness ", " on ", D score, " front ", " afterwards ", " left side ", " right side ", " vertically ", " level ", " top ", " end " " interior ", " outward ", " clockwise ", orientation or the position relationship of the instruction such as " counterclockwise " are based on orientation shown in the drawings or position relationship, only the present invention for convenience of description and simplified characterization, instead of indicate or imply that the device of indication or element must have specific orientation, with specific azimuth configuration and operation, therefore limitation of the present invention can not be interpreted as.
In addition, term " first ", " second " only for describing object, and can not be interpreted as instruction or hint relative importance or imply the quantity indicating indicated technical characteristic.Thus, be limited with " first ", the feature of " second " can express or impliedly comprise one or more these features.In describing the invention, the implication of " multiple " is two or more, unless otherwise expressly limited specifically.
In the present invention, unless otherwise clearly defined and limited, the term such as term " installation ", " being connected ", " connection ", " fixing " should be interpreted broadly, and such as, can be fixedly connected with, also can be removably connect, or connect integratedly; Can be mechanical connection, also can be electrical connection; Can be directly be connected, also indirectly can be connected by intermediary, can be the connection of two element internals.For the ordinary skill in the art, above-mentioned term concrete meaning in the present invention can be understood as the case may be.
In the present invention, unless otherwise clearly defined and limited, fisrt feature second feature it " on " or D score can comprise the first and second features and directly contact, also can comprise the first and second features and not be directly contact but by the other characterisation contact between them.And, fisrt feature second feature " on ", " top " and " above " comprise fisrt feature directly over second feature and oblique upper, or only represent that fisrt feature level height is higher than second feature.Fisrt feature second feature " under ", " below " and " below " comprise fisrt feature immediately below second feature and tiltedly below, or only represent that fisrt feature level height is less than second feature.
As shown in Figure 1, be the schematic diagram of the DDR control technology based on FPGA according to the embodiment of the present invention.
In Fig. 1, hypothesis has 4 groups of data channel.I.e. 4 groups of input data, 4 groups of output data, 4 input data buffer storages, namely wconver and RAM shown in figure, 4 outputs buffer memory, i.e. rconver and RAM shown in figure, can be 1 group, 2 groups or many groups in fact here.Be assumed to be N group.Here N group data representation is stored in the N group data of N number of diverse location on DDR chip, and whole group of DDR control device 10 can accept the input of these N group data simultaneously, then will often organize data stored in position corresponding on DDR chip successively.Integrally, shared one and write DDR start address writing N group data channel in process, therefore first data of every segment data of different pieces of information passage need at least one input data clock that staggers to whole group of DDR control device 10.
As shown in Figure 2, be the structural representation of the DDR control device based on FPGA according to the embodiment of the present invention, comprise: Read-write Catrol module 100, DDR chip drives module 200, input data buffer storage 300, output data buffer storage 400 and DDR chip I P core 20.
Input data buffer storage 300 comprises at least one on-chip memory, works under input data clock, for input data bit width being converted to the data bit width of DDR chip I P core 20, and stored in inputting the on-chip memory of data buffer storage 300.Concrete, the numerical value of the on-chip memory of input data buffer storage 300, by producing in whole system and need the input data class stored in DDR chip to determine simultaneously, also can be other arbitrary value.The size of each on-chip memory can be different, enter input data buffer storage 300 in input data and are written in the flow process of DDR chip, and input data first-in first-out, can carry out accumulation operations separately by the reading, writing address of on-chip memory and complete.The input end data bit width of input data buffer storage 300 is identical with input data bit width, and output terminal data bit width is identical with DDR chip I P core 20 input end data bit width.
Export data buffer storage 400 and comprise at least one on-chip memory, work under output data clock, for by the data of DDR chip I P core 20 stored in exporting the on-chip memory of data buffer storage 400, and the data bit width of DDR chip I P core 20 is converted to the wide output of outputs data bits.Concrete, the value exporting the on-chip memory of data buffer storage 400 is determined by the output data class read from DDR chip in whole system simultaneously, also can be other arbitrary value.The size of each on-chip memory can be different, enter in the output data read from DDR chip and export data buffer storage 400 and export in the flow process of Read-write Catrol module 100, export data first-in first-out, accumulation operations can be carried out separately by the reading, writing address of on-chip memory and complete.The output data that DDR chip only reads by each read operation are stored in an on-chip memory.And the input end data bit width exporting data buffer storage 400 is identical with DDR chip I P core 20 output terminal data bit width, and output terminal data bit width is wide identical with outputs data bits.
Wherein, input data comprise input data signal, write enable signal, write finishing signal and write DDR start address low level, export data and comprise outputting data signals and export useful signal.
In an embodiment of the present invention, the number inputting the on-chip memory that data buffer storage 300 comprises is equal with the number exporting the on-chip memory that data buffer storage 400 comprises.
In an embodiment of the present invention, DDR chip I P core 20 input end data bit width is identical with output terminal data bit width.
According to the DDR control device based on FPGA of the embodiment of the present invention, such as need simultaneously stored in input data have two kinds: a kind of is the input data of 8bit, also having a kind of is the input data of 16bit, the data bit width that DDR chip drives module 200 writes at every turn or reads is 16bit, and wherein input data clock is consistent with output data clock.
Input data buffer storage 300 is made up of two on-chip memories, and output terminal is all 16bit, and wherein a slice input end is 8bit, and another sheet input end is 16bit.Two panels on-chip memory works under input data clock, and during write data, DDR chip drives module 200 often writes a data writing address and adds 1 and circulate, and the address of sense data is operated by DDR chip drives module 200.
Export data buffer storage 400 to be made up of two on-chip memories, input end is all 16bit, and wherein a slice output terminal is 8bit, and another sheet output terminal is 16bit.Two panels on-chip memory works under output data clock, and during sense data, DDR chip drives module 200 often reads a data reading address and adds 1 and circulate, and the address of write data is operated by DDR chip drives module 200.
Read-write Catrol module 100, with input data buffer storage 300, export data buffer storage 400 and be connected with DDR chip drives module 200, for receiving write order and read command, the 200 pairs of DDR chip writes of control DDR chip drives module or sense data, and read enable signal to the transmission of output data buffer storage 400.
In an embodiment of the present invention, write order comprises write enable signal, writes finishing signal and writes DDR start address, and read command comprises reading request signal, reads DDR start address, read data number and read channel numbering.
Here, write DDR start address or read DDR start address and be divided into high-order and low level two parts, a high position is for representing the address of DDR chip-stored unit, and low level is for representing the address of data in DDR chip-stored unit.Write enable signal, for judging that whether input data are effective, being write finishing signal for judging whether input data terminate, being exported useful signal whether effective for judging to export data.
DDR chip drives module 200 and DDR chip I P core 20, Read-write Catrol module 100, input data buffer storage 300 and export data buffer storage 400 and be connected, work under DDR chip drives module work clock, for the initialization by DDR chip I P core 20 control DDR chip, according to write order or the read command of Read-write Catrol module 100, writing the on-chip memory write data of state from input data buffer storage 300, or at read states to the on-chip memory sense data exporting data buffer storage 400.
Concrete, DDR chip drives module 200 waits for that DDR chip I P core 20 completes the initialization to DDR chip, and then DDR chip drives module 200 enters idle state.In an idle state, DDR chip drives module 200 can receive any read/write command and enter read/write status, but writing under state and cannot receiving read command, in like manner under read states, also cannot receive write order.State of wherein writing can be subdivided into again and can not receive write order state and can receive write order state, and read states can be subdivided into again and can not receive read command state and can receive read command state.
When DDR chip drives module 200 from idle state enter write state time, DDR chip drives module 200 is first in and can not receives write order state, then jump to and can receive write order state, again enter after receiving write order and can not receive write order state, until no longer receive write order and complete current write order write order state can be received, enter idle state.
When DDR chip drives module 200 enters read states from idle state, DDR chip drives module 200 is first in and can not receives read command state, then jump to and can receive read command state, again enter after receiving read command and can not receive read command state, until no longer receive read command and complete current read command read command state can be received, enter idle state.
The signal (request end signal a, response end signal b) that five kinds of states of DDR chip drives module 200 are returned by DDR chip drives module 200 is determined.Two signals are high expression DDR chip drives module 200 and are in 1 state, i.e. idle state, a height b low expression DDR chip drives module 200 is in 2 states or 4 states, read command state can be received and maybe can receive write order state, two signals are low representation module and are in 3 states or 5 states, namely can not receive read command state and maybe can not receive write order state.In latter two situation, specifically read states still writes state by the order of a upper success transmission is that read command or write order are determined, read command is then read states, and write order is then write state.
According to the DDR control device based on FPGA of the embodiment of the present invention, simplify the operation of DDR chip, improve the work efficiency of DDR chip, increase the dirigibility of reading and writing data, make full use of the utilization that on-chip memory improves Resources on Chip.
As shown in Figure 3, be the process flow diagram of the DDR control method based on FPGA according to the embodiment of the present invention, comprise the following steps:
A: Read-write Catrol module receives write order and read command, under input data clock, for being converted to the data bit width of DDR chip I P core, and stored in inputting the on-chip memory of data buffer storage by input data bit width.
Wherein, input data buffer storage comprises at least one on-chip memory, concrete, and the numerical value of the on-chip memory of input data buffer storage, by producing in whole system and need the input data class stored in DDR chip to determine simultaneously, also can be other arbitrary value.The size of each on-chip memory can be different, enter input data buffer storage in input data and are written in the flow process of DDR chip, and input data first-in first-out, can carry out accumulation operations separately by the reading, writing address of on-chip memory and complete.The input end data bit width of input data buffer storage is identical with input data bit width, and output terminal data bit width is identical with DDR chip I P core input end data bit width.
Wherein, write order comprises write enable signal, writes finishing signal and writes DDR start address, and read command comprises reading request signal, reads DDR start address, read data number and read channel numbering.And input data and comprise input data signal, write enable signal, write finishing signal and write DDR start address low level.
Here, write DDR start address or read DDR start address and be divided into high-order and low level two parts, a high position is for representing the address of DDR chip-stored unit, and low level is for representing the address of data in DDR chip-stored unit.Write enable signal, for judging that whether input data are effective, writes finishing signal for judging whether input data terminate.
B:DDR chip drives module, works under DDR chip drives module work clock, by the initialization of DDR chip I P nuclear control DDR chip, makes DDR chip drives module enter idle state.
Concrete, DDR chip drives module waits for that DDR chip I P core completes the initialization to DDR chip, and then DDR chip drives module enters idle state.In an idle state, DDR chip drives module can receive any read/write command and enter read/write status, but writing under state and cannot receiving read command, in like manner under read states, also cannot receive write order.State of wherein writing can be subdivided into again and can not receive write order state and can receive write order state, and read states can be subdivided into again and can not receive read command state and can receive read command state.
C: when DDR chip drives module enters idle state, according to write order, enter the state of writing, DDR chip is from the on-chip memory write data of input data buffer storage under the control of Read-write Catrol module, and then DDR chip drives module enters idle state.
When DDR chip drives module from idle state enter write state time, DDR chip drives module is first in and can not receives write order state, then jump to and can receive write order state, again enter after receiving write order and can not receive write order state, until no longer receive write order and complete current write order write order state can be received, enter idle state.
D: Read-write Catrol module is according to read command, send to output data buffer storage and read enable signal, DDR chip drives module enters read states, under DDR chip drives module work clock, DDR chip is to the on-chip memory sense data exporting data buffer storage, export data buffer storage under output data clock, by the data of DDR chip I P core stored in the on-chip memory exporting data buffer storage, and the data bit width of DDR chip I P core is converted to the wide output of outputs data bits, then DDR chip drives module enters idle state.
When DDR chip drives module enters read states from idle state, DDR chip drives module is first in and can not receives read command state, then jump to and can receive read command state, again enter after receiving read command and can not receive read command state, until no longer receive read command and complete current read command read command state can be received, enter idle state.
The signal (request end signal a, response end signal b) that five kinds of states of DDR chip drives module are returned by DDR chip drives module is determined.Two signals are high expression DDR chip drives module and are in 1 state, i.e. idle state, a height b low expression DDR chip drives module is in 2 states or 4 states, read command state can be received and maybe can receive write order state, two signals are low representation module and are in 3 states or 5 states, namely can not receive read command state and maybe can not receive write order state.In latter two situation, specifically read states still writes state by the order of a upper success transmission is that read command or write order are determined, read command is then read states, and write order is then write state.
Here, exporting data and comprise outputting data signals and export useful signal, exporting useful signal whether effective for judging to export data.
Export data buffer storage and comprise at least one on-chip memory, the value exporting the on-chip memory of data buffer storage is determined by the output data class read from DDR chip in whole system simultaneously, also can be other arbitrary value.The size of each on-chip memory can be different, enter in the output data read from DDR chip and export data buffer storage and export in the flow process of Read-write Catrol module, export data first-in first-out, accumulation operations can be carried out separately by the reading, writing address of on-chip memory and complete.The output data that DDR chip only reads by each read operation are stored in an on-chip memory.And the input end data bit width exporting data buffer storage is identical with DDR chip I P core output terminal data bit width, and output terminal data bit width is wide identical with outputs data bits.Meanwhile, the number of the on-chip memory that the number of the on-chip memory that input data buffer storage comprises and output data buffer storage comprise is equal, and DDR chip I P core input end data bit width is identical with output terminal data bit width.
According to the DDR control method based on FPGA of the embodiment of the present invention, simplify the operation of DDR chip, improve the work efficiency of DDR chip, increase the dirigibility of reading and writing data, make full use of the utilization that on-chip memory improves Resources on Chip.
Describe and can be understood in process flow diagram or in this any process otherwise described or method, represent and comprise one or more for realizing the module of the code of the executable instruction of the step of specific logical function or process, fragment or part, and the scope of the preferred embodiment of the present invention comprises other realization, wherein can not according to order that is shown or that discuss, comprise according to involved function by the mode while of basic or by contrary order, carry out n-back test, this should understand by embodiments of the invention person of ordinary skill in the field.
In the description of this instructions, specific features, structure, material or feature that the description of reference term " embodiment ", " some embodiments ", " example ", " concrete example " or " some examples " etc. means to describe in conjunction with this embodiment or example are contained at least one embodiment of the present invention or example.In this manual, identical embodiment or example are not necessarily referred to the schematic representation of above-mentioned term.And the specific features of description, structure, material or feature can combine in an appropriate manner in any one or more embodiment or example.
Although illustrate and describe embodiments of the invention above, be understandable that, above-described embodiment is exemplary, can not be interpreted as limitation of the present invention, those of ordinary skill in the art can change above-described embodiment within the scope of the invention when not departing from principle of the present invention and aim, revising, replacing and modification.
Claims (20)
1. based on a DDR control device of FPGA, it is characterized in that, comprising: input data buffer storage, output data buffer storage, Read-write Catrol module, DDR chip drives module, DDR chip I P core,
Input data buffer storage, described input data buffer storage comprises at least one on-chip memory, works under input data clock, for input data bit width is converted to the data bit width of described DDR chip I P core, and stored in the on-chip memory of described input data buffer storage;
Export data buffer storage, described output data buffer storage comprises at least one on-chip memory, work under output data clock, for by the on-chip memory of the data of described DDR chip I P core stored in described output data buffer storage, and the data bit width of described DDR chip I P core is converted to the wide output of outputs data bits;
Read-write Catrol module, be connected with described DDR chip drives module with described input data buffer storage, described output data buffer storage, for receiving write order and read command, control described DDR chip drives module to the write of DDR chip or sense data, and read enable signal to described output data buffer storage transmission; And
DDR chip drives module, described DDR chip drives module is connected with described output data buffer storage with described DDR chip I P core, described Read-write Catrol module, described input data buffer storage, work under DDR chip drives module work clock, for the initialization by DDR chip described in described DDR chip I P nuclear control, according to write order or the read command of described Read-write Catrol module, writing the on-chip memory write data of state from described input data buffer storage, or in the on-chip memory sense data of read states to described output data buffer storage.
2. as claimed in claim 1 based on the DDR control device of FPGA, it is characterized in that, described input data comprise input data signal, write enable signal, write finishing signal and write DDR start address low level, and described output data comprise outputting data signals and export useful signal.
3. as claimed in claim 2 based on the DDR control device of FPGA, it is characterized in that, described write order comprise described write enable signal, described in write finishing signal and write DDR start address, described read command comprises reading request signal, reads DDR start address, read data number and read channel numbering.
4. as claimed in claim 3 based on the DDR control device of FPGA, it is characterized in that, the described DDR of writing start address or described in read DDR start address and be divided into high-order and low level two parts, a described high position is for representing the address of described DDR chip-stored unit, and described low level is for representing the address of described data in described DDR chip-stored unit.
5. as claimed in claim 1 based on the DDR control device of FPGA, it is characterized in that, when writing state described in described DDR chip drives module enters from idle state, described DDR chip drives module is first in and can not receives write order state, then jump to and can receive write order state, write order state can not be received described in again entering after receiving described write order, until no longer receive described write order in the described write order state that receives and complete current described write order, enter described idle state.
6. as claimed in claim 5 based on the DDR control device of FPGA, it is characterized in that, when described DDR chip drives module enters described read states from described idle state, described DDR chip drives module is first in and can not receives read command state, then jump to and can receive read command state, read command state can not be received described in again entering after receiving described read command, until no longer receive described read command in the described read command state that receives and complete current described read command, enter described idle state.
7., as claimed in claim 1 based on the DDR control device of FPGA, it is characterized in that, the number of the described on-chip memory that the number of the described on-chip memory that described input data buffer storage comprises and described output data buffer storage comprise is equal.
8. as claimed in claim 1 based on the DDR control device of FPGA, it is characterized in that, the input end data bit width of described input data buffer storage is identical with described input data bit width, output terminal data bit width is identical with described DDR chip I P core input end data bit width, and the input end data bit width of described output data buffer storage is identical with described DDR chip I P core output terminal data bit width, and output terminal data bit width is wide identical with described outputs data bits.
9., as claimed in claim 1 based on the DDR control device of FPGA, it is characterized in that, described DDR chip I P core input end data bit width is identical with output terminal data bit width.
10. as claimed in claim 3 based on the DDR control device of FPGA, it is characterized in that, described write enable signal, whether effective for judging described input data, describedly write finishing signal, for judging whether described input data terminate, described output useful signal, whether effective for judging described output data.
11. 1 kinds, based on the DDR control method of FPGA, is characterized in that, adopt the DDR control device based on FPGA described in any one of claim 1-10 to control described DDR chip drives module, comprise the following steps:
A: described Read-write Catrol module receives described write order and described read command, under input data clock, for being converted to the data bit width of described DDR chip I P core by input data bit width, and stored in the on-chip memory of described input data buffer storage;
B: described DDR chip drives module, works under DDR chip drives module work clock, by the initialization of DDR chip described in described DDR chip I P nuclear control, makes described DDR chip drives module enter idle state;
C: when described DDR chip drives module enters idle state, according to described write order, enter the state of writing, described DDR chip is from the on-chip memory write data of described input data buffer storage under the control of described Read-write Catrol module, and then described DDR chip drives module enters described idle state;
D: described Read-write Catrol module is according to described read command, send to described output data buffer storage and read enable signal, described DDR chip drives module enters read states, under DDR chip drives module work clock, described DDR chip is to the on-chip memory sense data of described output data buffer storage, described output data buffer storage is under output data clock, by the on-chip memory of the data of described DDR chip I P core stored in described output data buffer storage, and the data bit width of described DDR chip I P core is converted to the wide output of outputs data bits, then described DDR chip drives module enters described idle state.
12. as claimed in claim 11 based on the DDR control method of FPGA, and it is characterized in that, described input data comprise input data signal, write enable signal and write finishing signal, and described output data comprise outputting data signals and export useful signal.
13. as claimed in claim 12 based on the DDR control method of FPGA, it is characterized in that, described write order comprise described write enable signal, described in write finishing signal and write DDR start address, described read command comprises reading request signal, reads DDR start address, read data number and read channel numbering.
14. as claimed in claim 13 based on the DDR control method of FPGA, it is characterized in that, the described DDR of writing start address or described in read DDR start address and be divided into high-order and low level two parts, a described high position is for representing the address of described DDR chip-stored unit, and described low level is for representing the address of described data in described DDR chip-stored unit.
15. as claimed in claim 11 based on the DDR control method of FPGA, it is characterized in that, when writing state described in described DDR chip drives module enters from described idle state, described DDR chip drives module is first in and can not receives write order state, then jump to and can receive write order state, write order state can not be received described in again entering after receiving described write order, until no longer receive described write order in the described write order state that receives and complete current described write order, enter described idle state.
16. as claimed in claim 11 based on the DDR control method of FPGA, it is characterized in that, when described DDR chip drives module enters described read states from described idle state, described DDR chip drives module is first in and can not receives read command state, then jump to and can receive read command state, read command state can not be received described in again entering after receiving described read command, until no longer receive described read command in the described read command state that receives and complete current described read command, enter described idle state.
17. as claimed in claim 11 based on the DDR control method of FPGA, and it is characterized in that, the number of the described on-chip memory that the number of the described on-chip memory that described input data buffer storage comprises and described output data buffer storage comprise is equal.
18. as claimed in claim 11 based on the DDR control method of FPGA, it is characterized in that, the input end data bit width of described input data buffer storage is identical with described input data bit width, output terminal data bit width is identical with described DDR chip I P core input end data bit width, and the input end data bit width of described output data buffer storage is identical with described DDR chip I P core output terminal data bit width, and output terminal data bit width is wide identical with described outputs data bits.
19. as claimed in claim 11 based on the DDR control method of FPGA, and it is characterized in that, described DDR chip I P core input end data bit width is identical with output terminal data bit width.
20. as claimed in claim 13 based on the DDR control method of FPGA, it is characterized in that, described write enable signal, whether effective for judging described input data, describedly write finishing signal, for judging whether described input data terminate, described output useful signal, whether effective for judging described output data.
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| CN104599227B (en) * | 2013-10-30 | 2017-09-22 | 南京理工大学 | DDR3 arbitration controllers and method for high-speed CCD data storage |
| CN105279116B (en) * | 2015-10-08 | 2017-12-01 | 中国电子科技集团公司第四十一研究所 | DDR controller and control method based on FPGA |
| CN108920097B (en) * | 2018-06-11 | 2021-04-13 | 北京理工雷科雷达技术研究院有限公司 | Three-dimensional data processing method based on interleaving storage |
| CN108777774A (en) * | 2018-06-13 | 2018-11-09 | 贵州大学 | A kind of four-way video conversion circuit and conversion method based on FPGA |
| CN108958800B (en) * | 2018-06-15 | 2020-09-15 | 中国电子科技集团公司第五十二研究所 | DDR management control system based on FPGA hardware acceleration |
| CN109376101B (en) * | 2018-09-07 | 2020-10-30 | 西安电子科技大学 | System storage control module |
| CN111610934A (en) * | 2020-05-22 | 2020-09-01 | 上海大骋医疗科技有限公司 | DDR controller and control method |
| CN111694775A (en) * | 2020-06-09 | 2020-09-22 | 电子科技大学 | Device for performing read-write control based on time division multiplexing in DDR3 |
| CN112069095B (en) * | 2020-09-09 | 2022-01-28 | 北京锐马视讯科技有限公司 | DDR3 read-write transmission method and device |
| CN112131150B (en) * | 2020-09-15 | 2023-10-03 | 北京神州飞航科技有限责任公司 | Multi-chip external memory control method and device |
| CN112347031A (en) * | 2020-09-24 | 2021-02-09 | 深圳市紫光同创电子有限公司 | Embedded data cache system based on FPGA |
| CN113434455B (en) * | 2021-06-22 | 2023-10-24 | 中国电子科技集团公司第十四研究所 | Optical fiber interface data cache management method based on FPGA |
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