CN106528217B

CN106528217B - on-site programmable gate array program loading system and method

Info

Publication number: CN106528217B
Application number: CN201610946997.9A
Authority: CN
Inventors: 郑映; 张步; 龚智; 潘峰; 邓超; 伍力伟; 范月霞
Original assignee: Wuhan Ship Communication Research Institute
Current assignee: Wuhan Ship Communication Research Institute
Priority date: 2016-10-26
Filing date: 2016-10-26
Publication date: 2019-12-06
Anticipated expiration: 2036-10-26
Also published as: CN106528217A

Abstract

the invention discloses a field programmable gate array program loading system and a method, belonging to the field of field programmable gate arrays. The system comprises: the FPGA chip is connected with the ARM chip, a PS interface is configured between the FPGA chip and the ARM chip, and the FPGA chip further comprises a double-port RAM module; the FPGA chip comprises a first transmission module and is used for sending an instruction to the ARM chip in the process of running a program by the FPGA chip; the ARM chip comprises a second transmission module, the second transmission module is connected with the dual-port RAM module and used for reading the SOF from the dual-port RAM module after receiving the instruction; the ARM chip also comprises a processing module used for loading the SOF into the FPGA chip through the PS interface; the FPGA chip also comprises an execution module used for executing the SOF and running a Bootloader program in the SOF; the second transmission module is also used for writing the ELF file into the dual-port RAM module; and the execution module is also used for loading and operating the ELF file through a Bootloader program.

Description

On-site programmable gate array program loading system and method

Technical Field

the present invention relates to the Field of FPGA (Field Programmable Gate Array), and in particular, to a system and a method for loading an FPGA program.

background

programs running on the FPGA chip are divided into a configuration program (SOF (SRAM Object File)) and a software program (ELF (Executable and Linkable Format) File), and when the programs are running, the SOF is loaded first, and then the ELF File is loaded. The program loading of the FPGA chip is divided into 2 loading modes: on-chip loading and off-chip loading.

The traditional off-chip loading mode is to store the program code to be run on an EPCS (Erasable programmable configurable serial interface) chip outside the FPGA chip, and the program loading after the FPGA chip is powered on is realized through a special serial interface between the EPCS chip and the EPCS chip.

however, the limitation of this conventional off-chip loading mode is that only one-time loading of the program after the FPGA chip is powered on can be realized. After the program is loaded, if a new program needs to be loaded on the FPGA chip, the FPGA chip needs to be powered on again, and this limitation cannot meet the requirement of some application systems for multiple times of loading of the running program of the FPGA chip under the non-power-down condition.

disclosure of Invention

In order to solve the problem that the FPGA chip needs to be powered on again when a new program is loaded in the prior art, the embodiment of the invention provides a system and a method for loading an FPGA program. The technical scheme is as follows:

in a first aspect, an embodiment of the present invention provides a field programmable gate array program loading system, where the system includes:

the FPGA chip is connected with the ARM chip, a passive serial configuration mode PS interface is configured between the FPGA chip and the ARM chip, and the FPGA chip also comprises a double-port random access memory RAM module;

The FPGA chip comprises a first transmission module used for sending an instruction to the ARM chip in the process of running a program by the FPGA chip;

the ARM chip comprises a second transmission module, wherein the second transmission module is connected with the dual-port RAM module and used for reading a static random access memory (SOF) object file from the dual-port RAM module after receiving the instruction;

The ARM chip also comprises a processing module which is used for loading the SOF into the FPGA chip through a PS interface;

The FPGA chip further comprises an execution module, a bootstrap loader and a bootstrap loader, wherein the execution module is used for executing the SOF and running a bootstrap loader program in the SOF, and the SOF comprises the bootstrap loader program;

the second transmission module is also used for writing the ELF file in the executable and linkable format into the dual-port RAM module;

the execution module is further configured to load and run the ELF file through the Bootloader program.

In an implementation manner of the embodiment of the present invention, the first transmission module is further configured to receive a first part SOF sent by a server;

The FPGA chip further comprises a synthesis module for synthesizing the first part of SOF and a second part of SOF stored in the FPGA chip to obtain the SOF.

in another implementation manner of the embodiment of the present invention, the system further includes a random access memory RAM connected to the FPGA chip, and the first transmission module is further configured to store the ELF file in the dual-port RAM module into the RAM;

And the execution module is used for loading the ELF file in the RAM through the Bootloader program.

In another implementation manner of the embodiment of the present invention, the processing module is further configured to determine an ELF file to be loaded after the SOF is read, and the ARM chip stores at least two ELF files.

In another implementation manner of the embodiment of the present invention, the processing module is configured to determine an ELF file to be loaded according to an instruction of the FPGA chip; or determining the ELF file to be loaded according to the number of times of reading the SOF.

in a second aspect, an embodiment of the present invention further provides a field programmable gate array program loading method, where the FPGA chip is connected to the ARM chip, and a PS interface is configured between the FPGA chip and the ARM chip, the FPGA chip includes a dual-port RAM module, and the method includes:

The FPGA chip sends an instruction to the ARM chip in the process of running a program, so that the ARM chip reads the SOF from the dual-port RAM module and loads the SOF into the FPGA chip through a PS interface;

Executing the SOF and running a Bootloader program in the SOF, wherein the SOF comprises the Bootloader program;

loading and operating an ELF file through the Bootloader program, and writing the ELF file into the dual-port RAM module by the ARM chip.

In an implementation manner of the embodiment of the present invention, the method further includes:

Receiving a first part of SOF sent by a server;

And synthesizing the first part of SOF and a second part of SOF stored in the FPGA chip to obtain the SOF.

In another implementation manner of the embodiment of the present invention, the FPGA chip is further connected to a RAM, and the method further includes: storing the ELF file in the dual-port RAM module into the RAM;

The loading and running of the ELF file through the Bootloader program comprises the following steps:

And loading the ELF file in the RAM through the Bootloader program.

In a third aspect, an embodiment of the present invention further provides a field programmable gate array program loading method, where the FPGA chip is connected to the ARM chip, and a PS interface is configured between the FPGA chip and the ARM chip, the FPGA chip includes a dual-port RAM module, and the method includes:

the ARM chip receives an instruction sent in the process of running the program by the FPGA chip;

reading SOF from the dual-port RAM module;

Loading the SOF into the FPGA chip through a PS interface so that the FPGA chip executes the SOF and runs a Bootloader program in the SOF, wherein the SOF comprises the Bootloader program;

and writing the ELF file into the dual-port RAM module so that the FPGA chip loads and operates the ELF file through the Bootloader program.

And after reading the SOF, determining an ELF file to be loaded, wherein at least two ELF files are stored in the ARM chip.

the technical scheme provided by the embodiment of the invention has the following beneficial effects:

The FPGA chip is connected with the ARM chip, in the process of running a program, if a new program needs to be run, the FPGA chip sends an instruction to the ARM chip, the ARM chip receives the instruction, reads the SOF in the dual-port RAM module and loads the SOF into the FPGA chip through a PS (packet switched) mode (realized by adopting a PS interface), after the SOF is loaded, the FPGA chip executes the SOF and runs a Bootloader program in the SOF, and then the Bootloader program executes the ELF file written into the dual-port RAM module by the ARM chip, so that the new program loading operation is completed; in the program loading process, the power does not need to be re-electrified, and the requirement of some application systems for multiple times of loading of the running programs of the FPGA chip under the condition of no power failure is met; and on the other hand, the ELF file is stored in the ARM chip, so that off-chip loading is realized, and the problem of small storage space of the FPGA chip is solved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of an FPGA program loading system according to an embodiment of the present invention;

Fig. 2 is a flowchart of an FPGA program loading method according to an embodiment of the present invention;

fig. 3 is a flowchart of another FPGA program loading method according to an embodiment of the present invention;

Fig. 4 is a flowchart of another FPGA program loading method according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of an FPGA program loading system according to an embodiment of the present invention, and referring to fig. 1, the system includes:

The FPGA chip 10 is connected to the ARM chip 11, a PS (Passive Serial configuration mode) interface is configured between the FPGA chip 10 and the ARM chip 11, and the FPGA chip 10 includes a dual-port RAM (Random Access Memory) module 100.

the FPGA chip 10 further includes a first transmission module 101, which is used for sending an instruction to the ARM chip 11 in the process of running the program on the FPGA chip 10.

the ARM chip 11 includes a second transmission module 111, and the second transmission module 111 is connected to the dual-port RAM module 100 and configured to read SOF from the dual-port RAM module 100 after receiving the instruction.

The ARM chip 11 further comprises a processing module 112 for loading the SOF into the FPGA chip 10 through the PS interface.

The FPGA chip 10 further includes an execution module 102, configured to execute the SOF and run a Bootloader (Bootloader) program in the SOF, where the SOF includes the Bootloader program.

the second transmission module 111 is further configured to write the ELF file into the dual-port RAM module 100 of the FPGA chip 10.

The execution module 102 is further configured to load and run the ELF file through the Bootloader program.

The FPGA chip 10 and the ARM chip 11 may be connected through an IO (Input Output) interface.

The PS interface is a logic interface, and is implemented by running corresponding protocols in the FPGA chip 10 and the ARM chip 11. Specifically, the PS interface is an interface that implements data transmission using the PS mode. The PS mode is a mode in which an external controller (ARM chip) controls the configuration process of the FPGA chip. In the mode, the ARM chip writes the SOF into the FPGA chip, programming of the FPGA is achieved, and loading of the SOF is completed.

The dual-port RAM module 100 refers to a memory equipped with two sets of independent address, data and control lines, and the dual-port RAM module 100 allows two independent controllers (an FPGA chip and an ARM chip) to access asynchronously and simultaneously.

According to the invention, the FPGA chip is connected with the ARM chip, in the process of running a program, if a new program needs to be run, the FPGA chip sends an instruction to the ARM chip, the ARM chip receives the instruction, reads the SOF in the dual-port RAM module, and loads the SOF into the FPGA chip through a PS mode (realized by adopting a PS interface) by the ARM chip, after the SOF is loaded, the FPGA chip executes the SOF and runs a Bootloader program in the SOF, and then executes the ELF file written into the dual-port RAM module by the ARM chip through the Bootloader program, so that the new program loading operation is completed; in the program loading process, the power does not need to be re-electrified, and the requirement of some application systems for multiple times of loading of the running programs of the FPGA chip under the condition of no power failure is met; and on the other hand, the ELF file is stored in the ARM chip, so that off-chip loading is realized, and the problem of small storage space of the FPGA chip is solved.

Optionally, the first transmission module 101 is further configured to receive a first partial SOF sent by the server; the FPGA chip 10 further includes a synthesis module, configured to synthesize the first part of SOF with a second part of SOF stored in the FPGA chip 10 to obtain the SOF. The synthesized SOF is stored in the dual port RAM module 100.

In the implementation mode, the SOF is divided into two parts which are respectively stored in the server and the local, so that the problem that the SOF is stolen when the FPGA chip 10 or the server is stolen is avoided, and the safety is improved.

The first transmission module 101 may perform SOF synthesis in a preset manner (corresponding to the way when the SOF is split into two parts), for example, directly splicing the two parts together, or performing simple operation (such as exclusive or) on the two parts.

of course, in other embodiments, the SOF may be stored entirely in the FPGA chip 10 or in a server.

further, the system may further include a random access memory RAM connected to the FPGA chip 10, a first transmission module 101, and a second transmission module for storing the ELF file stored in the dual-port RAM module 100 into the RAM; and the execution module 102 is configured to load the ELF file in the RAM through a Bootloader program.

in the implementation mode, the external RAM is connected to the exterior of the FPGA chip 10, and the ELF file is stored in the RAM, so that the problem that the internal storage space of the FPGA chip 10 is small is solved.

In the embodiment of the present invention, at least two ELF files are stored in the ARM chip 11, the FPGA chip 10 loads and runs the first ELF file after being powered on, and the second ELF file loads and runs when needed. Therefore, after receiving the instruction transmitted by the FPGA chip 10, the ARM chip 11 needs to determine which ELF file is transmitted to the FPGA chip 10.

Therefore, in this implementation, the processing module 112 may be further configured to determine an ELF file to be loaded after the SOF is read, so as to control the second transmission module 111 to write the ELF file to be loaded into the dual-port RAM module 100 of the FPGA chip 10.

specifically, the processing module 112 may be configured to determine, according to an instruction of the FPGA chip 10, an ELF file to be loaded; or determining the ELF file to be loaded according to the number of times of receiving the SOF.

In the implementation mode, more than two ELF files are stored in the ARM chip 11, so that the problem that a new program code needs to be recorded in the EPCS chip when a new program is reloaded in the conventional off-chip loading mode is solved.

the instruction transmitted by the FPGA chip 10 may include the number of the ELF file, for example, if the instruction is 0, the ELF file to be loaded is the first ELF file, and if the instruction is 1, the ELF file to be loaded is the second ELF file.

Or, the ARM chip 11 records the number of times of receiving the SOF, and determines the ELF file to be loaded according to the number of times of receiving the SOF. For example, if the ARM chip 11 receives the SOF for the first time, the ELF file to be loaded is the first ELF file, and if the ARM chip 11 receives the SOF for the second time, the ELF file to be loaded is the second ELF file.

Fig. 2 is a flowchart of an FPGA program loading method according to an embodiment of the present invention, which is executed by an FPGA chip in the system provided in fig. 1, and referring to fig. 2, the method includes:

Step 201: and in the process of running the program, the FPGA chip sends an instruction to the ARM chip so that the ARM chip reads the SOF from the dual-port RAM module and loads the SOF into the FPGA chip through the PS interface.

Step 202: and executing the SOF and running a Bootloader program in the SOF, wherein the SOF comprises the Bootloader program.

step 203: loading and operating the ELF file through a Bootloader program, and writing the ELF file into the dual-port RAM module by the ARM chip.

Fig. 3 is a flowchart of another FPGA program loading method according to an embodiment of the present invention, which is executed by an ARM chip in the system provided in fig. 1, and referring to fig. 3, the method includes:

Step 301: and the ARM chip receives an instruction sent in the process of running the program by the FPGA chip.

Step 302: SOF is read from the dual port RAM module.

Step 303: and loading the SOF into the FPGA chip through the PS interface so that the FPGA chip executes the SOF and runs a Bootloader program in the SOF, wherein the SOF comprises the Bootloader program.

step 304: and writing the ELF file into a dual-port RAM module so that the FPGA chip loads and runs the ELF file through a Bootloader program.

fig. 4 is a flowchart of another FPGA program loading method according to an embodiment of the present invention, which is executed by the FPGA chip and the ARM chip in the system shown in fig. 1, and referring to fig. 4, the method includes:

step 401: and the ARM chip reads the SOF from the dual-port RAM module.

Further, the method may further include:

The method comprises the steps that an FPGA chip receives a first part of SOF sent by a server; and the FPGA chip synthesizes the first part of SOF and a second part of SOF stored in the FPGA chip to obtain the SOF. The resulting SOF is stored in a dual port RAM module.

In the implementation mode, the SOF is divided into two parts which are respectively stored in the server and the local, so that the problem that the SOF is stolen when an FPGA chip or the server is stolen is avoided, and the safety is improved.

The first part SOF and the second part SOF may be combined in a preset manner (corresponding to the manner when the SOF is split into two parts), for example, the two parts are directly spliced together, or the two parts are simply operated (such as exclusive or).

of course, in other embodiments, the SOF may be stored entirely in the FPGA chip or in the server.

In the embodiment of the invention, at least two ELF files are stored in the ARM chip, the first ELF file is loaded and operated after the FPGA chip is powered on, and the second ELF file is loaded and operated when needed. Therefore, after the ARM chip receives the SOF transmitted by the FPGA chip, it needs to determine which ELF file is transmitted to the FPGA chip. Accordingly, the method may further comprise:

After the ARM chip reads the SOF, the ELF files to be loaded are determined, and at least two ELF files are stored in the ARM chip.

Specifically, after receiving the SOF, determining an ELF file to be loaded may include:

the ARM chip determines an ELF file to be loaded according to the instruction of the FPGA chip; or the ARM chip determines the ELF file to be loaded according to the number of times of receiving the SOF.

In the implementation mode, more than two ELF files are stored in the ARM chip at the same time, so that the problem that a new program code needs to be recorded in the EPCS chip when a new program is reloaded in the conventional off-chip loading mode is solved.

The instruction of the FPGA chip may include a number of the ELF file, for example, if the instruction is 0, the ELF file to be loaded is the first ELF file, and if the instruction is 1, the ELF file to be loaded is the second ELF file.

or the ARM chip records the number of times of receiving the SOF, and determines the ELF file to be loaded according to the number of times of receiving the SOF. For example, if the ARM chip receives the SOF for the first time, the ELF file to be loaded is the first ELF file, and if the ARM chip receives the SOF for the second time, the ELF file to be loaded is the second ELF file.

As shown in fig. 4, since step 401 is executed during the program running process, before step 401, the method further includes: the FPGA chip loads the SOF 'and ELF' (i.e., the program that the FPGA chip is running in step 401).

Further, for the efficiency of subsequent transmission of ELF files by the ARM chip, the ARM chip may read the ELF files before step 401.

Further, the FPGA chip may notify the ARM chip to execute loading of the new program by sending an instruction to the ARM chip. That is, the method may comprise: and the FPGA chip sends an instruction to the ARM chip in the process of running the program.

Step 402: and the ARM chip loads the SOF into the FPGA chip through the PS interface.

step 403: the FPGA chip executes the SOF and runs a Bootloader program in the SOF, and the SOF comprises the Bootloader program.

Step 404: and the ARM chip writes the ELF file into a double-port RAM module of the FPGA chip.

Further, after the step 403, the FPGA chip sends a notification instruction to the ARM chip to notify the ARM chip that the SOF is executed, so that the ARM chip executes the step 404.

Step 405: and the FPGA chip loads and runs the ELF file through a Bootloader program.

In the embodiment of the present invention, the FPGA chip may further be connected to the RAM, and accordingly, the method may further include: and the FPGA chip stores the ELF file in the dual-port RAM module into the RAM.

at this time, step 405 may include: and the FPGA chip loads the ELF file in the RAM through a Bootloader program. Specifically, the ELF file is stored in the RAM to obtain a starting address of the ELF file, and when the ELF file is loaded by the Bootloader program, the ELF file is directly jumped to the starting address to run the ELF file.

In the implementation mode, the RAM is externally connected outside the FPGA chip, the ELF file is stored in the RAM, and the problem that the internal storage space of the FPGA chip is small is solved.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims

1. a field programmable gate array program loading system, the system comprising:

the FPGA chip is connected with the ARM chip, a passive serial configuration mode PS interface is configured between the FPGA chip and the ARM chip, and the FPGA chip comprises a double-port RAM module;

The FPGA chip also comprises a first transmission module which is used for sending an instruction to the ARM chip in the process of running a program by the FPGA chip;

2. The system according to claim 1, wherein the first transmission module is further configured to receive a first part SOF sent by the server;

3. The system according to claim 1 or 2, further comprising a Random Access Memory (RAM) connected to the FPGA chip, wherein the first transmission module is further configured to store the ELF file in the dual-port RAM module into the RAM;

4. The system of claim 1 or 2, wherein the processing module is further configured to determine an ELF file to be loaded after the SOF is read, and at least two ELF files are stored in the ARM chip.

5. The system of claim 4, wherein the processing module is configured to determine an ELF file to be loaded according to an instruction of the FPGA chip; or determining the ELF file to be loaded according to the number of times of reading the SOF.

6. a field programmable gate array program loading method is characterized in that an FPGA chip is connected with an ARM chip, a PS interface is configured between the FPGA chip and the ARM chip, the FPGA chip comprises a double-port RAM module, and the method comprises the following steps:

The FPGA chip sends an instruction to the ARM chip in the process of running a program, so that the ARM chip reads a static random access memory (SOF) object file from the dual-port RAM module and loads the SOF into the FPGA chip through a PS (packet switch) interface;

loading and operating an executable and linkable format ELF file through the Bootloader program, and writing the ELF file into the dual-port RAM module by the ARM chip.

7. The method of claim 6, further comprising:

Receiving a first part of SOF sent by a server;

8. the method of claim 6 or 7, wherein the FPGA chip is further connected to RAM, the method further comprising: storing the ELF file in the dual-port RAM module into the RAM;

and loading the ELF file in the RAM through the Bootloader program.

9. A field programmable gate array program loading method is characterized in that an FPGA chip is connected with an ARM chip, a PS interface is configured between the FPGA chip and the ARM chip, the FPGA chip comprises a double-port RAM module, and the method comprises the following steps:

Reading an object file SOF of a static random access memory from the dual-port RAM module;

writing an executable ELF file in a linkable format into the dual-port RAM module so that the FPGA chip loads and runs the ELF file through the Bootloader program.

10. The method of claim 9, further comprising: