CN103218966B - The data transmission method of display panel internal interface and device - Google Patents
The data transmission method of display panel internal interface and device Download PDFInfo
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Abstract
The invention discloses a kind of data transmission method and device of display panel internal interface.Wherein, the data transmission method of display panel internal interface comprises: packet on the data channel that the display data of TCON side are mapped as display panel internal interface by the transmitting terminal of display panel internal interface; Transmitting terminal is encoded to packet; Transmitting terminal sends the receiving end of the packet after coding to display panel internal interface via data channel, employing fixed rate; The fixed rate that receiving end is corresponding according to packet obtains clock information; Receiving end is decoded to packet according to clock information; And receiving end by decoded data packet transmission to SD.By the present invention, solve the problem that in prior art, the electromagnetic interference (EMI) of display panel is higher, and then reach the effect reducing electromagnetic interference (EMI), improve anti-interference.
Description
Technical field
The present invention relates to display panel field, in particular to a kind of data transmission method and device of display panel internal interface.
Background technology
Field is manufactured at present at display panel, the widespread use of end-to-end interface mode, but inventor finds in current various end-to-end interface, there is serious electromagnetic interference (EMI) (Electro-Magnetic Interference is called for short EMI) problem.
For the problem that the electromagnetic interference (EMI) of display panel in related art is higher, at present effective solution is not yet proposed.
Summary of the invention
Fundamental purpose of the present invention is the data transmission method and the device that provide a kind of display panel internal interface, to solve the problem that in prior art, the electromagnetic interference (EMI) of display panel is higher.
To achieve these goals, according to an aspect of the present invention, provide a kind of data transmission method of display panel internal interface, comprising: packet on the data channel that the display data of TCON side are mapped as display panel internal interface by the transmitting terminal of display panel internal interface; Transmitting terminal is encoded to packet; Transmitting terminal sends the receiving end of the packet after coding to display panel internal interface via data channel, employing fixed rate; The fixed rate that receiving end is corresponding according to packet obtains clock information; Receiving end is decoded to packet according to clock information; And receiving end by decoded data packet transmission to SD.
Further, before transmitting terminal is encoded to packet, the data transmission method of display panel internal interface also comprises: transmitting terminal carries out scrambling to packet, wherein, transmitting terminal is encoded to packet and is comprised transmitting terminal and encode to the packet after scrambling, after receiving end is decoded to packet, the data transmission method of display panel internal interface also comprises: receiving end carries out descrambling to packet, wherein, decoded data packet transmission is comprised receiving end by the data packet transmission after descrambling to SD to SD by receiving end.
Further, carry out scrambling to packet and comprise and carry out scrambling by linear feedback shift register LFSR polynomial expression to packet, wherein, LFSR polynomial expression is:
G(x)＝X
16+X
5+X
4+X
3+1。
Further, packet comprises the first space code successively, controls bag, video packets, the second space code and idle bit, and wherein, the first space code and the second space code are different space codes.
Further, scrambling is carried out to packet and coding comprises: only scrambling and coding are carried out to control bag, video packets and idle bit.
Further, idle bit comprises whole zero bytes before scrambling and coding, controls handbag and draws together the static state in data transmission procedure or dynamically arrange order.
Further, when there is two pairs of differential signals when between TCON and SD, display panel internal interface has two data channels, on the data channel that display data are mapped as display panel internal interface, packets comprise: display data are mapped respectively packet on two data channels, wherein, control bag on two data channels in packet is identical, and when having a pair differential signal when between TCON and SD, display panel internal interface only has a data channel.
Further, the packet that display data are mapped as on data channel is comprised: display data are carried out 6bpc pattern or 8bpc mode map.
Further, when display panel internal interface has a data channel and display data carry out 8bpc mode map, the 0th of the X byte of video packets is followed successively by Ri [0] to the 7th, Ri [1] to Ri [7], the 0th of the X+1 byte of video packets is followed successively by Gi [0] to the 7th, Gi [1] to Gi [7], the 0th of the X+2 byte of video packets is followed successively by Bi [0] to the 7th, Bi [1] to Bi [7], wherein, Ri [n] is the quantized value of red component in single pixel, Gi [n] is the quantized value of single pixel Green component, Bi [n] is the quantized value of blue component in single pixel, X, i is nonnegative integer, n=0 ~ 7.
Further, when display panel internal interface has two data channels and display data carry out 8bpc mode map, if the number of pixels in each cutting video line is even number, then the 0th of X byte of the first video packets is followed successively by Ri [0] to the 7th, Ri [1] to Ri [7], the 0th of the X+1 byte of the first video packets is followed successively by Gi [0] to the 7th, Gi [1] to Gi [7], the 0th of the X+2 byte of the first video packets is followed successively by Bi [0] to the 7th, Bi [1] to Bi [7], wherein, first video packets is the video packets in two data channels on a data channel in packet, the 0th of the X byte of the second video packets is followed successively by R (i+1) [0] to the 7th, R (i+1) [1] is to R (i+1) [7], the 0th of the X+1 byte of the second video packets is followed successively by G (i+1) [0] to the 7th, G (i+1) [1] is to G (i+1) [7], the 0th of the X+2 byte of the second video packets is followed successively by B (i+1) [0] to the 7th, B (i+1) [1] is to B (i+1) [7], wherein, second video packets is the video packets in two data channels on another data channel in packet, if when number of pixels is odd number, the first video packets when first video packets is even number with number of pixels is identical, the X byte of the second video packets, everybody of X+1 byte and X+2 byte is 0, wherein, Ri [n] is the quantized value of red component in single pixel, Gi [n] is the quantized value of single pixel Green component, Bi [n] is the quantized value of blue component in single pixel, X, i is nonnegative integer, n=0 ~ 7.
Further, when display panel internal interface has a data channel and display data carry out 6bpc mode map, if the number of pixels in each cutting video line is 4N, then the 0th of X byte of video packets is followed successively by Gi [0] to the 7th, Gi [1], Ri [0], Ri [1] to Ri [5], the 0th of the X+1 byte of video packets is followed successively by Gi [2] to the 7th, Gi [3], Bi [0], Bi [1] to Bi [5], the 0th of the X+2 byte of video packets is followed successively by Gi [4] to the 7th, Gi [5], R (i+1) [0], R (i+1) [1], to R (i+1) [5], the 0th of the X+3 byte of video packets is followed successively by G (i+1) [0] to the 7th, G (i+1) [1], B (i+1) [0], B (i+1) [1], to B (i+1) [5], the 0th of the X+4 byte of video packets is followed successively by G (i+1) [2] to the 7th, G (i+1) [3] are to G (i+1) [5], G (i+2) [0], G (i+2) [1], to G (i+2) [3], the 0th of the X+5 byte of video packets is followed successively by G (i+2) [4] to the 7th, G (i+2) [5], R (i+2) [0], R (i+2) [1], to R (i+2) [5], the 0th of the X+6 byte of video packets is followed successively by G (i+3) [0] to the 7th, G (i+3) [1], B (i+2) [0], B (i+2) [1], to B (i+2) [5], the 0th of the X+7 byte of video packets is followed successively by G (i+3) [2] to the 7th, G (i+3) [3], R (i+3) [0], R (i+3) [1], to R (i+3) [5], the 0th of the X+8 byte of video packets is followed successively by G (i+3) [4] to the 7th, G (i+3) [5], B (i+3) [0], B (i+3) [1] is to B (i+3) [5],
If number of pixels is 4N+1, when then the X byte of video packets, X+1 byte are 4N with number of pixels, the X byte of video packets is identical respectively with X+1 byte, the 0th and the 1st of the X+2 byte of video packets is followed successively by Gi [4] and Gi [5], and the 2nd of the X+2 byte of video packets is 0 to the 7th, if number of pixels is 4N+2, the X byte of video packets when then the X byte of video packets, X+1 byte to X+3 byte are 4N with number of pixels, X+1 byte are identical respectively to X+3 byte, the 0th to the 3rd of the X+4 byte of video packets is followed successively by G (i+1) [2], G (i+1) [3] to G (i+1) [5], and the 4th of the X+4 byte of video packets is 0 to the 7th, if number of pixels is 4N+3, the then X byte of video packets, the X byte of video packets when X+1 byte to X+5 byte and number of pixels is 4N, X+1 byte is identical respectively to X+5 byte, the 2nd of the X+6 byte of video packets is followed successively by B (i+2) [0] to the 7th, B (i+2) [1] is to B (i+2) [5], the 0th and the 1st of the X+6 byte of video packets is 0, wherein, Ri [n] is the quantized value of red component in single pixel, Gi [n] is the quantized value of single pixel Green component, Bi [n] is the quantized value of blue component in single pixel, X, i, N is nonnegative integer, n=0 ~ 5.
Further, when display panel internal interface has two data channels and display data carry out 6bpc mode map, if the number of pixels in each cutting video line is 8N, then the 0th of X byte of the first video packets is followed successively by Gi [0] to the 7th, Gi [1], Ri [0], Ri [1] to Ri [5], the 0th of the X+1 byte of the first video packets is followed successively by Gi [2] to the 7th, Gi [3], Bi [0], Bi [1] to Bi [5], the 0th of the X+2 byte of the first video packets is followed successively by Gi [4] to the 7th, Gi [5], R (i+2) [0], R (i+2) [1], to R (i+2) [5], the 0th of the X+3 byte of the first video packets is followed successively by G (i+2) [0] to the 7th, G (i+2) [1], B (i+2) [0], B (i+2) [1], to B (i+2) [5], the 0th of the X+4 byte of the first video packets is followed successively by G (i+2) [2] to the 7th, G (i+2) [3] are to G (i+2) [5], G (i+4) [0], G (i+4) [1], to G (i+4) [3], the 0th of the X+5 byte of the first video packets is followed successively by G (i+4) [4] to the 7th, G (i+4) [5], R (i+4) [0], R (i+4) [1], to R (i+4) [5], the 0th of the X+6 byte of the first video packets is followed successively by G (i+6) [0] to the 7th, G (i+6) [1], B (i+4) [0], B (i+4) [1], to B (i+4) [5], the 0th of the X+7 byte of the first video packets is followed successively by G (i+6) [2] to the 7th, G (i+6) [3], R (i+6) [0], R (i+6) [1], to R (i+6) [5], the 0th of the X+8 byte of the first video packets is followed successively by G (i+6) [4] to the 7th, G (i+6) [5], B (i+6) [0], B (i+6) [1] is to B (i+6) [5], wherein, first video packets is the video packets in two data channels on a data channel in packet, and the 0th of the X byte of the second video packets is followed successively by G (i+1) [0] to the 7th, G (i+1) [1], R (i+1) [0], R (i+1) [1], to R (i+1) [5], the 0th of the X+1 byte of the second video packets is followed successively by G (i+1) [2] to the 7th, G (i+1) [3], B (i+1) [0], B (i+1) [1], to B (i+1) [5], the 0th of the X+2 byte of the second video packets is followed successively by G (i+1) [4] to the 7th, G (i+1) [5], R (i+3) [0], R (i+3) [1], to R (i+3) [5], the 0th of the X+3 byte of the second video packets is followed successively by G (i+3) [0] to the 7th, G (i+3) [1], B (i+3) [0], B (i+3) [1], to B (i+3) [5], the 0th of the X+4 byte of the second video packets is followed successively by G (i+3) [2] to the 7th, G (i+3) [3] are to G (i+3) [5], G (i+5) [0], G (i+5) [1], to G (i+5) [3], the 0th of the X+5 byte of the second video packets is followed successively by G (i+5) [4] to the 7th, G (i+5) [5], R (i+5) [0], R (i+5) [1], to R (i+5) [5], the 0th of the X+6 byte of the second video packets is followed successively by G (i+7) [0] to the 7th, G (i+7) [1], B (i+5) [0], B (i+5) [1], to B (i+5) [5], the 0th of the X+7 byte of the second video packets is followed successively by G (i+7) [2] to the 7th, G (i+7) [3], R (i+7) [0], R (i+7) [1], to R (i+7) [5], the 0th of the X+8 byte of the second video packets is followed successively by G (i+7) [4] to the 7th, G (i+7) [5], B (i+7) [0], B (i+7) [1], to B (i+7) [5], wherein, the second video packets is the video packets in two data channels on another data channel in packet, if number of pixels is 8N+1, when then the X byte of the first video packets, X+1 byte are 8N with number of pixels, the X byte of the first video packets is identical respectively with X+1 byte, the 0th and the 1st of the X+2 byte of the first video packets is followed successively by Gi [4] and Gi [5], the 2nd to the 7th of the X+2 byte of the first video packets be the X byte of the 0, the second video packets, X+1 byte and X+2 byte everybody be 0, if number of pixels is 8N+2, the first video packets when then the first video packets is 8N+1 with number of pixels is identical, when the X byte of the second video packets, X+1 byte are 8N with number of pixels, the X byte of the second video packets is identical respectively with X+1 byte, the 0th and the 1st of the X+2 byte of the second video packets is followed successively by G (i+1) [4] and G (i+1) [5], and the 2nd of the X+2 byte of the second video packets is 0 to the 7th, if number of pixels is 8N+3, the then X byte of the first video packets, the X byte of the first video packets when X+1 byte to X+3 byte and number of pixels is 8N, X+1 byte is identical respectively to X+3 byte, the 0th to the 3rd of the X+4 byte of the first video packets is followed successively by G (i+2) [2] to G (i+2) [5], the 4th of the X+4 byte of the first video packets is 0 to the 7th, when the X byte of the second video packets is 8N with X+1 byte with number of pixels, the X byte of the second video packets is identical respectively with X+1 byte, the 0th and the 1st of the X+2 byte of the second video packets is followed successively by G (i+1) [4] and G (i+1) [5], the 2nd to the 7th of the X+2 byte of the second video packets, X+3 and the X+4 byte of the second video packets are 0, if number of pixels is 8N+4, the first video packets when then the first video packets is 8N+3 with number of pixels is identical, the X byte of the second video packets when the X byte of the second video packets, X+1 byte to X+3 byte are 8N with number of pixels, X+1 byte are identical respectively to X+3 byte, the 0th to the 3rd of the X+4 byte of the second video packets is followed successively by G (i+3) [2] to G (i+3) [5], and the 4th of the X+4 byte of the second video packets is 0 to the 7th, if number of pixels is 8N+5, the then X byte of the first video packets, the X byte of the first video packets when X+1 byte to X+5 byte and number of pixels is 8N, X+1 byte is identical respectively to X+5 byte, the 0th and the 1st of the X+6 byte of the first video packets is 0, the 2nd to the 7th of the X+6 byte of the first video packets is followed successively by B (i+4) [0] to B (i+4) [5], the X byte of the second video packets, the X byte of the second video packets when X+1 byte to X+3 byte and number of pixels is 8N, X+1 byte is identical respectively to X+3 byte, the 0th to the 3rd of the X+4 byte of the second video packets is followed successively by G (i+3) [2] to G (i+3) [5], the 4th to the 7th of the X+4 byte of the second video packets, X+5 byte and the X+6 byte of the second video packets are 0, if number of pixels is 8N+6, the first video packets when then the first video packets is 8N+5 with number of pixels is identical, the X byte of the second video packets when the X byte of the second video packets, X+1 byte to X+5 byte are 8N with number of pixels, X+1 byte are identical respectively to X+5 byte, 0th and the 1st the 2nd to the 7th of being the X+6 byte of the 0, the second video packets of the X+6 byte of the second video packets is followed successively by B (i+5) [0] to B (i+5) [5], if number of pixels is 8N+7, the first video packets when then the first video packets is 8N with number of pixels is identical, the X byte of the second video packets, the X byte of the second video packets when X+1 byte to X+5 byte and number of pixels is 8N, X+1 byte is identical respectively to X+5 byte, the 2nd of the X+6 byte of the second video packets is followed successively by B (i+5) [0] to the 7th, B (i+5) [1] is to B (i+5) [5], the 0th and the 1st of the X+6 byte of the second video packets, X+7 byte and the X+8 byte of the second video packets are 0, wherein, Ri [n] is the quantized value of red component in single pixel, Gi [n] is the quantized value of single pixel Green component, Bi [n] is the quantized value of blue component in single pixel, X, i, N is nonnegative integer, n=0 ~ 5.
To achieve these goals, according to a further aspect in the invention, provide a kind of data transmission device of display panel internal interface, the data transmission device of the display panel internal interface data transmission method of any one display panel internal interface for performing foregoing of the present invention and providing.
To achieve these goals, according to a further aspect in the invention, provide a kind of data transmission device of display panel internal interface, comprising: mapping block, packet on the data channel display data of TCON side being mapped as display panel internal interface; Coding module, for encoding to packet; Sending module, for sending the packet after coding via data channel, employing fixed rate; Receiver module, for receiving the packet of sending module transmission, and the fixed rate corresponding according to packet obtains clock information; Decoder module, for decoding to packet according to clock information; And transport module, for by decoded data packet transmission to SD.
Further, the data transmission device of display panel internal interface also comprises: scrambling module, before packet being encoded at coding module, scrambling is carried out to packet, wherein, coding module is also for encoding to the packet after scrambling, descrambling module, after decoding to packet at decoder module, carries out descrambling to packet, wherein, transport module also for by the data packet transmission after descrambling to SD.
By the present invention, packet on the data channel adopting the transmitting terminal of display panel internal interface the display data of TCON side to be mapped as display panel internal interface; Transmitting terminal is encoded to packet; Transmitting terminal sends the receiving end of the packet after coding to display panel internal interface via data channel, employing fixed rate; The fixed rate that receiving end is corresponding according to packet obtains clock information; Receiving end is decoded to packet according to clock information; And receiving end by decoded data packet transmission to SD.By clock information being embedded in the mode of signaling channel, make receiving end can obtain clock information by the fixed rate corresponding according to packet, add the anti-interference of communication, solve the problem that in prior art, the electromagnetic interference (EMI) of display panel is higher, and then reach the effect reducing electromagnetic interference (EMI), improve anti-interference.
Accompanying drawing explanation
The accompanying drawing forming a application's part is used to provide a further understanding of the present invention, and schematic description and description of the present invention, for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 is the process flow diagram of the data transmission method of display panel internal interface according to the embodiment of the present invention;
Fig. 2 is the pixel-map figure according to the data transmission method of the embodiment of the present invention, display data being carried out to single channel 8bpc mode map;
Fig. 3 a and Fig. 3 b and Fig. 4 a and Fig. 4 b is the pixel-map figure according to the data transmission method of the embodiment of the present invention, display data being carried out to double-channel 8bpc mode map;
Fig. 5 a to Fig. 5 d is the pixel-map figure according to the data transmission method of the embodiment of the present invention, display data being carried out to single channel 6bpc mode map;
Fig. 6 a to Fig. 6 m is the pixel-map figure according to the data transmission method of the embodiment of the present invention, display data being carried out to double-channel 6bpc mode map; And
Fig. 7 is the schematic diagram of the data transmission device of display panel internal interface according to the embodiment of the present invention.
Embodiment
It should be noted that, when not conflicting, the embodiment in the application and the feature in embodiment can combine mutually.Below with reference to the accompanying drawings and describe the present invention in detail in conjunction with the embodiments.
Embodiments provide a kind of data transmission method of display panel internal interface, below the data transmission method of the display panel internal interface that the embodiment of the present invention provides be specifically introduced:
Fig. 1 is the data transmission method of the display panel internal interface according to the embodiment of the present invention, and as shown in Figure 1, this data transmission method comprises following step S101 to step S106:
S101: packet on the data channel that the display data of TCON side are mapped as display panel internal interface by the transmitting terminal of display panel internal interface, TCON refers to the time schedule controller in display panel, that is to say that the time schedule controller that display panel internal interface connects, data channel are the passage of transmitting terminal to receiving end transmission data of display panel internal interface.
S102: transmitting terminal is encoded to packet, preferably, transmitting terminal first carries out scrambling to packet before encoding to packet, then encodes to the packet after scrambling.
S103: transmitting terminal sends the receiving end of the packet after coding to display panel internal interface via data channel, employing fixed rate, that is, transmitting terminal is embedded in carrying out communication clock information used in data channel.
S104: the fixed rate that receiving end is corresponding according to packet obtains clock information, that is, obtain clock information according to fixed rate during transmitting terminal transmission packet.
S105: receiving end is decoded to packet according to clock information, preferably, receiving end, before decoding to packet according to clock information, first carries out descrambling to packet.
S106: receiving end by decoded data packet transmission to SD, accordingly, drive circuit chip that the data packet transmission after descrambling connects to SD, SD for display panel internal interface by receiving end (Source Driver is called for short SD).
The data transmission method of the display panel internal interface of the embodiment of the present invention, adopt mode clock information being embedded in signaling channel, make receiving end can obtain clock information by the fixed rate corresponding according to packet, add the anti-interference of communication, solve the problem that in prior art, the electromagnetic interference (EMI) of display panel is higher, and then reach the effect reducing electromagnetic interference (EMI), improve anti-interference.Wherein, send after first scrambling being carried out to packet by transmitting terminal, correspondingly, transfer to the mode of SD after carrying out descrambling by receiving end again, electromagnetic interference (EMI) can be reduced further.
In the embodiment of the present invention, packet comprises the first space code successively, controls bag, video packets, the second space code and idle bit, wherein, first space code and the second space code are different space codes, space code is control the proprietary space code (hereinafter referred to as K code) between bag and video packets, to distinguish mutually with idle bit, idle bit comprises whole zero bytes before scrambling and coding, controls handbag and draws together the static state in data transmission procedure or dynamically arrange order.Carrying out in scrambling and cataloged procedure to packet, only to control bag, video packets and idle bit carry out scrambling and coding, scrambling and coding are not carried out to K code, by K code, the control bag in packet and video packets are cut, achieve receiving end when receiving packet, easily control bag and video packets can be distinguished, ignore in scrambling and cataloged procedure that to be the object of K code be, because K code is specific coding, it is characterized in that including continuous 61 or continuous 60, certainly there will not be in the data of this feature after coding of the present invention, therefore receiving terminal can identify K code easily, and with the mark of K code as byte-aligned, namely receiving end gets final product the interval of byte after finding K code, the byte of decoding is partitioned into for finally carrying out decoding.
Wherein, the concrete mode of packet being carried out to scrambling and descrambling is: undertaken by linear feedback shift register (LinearFeedback Shift Register is called for short LFSR) polynomial expression, LFSR polynomial expression is G (x)=X
16+ X
5+ X
4+ X
3+ 1, the data of every byte all carry out scrambling/descrambling with the opposite direction of the most most-significant byte of LFSR:
dout_tmp[0]＝din_de[0]^lfsr_16_i[15]；
dout_tmp[1]＝din_de[1]^lfsr_16_i[14]；
dout_tmp[2]＝din_de[2]^lfsr_16_i[13]；
dout_tmp[3]＝din_de[3]^lfsr_16_i[12]；
dout_tmp[4]＝din_de[4]^lfsr_16_i[11]；
dout_tmp[5]＝din_de[5]^lfsr_16_i[10]；
dout_tmp[6]＝din_de[6]^lfsr_16_i[9]；
dout_tmp[7]＝din_de[7]^lfsr_16_i[8]；
Shown in the following verilog code of LFSR model:
Further, when there is two pairs of differential signals when between TCON and SD, accordingly, display panel internal interface has two data channels, on the data channel that display data are mapped as display panel internal interface, packets comprise: display data are mapped as respectively the packet on two data channels, wherein, the control bag on two data channels in packet is identical, when having a pair differential signal when between TCON and SD, display panel internal interface only has a data channel.Wherein, display data are mapped as packet on data channel mainly: display data are carried out 6bpc pattern or 8bpc mode map, bpc refers to every colour bits (bit per color).
Below with regard to the number of data channels difference that display panel internal interface has, carry out mapping the video pixel that the pattern difference adopted illustrates each byte in video packets to display data:
Situation one: when display panel internal interface has a data channel and display data carry out 8bpc mode map, as shown in Figure 2, the 0th of the X byte of video packets is followed successively by Ri [0] to the 7th, Ri [1] to Ri [7], the 0th of the X+1 byte of video packets is followed successively by Gi [0] to the 7th, Gi [1] to Gi [7], the 0th of the X+2 byte of video packets is followed successively by Bi [0] to the 7th, Bi [1] to Bi [7], wherein, Ri [n] is the quantized value of red component in single pixel, Gi [n] is the quantized value of single pixel Green component, Bi [n] is the quantized value of blue component in single pixel, X, i is nonnegative integer, n=0 ~ 7.
Situation two: when display panel internal interface has two data channels and display data carry out 8bpc mode map:
As shown shown in 3a and table 3b, if the number of pixels in each cutting video line is even number, then the 0th of X byte of the first video packets is followed successively by Ri [0] to the 7th, Ri [1] to Ri [7], the 0th of the X+1 byte of the first video packets is followed successively by Gi [0] to the 7th, Gi [1] to Gi [7], the 0th of the X+2 byte of the first video packets is followed successively by Bi [0] to the 7th, Bi [1] to Bi [7], wherein, first video packets is the video packets in two data channels on a data channel in packet, the 0th of the X byte of the second video packets is followed successively by R (i+1) [0] to the 7th, R (i+1) [1] is to R (i+1) [7], the 0th of the X+1 byte of the second video packets is followed successively by G (i+1) [0] to the 7th, G (i+1) [1] is to G (i+1) [7], the 0th of the X+2 byte of the second video packets is followed successively by B (i+1) [0] to the 7th, B (i+1) [1] is to B (i+1) [7], wherein, second video packets is the video packets in two data channels on another data channel in packet,
As shown in figures 4 a and 4b, if when number of pixels is odd number, the first video packets when first video packets is even number with number of pixels is identical, everybody of the X byte of the second video packets, X+1 byte and X+2 byte is 0, and wherein, Ri [n] is the quantized value of red component in single pixel, Gi [n] is the quantized value of single pixel Green component, Bi [n] for the quantized value of blue component in single pixel, X, i be nonnegative integer, n=0 ~ 7.
Situation three: when display panel internal interface has a data channel and display data carry out 6bpc mode map:
As shown in Figure 5 a, if the number of pixels in each cutting video line is 4N, then the 0th of X byte of video packets is followed successively by Gi [0] to the 7th, Gi [1], Ri [0], Ri [1] to Ri [5], the 0th of the X+1 byte of video packets is followed successively by Gi [2] to the 7th, Gi [3], Bi [0], Bi [1] to Bi [5], the 0th of the X+2 byte of video packets is followed successively by Gi [4] to the 7th, Gi [5], R (i+1) [0], R (i+1) [1], to R (i+1) [5], the 0th of the X+3 byte of video packets is followed successively by G (i+1) [0] to the 7th, G (i+1) [1], B (i+1) [0], B (i+1) [1], to B (i+1) [5], the 0th of the X+4 byte of video packets is followed successively by G (i+1) [2] to the 7th, G (i+1) [3] are to G (i+1) [5], G (i+2) [0], G (i+2) [1], to G (i+2) [3], the 0th of the X+5 byte of video packets is followed successively by G (i+2) [4] to the 7th, G (i+2) [5], R (i+2) [0], R (i+2) [1], to R (i+2) [5], the 0th of the X+6 byte of video packets is followed successively by G (i+3) [0] to the 7th, G (i+3) [1], B (i+2) [0], B (i+2) [1], to B (i+2) [5], the 0th of the X+7 byte of video packets is followed successively by G (i+3) [2] to the 7th, G (i+3) [3], R (i+3) [0], R (i+3) [1], to R (i+3) [5], the 0th of the X+8 byte of video packets is followed successively by G (i+3) [4] to the 7th, G (i+3) [5], B (i+3) [0], B (i+3) [1] is to B (i+3) [5],
As shown in Figure 5 b, if number of pixels is 4N+1, when then the X byte of video packets, X+1 byte are 4N with number of pixels, the X byte of video packets is identical respectively with X+1 byte, the 0th and the 1st of the X+2 byte of video packets is followed successively by Gi [4] and Gi [5], and the 2nd of the X+2 byte of video packets is 0 to the 7th;
As shown in Figure 5 c, if number of pixels is 4N+2, the X byte of video packets when then the X byte of video packets, X+1 byte to X+3 byte are 4N with number of pixels, X+1 byte are identical respectively to X+3 byte, the 0th to the 3rd of the X+4 byte of video packets is followed successively by G (i+1) [2], G (i+1) [3] to G (i+1) [5], and the 4th of the X+4 byte of video packets is 0 to the 7th;
As fig 5d, if number of pixels is 4N+3, the then X byte of video packets, the X byte of video packets when X+1 byte to X+5 byte and number of pixels is 4N, X+1 byte is identical respectively to X+5 byte, the 2nd of the X+6 byte of video packets is followed successively by B (i+2) [0] to the 7th, B (i+2) [1] is to B (i+2) [5], the 0th and the 1st of the X+6 byte of video packets is 0, wherein, Ri [n] is the quantized value of red component in single pixel, Gi [n] is the quantized value of single pixel Green component, Bi [n] is the quantized value of blue component in single pixel, X, i, N is nonnegative integer, n=0 ~ 5.
Situation four: when display panel internal interface has two data channels and display data carry out 6bpc mode map:
As shown in figure 6 a and 6b, if the number of pixels in each cutting video line is 8N, then the 0th of X byte of the first video packets is followed successively by Gi [0] to the 7th, Gi [1], Ri [0], Ri [1] to Ri [5], the 0th of the X+1 byte of the first video packets is followed successively by Gi [2] to the 7th, Gi [3], Bi [0], Bi [1] to Bi [5], the 0th of the X+2 byte of the first video packets is followed successively by Gi [4] to the 7th, Gi [5], R (i+2) [0], R (i+2) [1], to R (i+2) [5], the 0th of the X+3 byte of the first video packets is followed successively by G (i+2) [0] to the 7th, G (i+2) [1], B (i+2) [0], B (i+2) [1], to B (i+2) [5], the 0th of the X+4 byte of the first video packets is followed successively by G (i+2) [2] to the 7th, G (i+2) [3] are to G (i+2) [5], G (i+4) [0], G (i+4) [1], to G (i+4) [3], the 0th of the X+5 byte of the first video packets is followed successively by G (i+4) [4] to the 7th, G (i+4) [5], R (i+4) [0], R (i+4) [1], to R (i+4) [5], the 0th of the X+6 byte of the first video packets is followed successively by G (i+6) [0] to the 7th, G (i+6) [1], B (i+4) [0], B (i+4) [1], to B (i+4) [5], the 0th of the X+7 byte of the first video packets is followed successively by G (i+6) [2] to the 7th, G (i+6) [3], R (i+6) [0], R (i+6) [1], to R (i+6) [5], the 0th of the X+8 byte of the first video packets is followed successively by G (i+6) [4] to the 7th, G (i+6) [5], B (i+6) [0], B (i+6) [1] is to B (i+6) [5], wherein, first video packets is the video packets in two data channels on a data channel in packet, and the 0th of the X byte of the second video packets is followed successively by G (i+1) [0] to the 7th, G (i+1) [1], R (i+1) [0], R (i+1) [1], to R (i+1) [5], the 0th of the X+1 byte of the second video packets is followed successively by G (i+1) [2] to the 7th, G (i+1) [3], B (i+1) [0], B (i+1) [1], to B (i+1) [5], the 0th of the X+2 byte of the second video packets is followed successively by G (i+1) [4] to the 7th, G (i+1) [5], R (i+3) [0], R (i+3) [1], to R (i+3) [5], the 0th of the X+3 byte of the second video packets is followed successively by G (i+3) [0] to the 7th, G (i+3) [1], B (i+3) [0], B (i+3) [1], to B (i+3) [5], the 0th of the X+4 byte of the second video packets is followed successively by G (i+3) [2] to the 7th, G (i+3) [3] are to G (i+3) [5], G (i+5) [0], G (i+5) [1], to G (i+5) [3], the 0th of the X+5 byte of the second video packets is followed successively by G (i+5) [4] to the 7th, G (i+5) [5], R (i+5) [0], R (i+5) [1], to R (i+5) [5], the 0th of the X+6 byte of the second video packets is followed successively by G (i+7) [0] to the 7th, G (i+7) [1], B (i+5) [0], B (i+5) [1], to B (i+5) [5], the 0th of the X+7 byte of the second video packets is followed successively by G (i+7) [2] to the 7th, G (i+7) [3], R (i+7) [0], R (i+7) [1], to R (i+7) [5], the 0th of the X+8 byte of the second video packets is followed successively by G (i+7) [4] to the 7th, G (i+7) [5], B (i+7) [0], B (i+7) [1], to B (i+7) [5], wherein, the second video packets is the video packets in two data channels on another data channel in packet,
As described relative to figs. 6c and 6d, if number of pixels is 8N+1, when then the X byte of the first video packets, X+1 byte are 8N with number of pixels, the X byte of the first video packets is identical respectively with X+1 byte, the 0th and the 1st of the X+2 byte of the first video packets is followed successively by Gi [4] and Gi [5], the 2nd to the 7th of the X+2 byte of the first video packets be the X byte of the 0, the second video packets, X+1 byte and X+2 byte everybody be 0;
As shown in Fig. 6 c and 6e, if number of pixels is 8N+2, the first video packets when then the first video packets is 8N+1 with number of pixels is identical, when the X byte of the second video packets, X+1 byte are 8N with number of pixels, the X byte of the second video packets is identical respectively with X+1 byte, the 0th and the 1st of the X+2 byte of the second video packets is followed successively by G (i+1) [4] and G (i+1) [5], and the 2nd of the X+2 byte of the second video packets is 0 to the 7th;
As shown in Fig. 6 f and 6g, if number of pixels is 8N+3, the then X byte of the first video packets, the X byte of the first video packets when X+1 byte to X+3 byte and number of pixels is 8N, X+1 byte is identical respectively to X+3 byte, the 0th to the 3rd of the X+4 byte of the first video packets is followed successively by G (i+2) [2] to G (i+2) [5], the 4th of the X+4 byte of the first video packets is 0 to the 7th, when the X byte of the second video packets is 8N with X+1 byte with number of pixels, the X byte of the second video packets is identical respectively with X+1 byte, the 0th and the 1st of the X+2 byte of the second video packets is followed successively by G (i+1) [4] and G (i+1) [5], the 2nd to the 7th of the X+2 byte of the second video packets, X+3 and the X+4 byte of the second video packets are 0,
As shown in Fig. 6 f and 6h, if number of pixels is 8N+4, the first video packets when then the first video packets is 8N+3 with number of pixels is identical, the X byte of the second video packets when the X byte of the second video packets, X+1 byte to X+3 byte are 8N with number of pixels, X+1 byte are identical respectively to X+3 byte, the 0th to the 3rd of the X+4 byte of the second video packets is followed successively by G (i+3) [2] to G (i+3) [5], and the 4th of the X+4 byte of the second video packets is 0 to the 7th;
As shown in Fig. 6 i and 6j, if number of pixels is 8N+5, the then X byte of the first video packets, the X byte of the first video packets when X+1 byte to X+5 byte and number of pixels is 8N, X+1 byte is identical respectively to X+5 byte, the 0th and the 1st of the X+6 byte of the first video packets is 0, the 2nd to the 7th of the X+6 byte of the first video packets is followed successively by B (i+4) [0] to B (i+4) [5], the X byte of the second video packets, the X byte of the second video packets when X+1 byte to X+3 byte and number of pixels is 8N, X+1 byte is identical respectively to X+3 byte, the 0th to the 3rd of the X+4 byte of the second video packets is followed successively by G (i+3) [2] to G (i+3) [5], the 4th to the 7th of the X+4 byte of the second video packets, X+5 byte and the X+6 byte of the second video packets are 0,
As shown in Fig. 6 i and 6k, if number of pixels is 8N+6, the first video packets when then the first video packets is 8N+5 with number of pixels is identical, the X byte of the second video packets when the X byte of the second video packets, X+1 byte to X+5 byte are 8N with number of pixels, X+1 byte are identical respectively to X+5 byte, 0th and the 1st the 2nd to the 7th of being the X+6 byte of the 0, the second video packets of the X+6 byte of the second video packets is followed successively by B (i+5) [0] to B (i+5) [5];
As shown in Fig. 6 l and 6m, if number of pixels is 8N+7, the first video packets when then the first video packets is 8N with number of pixels is identical, the X byte of the second video packets, the X byte of the second video packets when X+1 byte to X+5 byte and number of pixels is 8N, X+1 byte is identical respectively to X+5 byte, the 2nd of the X+6 byte of the second video packets is followed successively by B (i+5) [0] to the 7th, B (i+5) [1] is to B (i+5) [5], the 0th and the 1st of the X+6 byte of the second video packets, X+7 byte and the X+8 byte of the second video packets are 0,
Wherein, Ri [n] is the quantized value of red component in single pixel, Gi [n] for the quantized value of single pixel Green component, Bi [n] be the quantized value of blue component in single pixel, X, i, N are nonnegative integer, n=0 ~ 5.
The embodiment of the present invention additionally provides a kind of data transmission device of display panel internal interface, is specifically introduced below to the data transmission device of the display panel internal interface that the embodiment of the present invention provides:
Fig. 2 is the schematic diagram of the data transmission device of display panel internal interface according to the embodiment of the present invention, and as shown in Figure 2, the data transmission device that this embodiment provides comprises:
Mapping block 10, packet on the data channel display data of TCON side being mapped as display panel internal interface, TCON refers to the time schedule controller in display panel, that is to say that the time schedule controller that display panel internal interface connects, data channel are the passage of transmitting terminal to receiving end transmission data of display panel internal interface.
Coding module 20, for encoding to packet, preferably, before coding module 20 pairs of packets being encoded, first carrying out scrambling by scrambling module to packet, then being encoded to the packet after scrambling by coding module.
Sending module 30, for sending the packet after coding via data channel, employing fixed rate, that is, sending module 30 is embedded in carrying out communication clock information used in data channel.
Receiver module 40, for receiving the packet of sending module transmission, and obtains clock information according to fixed rate corresponding to packet, that is, fixed rate when sending packet according to sending module 30 obtains clock information.
Decoder module 50, for decoding to packet according to clock information, preferably, before decoder module 50 to be decoded to packet according to clock information, first carries out descrambling by descrambling module to packet.
Transport module 60, for by decoded data packet transmission to SD, accordingly, drive circuit chip that the data packet transmission after descrambling connects to SD, SD for display panel internal interface by output module 60 (Source Driver is called for short SD).
The data transmission device of the display panel internal interface of the embodiment of the present invention, adopt mode clock information being embedded in data channel, make receiving end can obtain clock information by the fixed rate corresponding according to packet, enhance Electro Magnetic Compatibility, solve the problem that in prior art, the electromagnetic interference (EMI) of display panel is higher, and then reach the effect reducing electromagnetic interference (EMI), improve anti-interference.Wherein, after first scrambling being carried out to packet by scrambling module, then sent by sending module, correspondingly, after carrying out descrambling by descrambling module, then transferred to the mode of SD by transport module, electromagnetic interference (EMI) can be reduced further.
As can be seen from the above description, present invention achieves the effect reducing electromagnetic interference (EMI), improve anti-interference.
It should be noted that, can perform in the computer system of such as one group of computer executable instructions in the step shown in the process flow diagram of accompanying drawing, and, although show logical order in flow charts, but in some cases, can be different from the step shown or described by order execution herein.
Obviously, those skilled in the art should be understood that, above-mentioned of the present invention each module or each step can realize with general calculation element, they can concentrate on single calculation element, or be distributed on network that multiple calculation element forms, alternatively, they can realize with the executable program code of calculation element, thus, they can be stored and be performed by calculation element in the storage device, or they are made into each integrated circuit modules respectively, or the multiple module in them or step are made into single integrated circuit module to realize.Like this, the present invention is not restricted to any specific hardware and software combination.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (11)
1. a data transmission method for display panel internal interface, is characterized in that, comprising:
Packet on the data channel that the display data of the time schedule controller TCON side in described display panel are mapped as described display panel internal interface by the transmitting terminal of display panel internal interface;
Described transmitting terminal carries out scrambling to described packet, comprises and carries out scrambling by linear feedback shift register LFSR polynomial expression to described packet, and wherein, LFSR polynomial expression is: G (x)=X
16+ X
5+ X
4+ X
3+ 1;
Described transmitting terminal is encoded to the described packet after scrambling;
Described transmitting terminal sends the receiving end of the packet after coding to described display panel internal interface via described data channel, employing fixed rate;
The described fixed rate that described receiving end is corresponding according to described packet obtains clock information;
Described receiving end carries out descrambling to described packet;
Described receiving end is decoded to the described packet after descrambling according to described clock information; And
The drive circuit chip SD that decoded data packet transmission to described internal interface connects by described receiving end.
2. method according to claim 1, is characterized in that, described packet comprises the first space code successively, controls bag, video packets, the second space code and idle bit, and wherein, described first space code and described second space code are different space codes.
3. method according to claim 2, is characterized in that, carries out scrambling and coding comprises to described packet: only carry out scrambling and coding to described control bag, described video packets and described idle bit.
4. method according to claim 2, is characterized in that, described idle bit comprises whole zero bytes before scrambling and coding, and described control handbag is drawn together the static state in data transmission procedure or dynamically arranges order.
5. method according to claim 2, is characterized in that,
When there is two pairs of differential signals when between described TCON and described SD, described display panel internal interface has two data channels, on the data channel described display data being mapped as described display panel internal interface, packet comprises: described display data are mapped as packet on described two data channels respectively, wherein, control bag on described two data channels in packet is identical
When having a pair differential signal when between described TCON and described SD, described display panel internal interface only has a data channel.
6. method according to claim 5, is characterized in that, is comprised by the packet that described display data are mapped as on data channel: described display data are carried out 6bpc pattern or 8bpc mode map.
7. method according to claim 6, it is characterized in that, when described display panel internal interface has a data channel and described display data carry out 8bpc mode map, the 0th of the X byte of described video packets is followed successively by Ri [0] to the 7th, Ri [1] to Ri [7], the 0th of the X+1 byte of described video packets is followed successively by Gi [0] to the 7th, Gi [1] to Gi [7], the 0th of the X+2 byte of described video packets is followed successively by Bi [0] to the 7th, Bi [1] to Bi [7], wherein, Ri [n] is the quantized value of red component in single pixel, Gi [n] is the quantized value of single pixel Green component, Bi [n] is the quantized value of blue component in single pixel, X, i is nonnegative integer, n=0 ~ 7.
8. method according to claim 6, is characterized in that, when described display panel internal interface has two data channels and described display data carry out 8bpc mode map,
If the number of pixels in each cutting video line is even number,
Then the 0th to the 7th of X byte of the first video packets is followed successively by Ri [0], Ri [1] to Ri [7], the 0th to the 7th of the X+1 byte of described first video packets is followed successively by Gi [0], Gi [1] to Gi [7], the 0th to the 7th of the X+2 byte of described first video packets is followed successively by Bi [0], Bi [1] to Bi [7], wherein, described first video packets is the video packets in described two data channels on a data channel in packet
The 0th of the X byte of the second video packets is followed successively by R (i+1) [0] to the 7th, R (i+1) [1] is to R (i+1) [7], the 0th of the X+1 byte of described second video packets is followed successively by G (i+1) [0] to the 7th, G (i+1) [1] is to G (i+1) [7], the 0th of the X+2 byte of described second video packets is followed successively by B (i+1) [0] to the 7th, B (i+1) [1] is to B (i+1) [7], wherein, described second video packets is the video packets in described two data channels on another data channel in packet,
If when described number of pixels is odd number, described first video packets when described first video packets is even number with described number of pixels is identical, and everybody of the X byte of described second video packets, X+1 byte and X+2 byte is 0,
Wherein, Ri [n] is the quantized value of red component in single pixel, and Gi [n] is the quantized value of single pixel Green component, Bi [n] for the quantized value of blue component in single pixel, X, i be nonnegative integer, n=0 ~ 7.
9. method according to claim 6, is characterized in that, when described display panel internal interface has a data channel and described display data carry out 6bpc mode map,
If the number of pixels in each cutting video line is 4N, then the 0th of X byte of described video packets is followed successively by Gi [0] to the 7th, Gi [1], Ri [0], Ri [1] to Ri [5], the 0th of the X+1 byte of described video packets is followed successively by Gi [2] to the 7th, Gi [3], Bi [0], Bi [1] to Bi [5], the 0th of the X+2 byte of described video packets is followed successively by Gi [4] to the 7th, Gi [5], R (i+1) [0], R (i+1) [1], to R (i+1) [5], the 0th of the X+3 byte of described video packets is followed successively by G (i+1) [0] to the 7th, G (i+1) [1], B (i+1) [0], B (i+1) [1], to B (i+1) [5], the 0th of the X+4 byte of described video packets is followed successively by G (i+1) [2] to the 7th, G (i+1) [3] are to G (i+1) [5], G (i+2) [0], G (i+2) [1], to G (i+2) [3], the 0th of the X+5 byte of described video packets is followed successively by G (i+2) [4] to the 7th, G (i+2) [5], R (i+2) [0], R (i+2) [1], to R (i+2) [5], the 0th of the X+6 byte of described video packets is followed successively by G (i+3) [0] to the 7th, G (i+3) [1], B (i+2) [0], B (i+2) [1], to B (i+2) [5], the 0th of the X+7 byte of described video packets is followed successively by G (i+3) [2] to the 7th, G (i+3) [3], R (i+3) [0], R (i+3) [1], to R (i+3) [5], the 0th of the X+8 byte of described video packets is followed successively by G (i+3) [4] to the 7th, G (i+3) [5], B (i+3) [0], B (i+3) [1] is to B (i+3) [5],
If described number of pixels is 4N+1, when then the X byte of described video packets, X+1 byte are 4N with described number of pixels, the X byte of described video packets is identical respectively with X+1 byte, the 0th and the 1st of the X+2 byte of described video packets is followed successively by Gi [4] and Gi [5], and the 2nd of the X+2 byte of described video packets is 0 to the 7th;
If described number of pixels is 4N+2, the X byte of described video packets when then the X byte of described video packets, X+1 byte to X+3 byte are 4N with described number of pixels, X+1 byte are identical respectively to X+3 byte, the 0th to the 3rd of the X+4 byte of described video packets is followed successively by G (i+1) [2], G (i+1) [3] to G (i+1) [5], and the 4th of the X+4 byte of described video packets is 0 to the 7th;
If described number of pixels is 4N+3, the X byte of described video packets when then the X byte of described video packets, X+1 byte to X+5 byte are 4N with described number of pixels, X+1 byte are identical respectively to X+5 byte, the 2nd to the 7th of the X+6 byte of described video packets is followed successively by B (i+2) [0], B (i+2) [1] to B (i+2) [5], the 0th and the 1st of the X+6 byte of described video packets is 0
Wherein, Ri [n] is the quantized value of red component in single pixel, Gi [n] for the quantized value of single pixel Green component, Bi [n] be the quantized value of blue component in single pixel, X, i, N are nonnegative integer, n=0 ~ 5.
10. method according to claim 6, is characterized in that, when described display panel internal interface has two data channels and described display data carry out 6bpc mode map,
If the number of pixels in each cutting video line is 8N, then
The 0th of the X byte of the first video packets is followed successively by Gi [0] to the 7th, Gi [1], Ri [0], Ri [1] to Ri [5], the 0th of the X+1 byte of described first video packets is followed successively by Gi [2] to the 7th, Gi [3], Bi [0], Bi [1] to Bi [5], the 0th of the X+2 byte of described first video packets is followed successively by Gi [4] to the 7th, Gi [5], R (i+2) [0], R (i+2) [1], to R (i+2) [5], the 0th of the X+3 byte of described first video packets is followed successively by G (i+2) [0] to the 7th, G (i+2) [1], B (i+2) [0], B (i+2) [1], to B (i+2) [5], the 0th of the X+4 byte of described first video packets is followed successively by G (i+2) [2] to the 7th, G (i+2) [3] are to G (i+2) [5], G (i+4) [0], G (i+4) [1], to G (i+4) [3], the 0th of the X+5 byte of described first video packets is followed successively by G (i+4) [4] to the 7th, G (i+4) [5], R (i+4) [0], R (i+4) [1], to R (i+4) [5], the 0th of the X+6 byte of described first video packets is followed successively by G (i+6) [0] to the 7th, G (i+6) [1], B (i+4) [0], B (i+4) [1], to B (i+4) [5], the 0th of the X+7 byte of described first video packets is followed successively by G (i+6) [2] to the 7th, G (i+6) [3], R (i+6) [0], R (i+6) [1], to R (i+6) [5], the 0th of the X+8 byte of described first video packets is followed successively by G (i+6) [4] to the 7th, G (i+6) [5], B (i+6) [0], B (i+6) [1], to B (i+6) [5], wherein, described first video packets is the video packets in described two data channels on a data channel in packet,
The 0th of the X byte of the second video packets is followed successively by G (i+1) [0] to the 7th, G (i+1) [1], R (i+1) [0], R (i+1) [1], to R (i+1) [5], the 0th of the X+1 byte of described second video packets is followed successively by G (i+1) [2] to the 7th, G (i+1) [3], B (i+1) [0], B (i+1) [1], to B (i+1) [5], the 0th of the X+2 byte of described second video packets is followed successively by G (i+1) [4] to the 7th, G (i+1) [5], R (i+3) [0], R (i+3) [1], to R (i+3) [5], the 0th of the X+3 byte of described second video packets is followed successively by G (i+3) [0] to the 7th, G (i+3) [1], B (i+3) [0], B (i+3) [1], to B (i+3) [5], the 0th of the X+4 byte of described second video packets is followed successively by G (i+3) [2] to the 7th, G (i+3) [3] are to G (i+3) [5], G (i+5) [0], G (i+5) [1], to G (i+5) [3], the 0th of the X+5 byte of described second video packets is followed successively by G (i+5) [4] to the 7th, G (i+5) [5], R (i+5) [0], R (i+5) [1], to R (i+5) [5], the 0th of the X+6 byte of described second video packets is followed successively by G (i+7) [0] to the 7th, G (i+7) [1], B (i+5) [0], B (i+5) [1], to B (i+5) [5], the 0th of the X+7 byte of described second video packets is followed successively by G (i+7) [2] to the 7th, G (i+7) [3], R (i+7) [0], R (i+7) [1], to R (i+7) [5], the 0th of the X+8 byte of described second video packets is followed successively by G (i+7) [4] to the 7th, G (i+7) [5], B (i+7) [0], B (i+7) [1], to B (i+7) [5], wherein, described second video packets is the video packets in described two data channels on another data channel in packet,
If described number of pixels is 8N+1, then the X byte of described first video packets, X+1 byte and described number of pixels for the X byte of the first video packets described in during 8N identical respectively with X+1 byte, the 0th and the 1st of the X+2 byte of described first video packets is followed successively by Gi [4] and Gi [5], the 2nd of the X+2 byte of described first video packets is 0 to the 7th, and everybody of the X byte of described second video packets, X+1 byte and X+2 byte is 0;
If described number of pixels is 8N+2, described first video packets when then described first video packets is 8N+1 with described number of pixels is identical, the X byte of described second video packets, X+1 byte and described number of pixels for the X byte of the second video packets described in during 8N identical respectively with X+1 byte, the 0th and the 1st of the X+2 byte of described second video packets is followed successively by G (i+1) [4] and G (i+1) [5], and the 2nd of the X+2 byte of described second video packets is 0 to the 7th;
If described number of pixels is 8N+3, the then X byte of described first video packets, X+1 byte is to X byte for the first video packets described in during 8N of X+3 byte and described number of pixels, X+1 byte is identical respectively to X+3 byte, the 0th to the 3rd of the X+4 byte of described first video packets is followed successively by G (i+2) [2] to G (i+2) [5], the 4th of the X+4 byte of described first video packets is 0 to the 7th, the X byte of described second video packets and X+1 byte and described number of pixels for the X byte of the second video packets described in during 8N identical respectively with X+1 byte, the 0th and the 1st of the X+2 byte of described second video packets is followed successively by G (i+1) [4] and G (i+1) [5], the 2nd to the 7th of the X+2 byte of described second video packets, X+3 and the X+4 byte of described second video packets are 0,
If described number of pixels is 8N+4, described first video packets when then described first video packets is 8N+3 with described number of pixels is identical, the X byte that the X byte of described second video packets, X+1 byte are the second video packets described in during 8N to X+3 byte and described number of pixels, X+1 byte are identical respectively to X+3 byte, the 0th to the 3rd of the X+4 byte of described second video packets is followed successively by G (i+3) [2] to G (i+3) [5], and the 4th of the X+4 byte of described second video packets is 0 to the 7th;
If described number of pixels is 8N+5, the then X byte of described first video packets, X+1 byte is to X byte for the first video packets described in during 8N of X+5 byte and described number of pixels, X+1 byte is identical respectively to X+5 byte, the 0th and the 1st of the X+6 byte of described first video packets is 0, the 2nd to the 7th of the X+6 byte of described first video packets is followed successively by B (i+4) [0] to B (i+4) [5], the X byte of described second video packets, X+1 byte is to X byte for the second video packets described in during 8N of X+3 byte and described number of pixels, X+1 byte is identical respectively to X+3 byte, the 0th to the 3rd of the X+4 byte of described second video packets is followed successively by G (i+3) [2] to G (i+3) [5], the 4th to the 7th of the X+4 byte of described second video packets, X+5 byte and the X+6 byte of described second video packets are 0,
If described number of pixels is 8N+6, described first video packets when then described first video packets is 8N+5 with described number of pixels is identical, the X byte that the X byte of described second video packets, X+1 byte are the second video packets described in during 8N to X+5 byte and described number of pixels, X+1 byte are identical respectively to X+5 byte, the 0th and the 1st of the X+6 byte of described second video packets is 0, and the 2nd to the 7th of the X+6 byte of described second video packets is followed successively by B (i+5) [0] to B (i+5) [5];
If described number of pixels is 8N+7, described first video packets when then described first video packets is 8N with described number of pixels is identical, the X byte of described second video packets, X+1 byte is to X byte for the second video packets described in during 8N of X+5 byte and described number of pixels, X+1 byte is identical respectively to X+5 byte, the 2nd of the X+6 byte of described second video packets is followed successively by B (i+5) [0] to the 7th, B (i+5) [1] is to B (i+5) [5], the 0th and the 1st of the X+6 byte of described second video packets, X+7 byte and the X+8 byte of described second video packets are 0,
Wherein, Ri [n] is the quantized value of red component in single pixel, Gi [n] for the quantized value of single pixel Green component, Bi [n] be the quantized value of blue component in single pixel, X, i, N are nonnegative integer, n=0 ~ 5.
The data transmission device of 11. 1 kinds of display panel internal interfaces, is characterized in that, comprising:
Mapping block, packet on the data channel display data of the time schedule controller TCON side in described display panel being mapped as described display panel internal interface;
Scrambling module, for carrying out scrambling to described packet, comprising and carrying out scrambling by linear feedback shift register LFSR polynomial expression to described packet, wherein, LFSR polynomial expression is: G (x)=X
16+ X
5+ X
4+ X
3+ 1;
Coding module, for encoding to the described packet after scrambling;
Sending module, for sending the packet after coding to described display panel internal interface via described data channel, employing fixed rate;
Receiver module, for receiving the packet of described sending module transmission, and the described fixed rate corresponding according to described packet obtains clock information;
Descrambling module, for carrying out descrambling to described packet;
Decoder module, for decoding to the described packet after descrambling according to described clock information; And
Transport module, for the drive circuit chip SD connected by decoded data packet transmission to described internal interface.
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| CN108694917B (en) * | 2017-06-09 | 2021-10-22 | 京东方科技集团股份有限公司 | Data transmission method, assembly and display device |
| CN108696288B (en) * | 2017-06-09 | 2022-02-01 | 京东方科技集团股份有限公司 | Signal transmission method, transmitting unit, receiving unit and display device |
| CN112331135B (en) * | 2020-11-05 | 2021-09-24 | Tcl华星光电技术有限公司 | Display panel and driving method |
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