CN103199852A - Analog multiplier used in positive feedback circuit (PFC) - Google Patents
Analog multiplier used in positive feedback circuit (PFC) Download PDFInfo
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- CN103199852A CN103199852A CN201310080944XA CN201310080944A CN103199852A CN 103199852 A CN103199852 A CN 103199852A CN 201310080944X A CN201310080944X A CN 201310080944XA CN 201310080944 A CN201310080944 A CN 201310080944A CN 103199852 A CN103199852 A CN 103199852A
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Abstract
The invention belongs to the technical filed of electronics, and discloses an analog multiplier used in a positive feedback circuit (PFC). The analog multiplier comprises four modules, namely a preceding stage differential amplifier, an active attenuator, a secondary stage differential amplifier and an output circuit which is used for converting current signals into voltage signals. Compared with a traditional PFC multiplier circuit, the analog multiplier used in the PFC is provided with the active attenuator, negative feedback is used in the active attenuator, resistors are respectively arranged at emitter electrodes of P-type triodes in the secondary stage differential amplifier, a beta helper structure is used, and due to the structure, the non-linear error of the analog multiplier is enormously reduced.
Description
Technical field
The invention belongs to electronic technology field, relate to the analog multiplier circuit in the integrated circuit technique, be specifically related to a kind of analog multiplier that is used for PFC that reduces nonlinearity erron.
Background technology
Along with the various power electronic equipments that with the Switching Power Supply are representative are more and more, produce a large amount of current harmonics components and blowed back into electrical network, caused the harmonic pollution of electrical network.In order to suppress these current harmonics components, adopt Active PFC (Power Factor Correction is called for short PFC) technology usually.And analog multiplier is the indispensable modules of most PFC chips, and improves the linearity of multiplier, reduces the important directions that nonlinearity erron becomes the research analog multiplier.
Summary of the invention
The objective of the invention is in order to reduce the nonlinearity erron of analog multiplier in the PFC technology, and proposed a kind of analog multiplier for FPC, this analog multiplier has minimum nonlinearity erron.
Technical scheme of the present invention is:
A kind of analog multiplier for FPC, as shown in Figure 2, comprise module one, module two, module three, module four, wherein module one is the prime differential amplifier, module two is active attenuator, module three is second level differential amplifier, and module four is converted into the output circuit of voltage signal for current signal.
Described prime differential amplifier comprises two PMOS pipe MP1 and MP2, three NMOS pipe MN1, MN2 and MN3, a crossing current source I, two resistance R 1 and R2, and two positive-negative-positive triode QP1 and QP2; The source electrode of PMOS pipe MP1 and MP2 meets supply voltage VDD, its gate interconnection; The grid of PMOS pipe MP1 and drain electrode interconnection, and by constant-current source I ground connection GND; The drain electrode of PMOS pipe MP2 connects the emitter of positive-negative-positive triode QP1 on the one hand by resistance R 1, connect the emitter of positive-negative-positive triode QP2 on the other hand by resistance R 2; The base stage of positive-negative-positive triode QP1 is imported the first input signal VCOMP, the base stage input offset voltage VB of positive-negative-positive triode QP2; The source ground GND of NMOS pipe MN1, MN2 and MN3, the gate interconnection of NMOS pipe MN1 and MN2, the grid of NMOS pipe MN1 and the collector electrode that drains and interconnect and meet positive-negative-positive triode QP1, the drain electrode of NMOS pipe MN2 and MN3 connects the collector electrode of positive-negative-positive triode QP2, the grid of NMOS pipe MN3 and drain electrode interconnection.
Described active attenuator comprises PMOS pipe MP3, two NPN type triode QN1 and QN2, two positive-negative-positive triode QP3 and QP4, five resistance R 3, R4, R5, R6 and R7; The source electrode of PMOS pipe MP3 meets supply voltage VDD, and its grid connects the grid of PMOS pipe MP1 and MP2 in the prime differential amplifier, and its drain electrode connects base stage and the collector electrode of two NPN type triode QN1 and QN2 simultaneously; The emitter of NPN type triode QN1 order on the one hand connects the emitter of positive-negative-positive triode QP3 on the other hand by resistance R 3 and R6 ground connection GND by resistance R 4; The base stage of positive-negative-positive triode QP3 is by resistance R 6 ground connection GND; The emitter of NPN type triode QN2 connects the emitter of positive-negative-positive triode QP4 by resistance R 5, and the base stage of positive-negative-positive triode QP4 meets the second input signal VMULT, the grounded collector GND of positive-negative-positive triode QP3 and QP4 by resistance R 7.
Described second level differential amplifier comprises three positive-negative-positive triode QP5, QP6 and QP9, two NPN type triode QN3 and QN4, and a NMOS pipe MN4 also comprises two resistance R 8 and R9; The emitter of positive-negative-positive triode QP5 meets supply voltage VDD by resistance R 8, the emitter of positive-negative-positive triode QP6 meets supply voltage VDD by resistance R 9, the base stage interconnection of positive-negative-positive triode QP5 and QP6, the collector electrode of positive-negative-positive triode QP5 connects the collector electrode of NPN type triode QN3, and the collector electrode of positive-negative-positive triode QP6 connects the collector electrode of NPN type triode QN4; The emitter of positive-negative-positive triode QP9 connects the base stage of positive-negative-positive triode QP5 and QP6, and its base stage meets the collector electrode of positive-negative-positive triode QP5 and NPN type triode QN3, its grounded collector GND; The base stage of NPN type triode QN3 is connected to the emitter of NPN type triode QN1 in the attenuator of source, and the base stage of NPN type triode QN4 is connected to the emitter of NPN type triode QN2 in the attenuator of source; The emitter of NPN type triode QN3 and QN4 connects the drain electrode of NMOS pipe MN4 jointly, and the grid of NMOS pipe MN4 connects the grid of NMOS pipe MN3 in the prime differential amplifier, the source ground GND of NMOS pipe MN4.
The output circuit that described current signal is converted into voltage signal comprises three positive-negative-positive triode QP7, QP8 and QP9, and three resistance R 11, R12 and R13 also comprise a filter capacitor CL; The emitter of positive-negative-positive triode QP7 meets supply voltage VDD by resistance R 11, the emitter of positive-negative-positive triode QP8 meets supply voltage VDD by resistance R 12, the base stage interconnection of positive-negative-positive triode QP7 and QP8, the interconnection of the base stage of positive-negative-positive triode QP8 and collector electrode also connects the emitter of positive-negative-positive triode QP10, the base stage of positive-negative-positive triode QP10 connects the collector electrode of positive-negative-positive triode QP6 in the collector electrode of positive-negative-positive triode QP7 and the second level differential amplifier, the collector electrode of positive-negative-positive triode QP10 is by the parallel circuits ground connection GND of resistance R 13 and filter capacitor CL, and the collector electrode of positive-negative-positive triode QP10 is exported the output signal VOUT of whole analog multiplier.
The invention has the beneficial effects as follows: than conventional P FC multiplier circuit, the present invention adopts active attenuator shown in Fig. 2 module two, and in active attenuator, introduce negative feedback, P type triode emitter-base bandgap grading is introduced resistance respectively in module three, and adopt β helper structure, said structure has reduced the nonlinearity erron of multiplier greatly.
Description of drawings
Fig. 1 is analog multiplier circuit schematic diagram provided by the invention.
Fig. 2 is analog multiplier circuit structure chart provided by the invention.
Fig. 3 is analog multiplier circuit principle schematic provided by the invention.
Embodiment
The present invention is further illustrated below in conjunction with the drawings and specific embodiments.
Analog multiplier circuit provided by the invention as shown in Figure 1.
The analog multiplier that provides of the present invention, as shown in Figure 2, comprise module one, module two, module three, module four, wherein module one is the prime differential amplifier, module two is active attenuator, module three is second level differential amplifier, and module four is converted into the output circuit of voltage signal for current signal.
Described prime differential amplifier comprises two PMOS pipe MP1 and MP2, three NMOS pipe MN1, MN2 and MN3, a crossing current source I, two resistance R 1 and R2, and two positive-negative-positive triode QP1 and QP2; The source electrode of PMOS pipe MP1 and MP2 meets supply voltage VDD, its gate interconnection; The grid of PMOS pipe MP1 and drain electrode interconnection, and by constant-current source I ground connection GND; The drain electrode of PMOS pipe MP2 connects the emitter of positive-negative-positive triode QP1 on the one hand by resistance R 1, connect the emitter of positive-negative-positive triode QP2 on the other hand by resistance R 2; The base stage of positive-negative-positive triode QP1 is imported the first input signal VCOMP, the base stage input offset voltage VB of positive-negative-positive triode QP2; The source ground GND of NMOS pipe MN1, MN2 and MN3, the gate interconnection of NMOS pipe MN1 and MN2, the grid of NMOS pipe MN1 and the collector electrode that drains and interconnect and meet positive-negative-positive triode QP1, the drain electrode of NMOS pipe MN2 and MN3 connects the collector electrode of positive-negative-positive triode QP2, the grid of NMOS pipe MN3 and drain electrode interconnection.
Described active attenuator comprises PMOS pipe MP3, two NPN type triode QN1 and QN2, two positive-negative-positive triode QP3 and QP4, five resistance R 3, R4, R5, R6 and R7; The source electrode of PMOS pipe MP3 meets supply voltage VDD, and its grid connects the grid of PMOS pipe MP1 and MP2 in the prime differential amplifier, and its drain electrode connects base stage and the collector electrode of two NPN type triode QN1 and QN2 simultaneously; The emitter of NPN type triode QN1 order on the one hand connects the emitter of positive-negative-positive triode QP3 on the other hand by resistance R 3 and R6 ground connection GND by resistance R 4; The base stage of positive-negative-positive triode QP3 is by resistance R 6 ground connection GND; The emitter of NPN type triode QN2 connects the emitter of positive-negative-positive triode QP4 by resistance R 5, and the base stage of positive-negative-positive triode QP4 meets the second input signal VMULT, the grounded collector GND of positive-negative-positive triode QP3 and QP4 by resistance R 7.
Described second level differential amplifier comprises three positive-negative-positive triode QP5, QP6 and QP9, two NPN type triode QN3 and QN4, and a NMOS pipe MN4 also comprises two resistance R 8 and R9; The emitter of positive-negative-positive triode QP5 meets supply voltage VDD by resistance R 8, the emitter of positive-negative-positive triode QP6 meets supply voltage VDD by resistance R 9, the base stage interconnection of positive-negative-positive triode QP5 and QP6, the collector electrode of positive-negative-positive triode QP5 connects the collector electrode of NPN type triode QN3, and the collector electrode of positive-negative-positive triode QP6 connects the collector electrode of NPN type triode QN4; The emitter of positive-negative-positive triode QP9 connects the base stage of positive-negative-positive triode QP5 and QP6, and its base stage meets the collector electrode of positive-negative-positive triode QP5 and NPN type triode QN3, its grounded collector GND; The base stage of NPN type triode QN3 is connected to the emitter of NPN type triode QN1 in the attenuator of source, and the base stage of NPN type triode QN4 is connected to the emitter of NPN type triode QN2 in the attenuator of source; The emitter of NPN type triode QN3 and QN4 connects the drain electrode of NMOS pipe MN4 jointly, and the grid of NMOS pipe MN4 connects the grid of NMOS pipe MN3 in the prime differential amplifier, the source ground GND of NMOS pipe MN4.
The output circuit that described current signal is converted into voltage signal comprises three positive-negative-positive triode QP7, QP8 and QP9, and three resistance R 11, R12 and R13 also comprise a filter capacitor CL; The emitter of positive-negative-positive triode QP7 meets supply voltage VDD by resistance R 11, the emitter of positive-negative-positive triode QP8 meets supply voltage VDD by resistance R 12, the base stage interconnection of positive-negative-positive triode QP7 and QP8, the interconnection of the base stage of positive-negative-positive triode QP8 and collector electrode also connects the emitter of positive-negative-positive triode QP10, the base stage of positive-negative-positive triode QP10 connects the collector electrode of positive-negative-positive triode QP6 in the collector electrode of positive-negative-positive triode QP7 and the second level differential amplifier, the collector electrode of positive-negative-positive triode QP10 is by the parallel circuits ground connection GND of resistance R 13 and filter capacitor CL, and the collector electrode of positive-negative-positive triode QP10 is exported the output signal VOUT of whole analog multiplier.
Circuit working mechanism of the present invention is as follows:
Positive-negative-positive triode QP1 and QP2 form a differential pair in the module one (prime differential amplifier), and PMOS pipe MP2 mirror image MP1 electric current provides the differential pair current offset, and resistance R 1 and R2 are as the load of differential pair.QP1 and QP2 are identical triodes, V
COMP-V
B0, according to derivation,
NMOS pipe MN1 and MN2 form current mirror, so I
C2-I
C1=I
1
Make the multiplier can operate as normal, two applied signal voltages must be less than 2V
T, will dwindle input voltage range greatly like this, also just limited circuit application greatly.In order to enlarge the input range of input voltage, must carry out linear attenuation to input voltage, the input voltage after the decay is satisfied less than 2V
TThereby, can realize multiplication function.Therefore, another input at multiplier has added a voltage attenuation circuit.Voltage attenuation circuit is shown in module among Fig. 3 two (active attenuator).NPN type triode QN1 and QN2 are just the same, and positive-negative-positive triode QP3 and QP4 are also just the same, and the electric current of PMOS pipe MP3 mirror-image constant flow source I provides current offset for circuit, and the resistance of resistance R 4 and R5 equates (R
4=R
5), the relational expression of the first input signal VCOMP and output voltage V id is:
Arrangement can get:
Can find out thus, as long as adjust the value of R4 or I, just can obtain input voltage and well decay.Negative feedback is introduced in the active decay that adds 3 pairs of voltages of resistance R, has well improved the linearity of voltage attenuation circuit.
The resistance of resistance R 8 and R9 equates (R in the module three (second level differential amplifier)
8=R
9), positive-negative-positive triode QP5 and QP6 are just the same, and the two and QP9 form β helper structure, reduce the influence of β.NPN type triode QN3 and QN4 are also just the same, the electric current of MN3 in NMOS pipe MN4 mirror image module one (the prime differential amplifier), I
EE=I
1, the tail current biasing is provided for the cascode differential pair, and V
Id0, in like manner,
And I
C4-I
C3=I
2
In the module four (current signal is converted into the output circuit of voltage signal), the collector current of positive-negative-positive triode QP8 mirror image QP7, the electric current that flows through the QP10 collector electrode is approximately equal to I
C8, i.e. I
C8=I
C7=I
2, and V
OUT=I
C8R
13
In sum, arrangement obtains
The size of suitably adjusting R4, I2, I3 can obtain suitable output voltage gain, and the negative feedback of the present invention's employing, β helper structure, and load resistance has all reduced the nonlinearity erron of multiplier greatly.
Those of ordinary skill in the art will appreciate that embodiment described here is in order to help reader understanding's principle of the present invention, should to be understood that the protection range of inventing is not limited to such special statement and embodiment.Everyly make various possible being equal to according to foregoing description and replace or change, all be considered to belong to the protection range of claim of the present invention.
Claims (1)
1. analog multiplier that is used for FPC, comprise module one, module two, module three, module four, wherein module one is the prime differential amplifier, and module two is active attenuator, module three is second level differential amplifier, and module four is converted into the output circuit of voltage signal for current signal;
Described prime differential amplifier comprises two PMOS pipe MP1 and MP2, three NMOS pipe MN1, MN2 and MN3, a crossing current source I, two resistance R 1 and R2, and two positive-negative-positive triode QP1 and QP2; The source electrode of PMOS pipe MP1 and MP2 meets supply voltage VDD, its gate interconnection; The grid of PMOS pipe MP1 and drain electrode interconnection, and by constant-current source I ground connection GND; The drain electrode of PMOS pipe MP2 connects the emitter of positive-negative-positive triode QP1 on the one hand by resistance R 1, connect the emitter of positive-negative-positive triode QP2 on the other hand by resistance R 2; The base stage of positive-negative-positive triode QP1 is imported the first input signal VCOMP, the base stage input offset voltage VB of positive-negative-positive triode QP2; The source ground GND of NMOS pipe MN1, MN2 and MN3, the gate interconnection of NMOS pipe MN1 and MN2, the grid of NMOS pipe MN1 and the collector electrode that drains and interconnect and meet positive-negative-positive triode QP1, the drain electrode of NMOS pipe MN2 and MN3 connects the collector electrode of positive-negative-positive triode QP2, the grid of NMOS pipe MN3 and drain electrode interconnection;
Described active attenuator comprises PMOS pipe MP3, two NPN type triode QN1 and QN2, two positive-negative-positive triode QP3 and QP4, five resistance R 3, R4, R5, R6 and R7; The source electrode of PMOS pipe MP3 meets supply voltage VDD, and its grid connects the grid of PMOS pipe MP1 and MP2 in the prime differential amplifier, and its drain electrode connects base stage and the collector electrode of two NPN type triode QN1 and QN2 simultaneously; The emitter of NPN type triode QN1 order on the one hand connects the emitter of positive-negative-positive triode QP3 on the other hand by resistance R 3 and R6 ground connection GND by resistance R 4; The base stage of positive-negative-positive triode QP3 is by resistance R 6 ground connection GND; The emitter of NPN type triode QN2 connects the emitter of positive-negative-positive triode QP4 by resistance R 5, and the base stage of positive-negative-positive triode QP4 meets the second input signal VMULT, the grounded collector GND of positive-negative-positive triode QP3 and QP4 by resistance R 7;
Described second level differential amplifier comprises three positive-negative-positive triode QP5, QP6 and QP9, two NPN type triode QN3 and QN4, and a NMOS pipe MN4 also comprises two resistance R 8 and R9; The emitter of positive-negative-positive triode QP5 meets supply voltage VDD by resistance R 8, the emitter of positive-negative-positive triode QP6 meets supply voltage VDD by resistance R 9, the base stage interconnection of positive-negative-positive triode QP5 and QP6, the collector electrode of positive-negative-positive triode QP5 connects the collector electrode of NPN type triode QN3, and the collector electrode of positive-negative-positive triode QP6 connects the collector electrode of NPN type triode QN4; The emitter of positive-negative-positive triode QP9 connects the base stage of positive-negative-positive triode QP5 and QP6, and its base stage meets the collector electrode of positive-negative-positive triode QP5 and NPN type triode QN3, its grounded collector GND; The base stage of NPN type triode QN3 is connected to the emitter of NPN type triode QN1 in the attenuator of source, and the base stage of NPN type triode QN4 is connected to the emitter of NPN type triode QN2 in the attenuator of source; The emitter of NPN type triode QN3 and QN4 connects the drain electrode of NMOS pipe MN4 jointly, and the grid of NMOS pipe MN4 connects the grid of NMOS pipe MN3 in the prime differential amplifier, the source ground GND of NMOS pipe MN4;
The output circuit that described current signal is converted into voltage signal comprises three positive-negative-positive triode QP7, QP8 and QP9, and three resistance R 11, R12 and R13 also comprise a filter capacitor CL; The emitter of positive-negative-positive triode QP7 meets supply voltage VDD by resistance R 11, the emitter of positive-negative-positive triode QP8 meets supply voltage VDD by resistance R 12, the base stage interconnection of positive-negative-positive triode QP7 and QP8, the interconnection of the base stage of positive-negative-positive triode QP8 and collector electrode also connects the emitter of positive-negative-positive triode QP10, the base stage of positive-negative-positive triode QP10 connects the collector electrode of positive-negative-positive triode QP6 in the collector electrode of positive-negative-positive triode QP7 and the second level differential amplifier, the collector electrode of positive-negative-positive triode QP10 is by the parallel circuits ground connection GND of resistance R 13 and filter capacitor CL, and the collector electrode of positive-negative-positive triode QP10 is exported the output signal VOUT of whole analog multiplier.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2016119661A1 (en) * | 2015-01-27 | 2016-08-04 | 意瑞半导体（上海）有限公司 | Power factor correction circuit and multiplier |
| CN107092297A (en) * | 2017-06-13 | 2017-08-25 | 成都芯进电子有限公司 | Second order compensation band-gap reference circuit for signal amplifier |
| WO2021004140A1 (en) * | 2019-07-08 | 2021-01-14 | 神亚科技股份有限公司 | Multiplier device |
| CN114285385A (en) * | 2022-02-21 | 2022-04-05 | 成都芯翼科技有限公司 | Offset circuit of operational amplifier input current |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016119661A1 (en) * | 2015-01-27 | 2016-08-04 | 意瑞半导体（上海）有限公司 | Power factor correction circuit and multiplier |
| US10171035B2 (en) | 2015-01-27 | 2019-01-01 | Cosemitech (Shanghai) Co., Ltd. | Power factor correction circuit and multiplier |
| CN107092297A (en) * | 2017-06-13 | 2017-08-25 | 成都芯进电子有限公司 | Second order compensation band-gap reference circuit for signal amplifier |
| WO2021004140A1 (en) * | 2019-07-08 | 2021-01-14 | 神亚科技股份有限公司 | Multiplier device |
| CN114285385A (en) * | 2022-02-21 | 2022-04-05 | 成都芯翼科技有限公司 | Offset circuit of operational amplifier input current |
| CN114285385B (en) * | 2022-02-21 | 2022-06-03 | 成都芯翼科技有限公司 | Offset circuit of operational amplifier input current |
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