CN103197159B - A kind of SRAM type FPGA simultaneous switching noise verification method - Google Patents
A kind of SRAM type FPGA simultaneous switching noise verification method Download PDFInfo
- Publication number
- CN103197159B CN103197159B CN201310078268.2A CN201310078268A CN103197159B CN 103197159 B CN103197159 B CN 103197159B CN 201310078268 A CN201310078268 A CN 201310078268A CN 103197159 B CN103197159 B CN 103197159B
- Authority
- CN
- China
- Prior art keywords
- bank
- simultaneous switching
- switching noise
- synchro switch
- disturbed line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Tests Of Electronic Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Testing Electric Properties And Detecting Electric Faults (AREA)
Abstract
A kind of SRAM type FPGA simultaneous switching noise verification method, realize based on SRAM type FPGA simultaneous switching noise demo plant, this device comprises PC, FPGA socket, signal input unit and tunable load electric capacity; The verification method of SRAM type FPGA simultaneous switching noise comprises: the influencing each other and the relation of simultaneous switching noise and I/O port number, output switching activity speed, clock frequency, disturbed line position and load capacitance of simultaneous switching noise between maximum synchro switch quantity, different I/O-BANK in single I/O-BANK; In proof procedure, be that FPGA to be verified configures different test files by PC, and under the condition of different clock frequencies and load, the interference noise size detected on the sensitive signal wire in FPGA to be verified realizes the checking of FPGA device in simultaneous switching noise signal integrity.
Description
Technical field
The present invention relates to a kind of SRAM type FPGA simultaneous switching noise verification method, belong to the application verification technical field of FPGA.
Background technology
Along with the development of semiconductor technology, the integrated level of SRAM type FPGA constantly increases.Thus the I/O port of FPGA is on the increase and the more crypto set that distributes on the one hand, makes to be more prone to mutual interference between I/O; On the other hand due to power consumption and heat radiation, the operating voltage step-down of FPGA, makes I/O more responsive to interference.And in current high-performance FPGA system design, the I/O of FPGA is under lower voltage conditions, and what often have hundreds of I/O to walk abreast at the same time converts, as easy as rolling off a log generation simultaneous switching noise.Therefore, simultaneous switching noise is most important for the impact of system.
Summary of the invention
Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, provides a kind of SRAM type FPGA simultaneous switching noise verification method.
Technical solution of the present invention is:
A kind of SRAM type FPGA simultaneous switching noise verification method, comprises the influence factor checking of influence each other checking and the simultaneous switching noise of simultaneous switching noise between maximum synchro switch quantity validation, different I/O-BANK in single I/O-BANK;
In described single I/O-BANK, maximum synchro switch quantity validation comprises the steps:
(1) I/O-BANK of SRAM type FPGA is chosen;
(2) be static low level voltage by an I/O pin configuration adjacent with ground pin in this I/O-BANK, as disturbed line;
(3) be that synchro switch under LVTTL agreement exports by other I/O port arrangement in this I/O-BANK, the toggle frequency of setting synchro switch is to ensure between twice adjacent upset without influencing each other;
(4) configure the internal logic of SRAM type FPGA, I/O port upset number in I/O-BANK is changed periodically one by one from 0 to maximum port number;
(5) use oscillograph to detect noise size on disturbed line in real time, recording noise amplitude first time is more than the synchro switch number under LVTTL agreement during most high low level voltage;
(6) the disturbed line in step (2) is configured to static high level voltage, performs step (3) ~ (4);
(7) use oscillograph detects the noise size on disturbed line in real time, and recording noise amplitude is lower than the synchro switch number of high level voltage minimum under LVTTL agreement;
(8) be static low level voltage by I/O pin configuration adjacent with outputting drive voltage pin in this I/O-BANK, as disturbed line, perform step (3) ~ (5);
(9) the disturbed line in step (8) is configured to static high level voltage, performs step (3), step (4) and step (7) successively;
(10) select other I/O-BANK, repeated execution of steps (2) ~ (9), complete the checking of maximum synchro switch quantity in single I/O-BANK;
Between described different I/O-BANK, the checking that influences each other of simultaneous switching noise comprises the steps:
A () selects an I/O-BANK in SRAM type FPGA;
B an I/O pin configuration adjacent with ground pin in other each I/O-BANK is static low level voltage by (), as disturbed line;
C I/O port arrangement in the I/O-BANK of described selection is that the synchro switch under LVTTL agreement exports by (), the toggle frequency of setting synchro switch is to ensure between twice adjacent upset without influencing each other;
D the internal logic of () configuration SRAM type FPGA, makes I/O port upset number in I/O-BANK change periodically one by one from 0 to maximum port number;
E () use oscillograph detects the noise size on disturbed line in real time, record the noise amplitude in each I/O-BANK;
F disturbed line in step (b) is configured to static high level voltage by (), perform step (c) ~ (e);
G pin configuration adjacent with outputting drive voltage pin in other I/O-BANK is static low level signal by (), as disturbed line, perform (c) ~ (e)
H disturbed line in (g) is configured to static high level signal by (), perform (c) ~ (e);
I () all repeats (b) ~ (h) for remaining I/O-BANK, complete the interactional checking of simultaneous switching noise between different I/O-BANK;
The influence factor checking of described simultaneous switching noise comprises the steps:
(aa) in each I/O-BANK, select an I/O pin, be configured to static low level voltage, as disturbed line;
(bb) be that synchro switch under LVTTL agreement exports by other pin configuration in all I/O-BANK, control to export by internal logic, increase the number of output switching activity one by one;
(cc) adjust the output switching activity speed of interfering line, measure the size of simultaneous switching noise respectively;
(dd) adjusting the toggle frequency of synchro switch, is the size measuring simultaneous switching noise under the condition of 20MHz, 40MHz, 50MHz, 80MHz, 100MHz respectively at toggle frequency;
(ee) adjusting the load capacitance size of synchro switch, is the size measuring simultaneous switching noise under the condition of 34pf, 68pf, 90pf, 180pf respectively in load capacitance;
(ff) the disturbed line in (aa) is configured to static high level voltage, performs (bb) ~ (ee);
(gg) change the position of disturbed line, namely disturbed line is relative to the distance of ground or power pin, performs (bb) ~ (ff), completes the checking of the influence factor of simultaneous switching noise.
The influence factor of described simultaneous switching noise comprises the quantity of synchro switch, output switching activity speed, output switching activity frequency, disturbed line position and load capacitance size.
The toggle frequency of synchro switch is set as being not more than 60MHz in described step (3).
The present invention's beneficial effect is compared with prior art:
(1) the invention provides a SRAM type FPGA simultaneous switching noise verification method, according to the needs of device application checking, adjustment and measurement can be carried out to Verification Project or method at any time.
(2) the present invention can be general for the SRAM type FPGA of domestic different factories different size, and also can be general for the SRAM type FPGA of external Xilinx company different size, can to compare test to the simultaneous switching noise situation of different factory easily.
Accompanying drawing explanation
Fig. 1 is maximum synchro switch quantity validation method schematic diagram in single I/O-BANK;
Fig. 2 is the interactional verification method schematic diagram of simultaneous switching noise between different I/O-BANK;
Fig. 3 is the influence factor verification method schematic diagram of simultaneous switching noise;
Fig. 4 is demo plant schematic diagram.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described in detail.
A kind of SRAM type FPGA simultaneous switching noise verification method that the present invention proposes carries out based on such as lower device:
As shown in Figure 4, SRAM type FPGA simultaneous switching noise demo plant comprises: PC, FPGA socket, signal input unit and tunable load electric capacity;
PC: provide configuration file for FPGA to be verified and configure FPGA by JTAG mode;
FPGA socket: for FPGA to be verified and demo plant provide interface;
Signal input unit: the input signal providing the edge rise/fall time adjustable for FPGA to be verified;
Tunable load electric capacity: the load capacitance providing size adjustable for FPGA to be verified.
SRAM type FPGA simultaneous switching noise verification method of the present invention, comprises the influence factor checking of influence each other checking and the simultaneous switching noise of simultaneous switching noise between maximum synchro switch quantity validation, different I/O-BANK in single I/O-BANK.The influence factor of simultaneous switching noise comprises the quantity of synchro switch, output switching activity speed, output switching activity frequency, disturbed line position and load capacitance size.
Fpga chip has a lot of I/O port, and in order to convenient management, all I/O ports are divided into some I/O-BANK, the I/O-BANK of every a fpga chip determines when chip dispatches from the factory.
As shown in Figure 1, in single I/O-BANK, maximum synchro switch quantity validation comprises the steps:
(1) I/O-BANK of SRAM type FPGA is chosen;
(2) be static low level voltage by an I/O pin configuration adjacent with ground pin in this I/O-BANK, as disturbed line;
(3) be that synchro switch under LVTTL agreement exports by other I/O port arrangement in this I/O-BANK, the toggle frequency of setting synchro switch is to ensure between twice adjacent upset without influencing each other; The toggle frequency of synchro switch is set as being not more than 60MHz. in step (3)
(4) configure the internal logic of SRAM type FPGA, I/O port upset number in I/O-BANK is changed periodically one by one from 0 to maximum port number;
(5) use oscillograph to detect noise size on disturbed line in real time, recording noise amplitude first time is more than the synchro switch number under LVTTL agreement during most high low level voltage;
(6) the disturbed line in step (2) is configured to static high level voltage, performs step (3) ~ (4);
(7) use oscillograph detects the noise size on disturbed line in real time, and recording noise amplitude is lower than the synchro switch number of high level voltage minimum under LVTTL agreement;
(8) be static low level voltage by I/O pin configuration adjacent with outputting drive voltage pin in this I/O-BANK, as disturbed line, perform step (3) ~ (5);
(9) the disturbed line in step (8) is configured to static high level voltage, performs step (3), step (4) and step (7) successively;
(10) select other I/O-BANK, repeated execution of steps (2) ~ (9), complete the checking of maximum synchro switch quantity in single I/O-BANK.
The I/O port of FPGA can be configured to multiple transport protocols, to adapt to the digital signal of different voltage levvl.LVTTL agreement is the one of the I/O Port Profile of FPGA, the most frequently used, defines the voltage standard that I/O port judges digital signal true value (i.e. " 0 " and " 1 "), comprises minimum high level voltage and most high low level voltage.Wherein, minimum high level voltage is judge the minimum voltage requirement of digital signal as " 1 "; Most high low level voltage is judge the ceiling voltage requirement of digital signal as " 0 ".
As shown in Figure 2, between different I/O-BANK, the checking that influences each other of simultaneous switching noise comprises the steps:
A () selects an I/O-BANK in SRAM type FPGA;
B an I/O pin configuration adjacent with ground pin in other each I/O-BANK is static low level voltage by (), as disturbed line;
C I/O port arrangement in the I/O-BANK of described selection is that the synchro switch under LVTTL agreement exports by (), the toggle frequency of setting synchro switch is to ensure between twice adjacent upset without influencing each other;
D the internal logic of () configuration SRAM type FPGA, makes the upset of I/O port in I/O-BANK number from 0 to the change one by one of maximum synchro switch property one number time;
E () use oscillograph detects the noise size on disturbed line in real time, record the noise amplitude in each I/O-BANK;
F disturbed line in step (b) is configured to static high level voltage by (), perform step (c) ~ (e);
G pin configuration adjacent with outputting drive voltage pin in other I/O-BANK is static low level signal by (), as disturbed line, perform (c) ~ (e)
H disturbed line in (g) is configured to static high level signal by (), perform (c) ~ (e);
I () all repeats (b) ~ (h) for remaining I/O-BANK, complete the interactional checking of simultaneous switching noise between different I/O-BANK.
As shown in Figure 3, the influence factor checking of simultaneous switching noise comprises the steps:
(aa) in each I/O-BANK, select an I/O pin, be configured to static low level voltage, as disturbed line;
(bb) be that synchro switch under LVTTL agreement exports by other pin configuration in all I/O-BANK, control to export by internal logic, increase the number of output switching activity one by one;
(cc) adjust the output switching activity speed of interfering line, measure the size of simultaneous switching noise respectively;
(dd) adjusting the toggle frequency of synchro switch, is the size measuring simultaneous switching noise under the condition of 20MHz, 40MHz, 50MHz, 80MHz, 100MHz respectively at toggle frequency;
(ee) adjusting the load capacitance size of synchro switch, is the size measuring simultaneous switching noise under the condition of 34pf, 68pf, 90pf, 180pf respectively in load capacitance;
(ff) the disturbed line in (aa) is configured to static high level voltage, performs (bb) ~ (ee);
(gg) change the position of disturbed line, namely disturbed line is relative to the distance of ground or power pin, performs (bb) ~ (ff), completes the checking of the influence factor of simultaneous switching noise.
The content be not described in detail in instructions of the present invention belongs to the known technology of professional and technical personnel in the field.
Claims (3)
1. a SRAM type FPGA simultaneous switching noise verification method, is characterized in that comprising the influence factor checking of influence each other checking and the simultaneous switching noise of simultaneous switching noise between maximum synchro switch quantity validation, different I/O-BANK in single I/O-BANK;
In described single I/O-BANK, maximum synchro switch quantity validation comprises the steps:
(1) I/O-BANK of SRAM type FPGA is chosen;
(2) be static low level voltage by an I/O port arrangement adjacent with ground pin in this I/O-BANK, as disturbed line;
(3) be that synchro switch under LVTTL agreement exports by other I/O port arrangement in this I/O-BANK, the toggle frequency of setting synchro switch is to ensure between twice adjacent upset without influencing each other;
(4) configure the internal logic of SRAM type FPGA, I/O port upset number in I/O-BANK is changed periodically one by one from 0 to maximum port number;
(5) use oscillograph to detect noise size on disturbed line in real time, recording noise amplitude first time is more than the synchro switch number under LVTTL agreement during most high low level voltage;
(6) the disturbed line in step (2) is configured to static high level voltage, performs step (3) ~ (4);
(7) use oscillograph detects the noise size on disturbed line in real time, and recording noise amplitude is lower than the synchro switch number of high level voltage minimum under LVTTL agreement;
(8) be static low level voltage by I/O port arrangement adjacent with outputting drive voltage pin in this I/O-BANK, as disturbed line, perform step (3) ~ (5);
(9) the disturbed line in step (8) is configured to static high level voltage, performs step (3), step (4) and step (7) successively;
(10) select other I/O-BANK, repeated execution of steps (2) ~ (9), complete the checking of maximum synchro switch quantity in single I/O-BANK;
Between described different I/O-BANK, the checking that influences each other of simultaneous switching noise comprises the steps:
A () selects an I/O-BANK in SRAM type FPGA;
B an I/O port arrangement adjacent with ground pin in other each I/O-BANK is static low level voltage by (), as disturbed line;
C I/O port arrangement in the I/O-BANK of described selection is that the synchro switch under LVTTL agreement exports by (), the toggle frequency of setting synchro switch is to ensure between twice adjacent upset without influencing each other;
D the internal logic of () configuration SRAM type FPGA, makes I/O port upset number in I/O-BANK change periodically one by one from 0 to maximum port number;
E () use oscillograph detects the noise size on disturbed line in real time, record the noise amplitude in each I/O-BANK;
F disturbed line in step (b) is configured to static high level voltage by (), perform step (c) ~ (e);
G port arrangement adjacent with outputting drive voltage pin in other I/O-BANK is static low level signal by (), as disturbed line, perform (c) ~ (e)
H disturbed line in (g) is configured to static high level signal by (), perform (c) ~ (e);
I () all repeats (b) ~ (h) for remaining I/O-BANK, complete the interactional checking of simultaneous switching noise between different I/O-BANK;
The influence factor checking of described simultaneous switching noise comprises the steps:
(aa) in each I/O-BANK, select an I/O port, be configured to static low level voltage, as disturbed line;
(bb) be that synchro switch under LVTTL agreement exports by other pin configuration in all I/O-BANK, control to export by internal logic, increase the number of output switching activity one by one;
(cc) adjust the output switching activity speed of interfering line, measure the size of simultaneous switching noise respectively;
(dd) adjusting the toggle frequency of synchro switch, is the size measuring simultaneous switching noise under the condition of 20MHz, 40MHz, 50MHz, 80MHz, 100MHz respectively at toggle frequency;
(ee) adjusting the load capacitance size of synchro switch, is the size measuring simultaneous switching noise under the condition of 34pf, 68pf, 90pf, 180pf respectively in load capacitance;
(ff) the disturbed line in (aa) is configured to static high level voltage, performs (bb) ~ (ee);
(gg) change the position of disturbed line, namely disturbed line is relative to the distance of ground or power pin, performs (bb) ~ (ff), completes the checking of the influence factor of simultaneous switching noise.
2. a kind of SRAM type FPGA simultaneous switching noise verification method according to claim 1, is characterized in that: the influence factor of described simultaneous switching noise comprises the load capacitance size of the quantity of synchro switch, the output switching activity speed of synchro switch, the output switching activity frequency of synchro switch, the disturbed line position of synchro switch and synchro switch.
3. a kind of SRAM type FPGA simultaneous switching noise verification method according to claim 1, is characterized in that: set the toggle frequency of synchro switch as being not more than 60MHz in described step (3).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310078268.2A CN103197159B (en) | 2013-03-12 | 2013-03-12 | A kind of SRAM type FPGA simultaneous switching noise verification method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310078268.2A CN103197159B (en) | 2013-03-12 | 2013-03-12 | A kind of SRAM type FPGA simultaneous switching noise verification method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103197159A CN103197159A (en) | 2013-07-10 |
| CN103197159B true CN103197159B (en) | 2015-08-12 |
Family
ID=48719843
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310078268.2A Active CN103197159B (en) | 2013-03-12 | 2013-03-12 | A kind of SRAM type FPGA simultaneous switching noise verification method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103197159B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104215265A (en) * | 2014-08-18 | 2014-12-17 | 中国空间技术研究院 | PSD (position sensitive detector) signal noise reduction method with high precision |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101363900A (en) * | 2007-09-30 | 2009-02-11 | 北京华大泰思特半导体检测技术有限公司 | Method for testing FPGA device |
| CN102890234A (en) * | 2012-09-21 | 2013-01-23 | 中国空间技术研究院 | SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) application verification system and application verification method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7949978B2 (en) * | 2007-11-05 | 2011-05-24 | International Business Machines Corporation | Structure for system architectures for and methods of scheduling on-chip and across-chip noise events in an integrated circuit |
| US20120313655A1 (en) * | 2011-06-10 | 2012-12-13 | Associated Research, Inc. | Electrical test equipment having switchable intermediate-voltage line- leakage and run test power source |
-
2013
- 2013-03-12 CN CN201310078268.2A patent/CN103197159B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101363900A (en) * | 2007-09-30 | 2009-02-11 | 北京华大泰思特半导体检测技术有限公司 | Method for testing FPGA device |
| CN102890234A (en) * | 2012-09-21 | 2013-01-23 | 中国空间技术研究院 | SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) application verification system and application verification method |
Non-Patent Citations (4)
| Title |
|---|
| A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs;Luca Sterpone等;《IEEE TRANSACTIONS ON COMPUTERS》;20060630;第55卷(第6期);第732-744页 * |
| NOISE IMPACT OF SINGLE-EVENT UPSETS ON AN FPGA-BASED DIGITAL FILTER;Brian H.Pratt等;《2009 IEEE》;20091231;第38-43页 * |
| 卫星用半导体器件失效模式和机理分布;夏泓等;《中国空间科学技术》;19920831(第4期);第55-58页 * |
| 基于宏模型的同步开关噪声仿真分析;蒋历国等;《半导体技术》;20080131;第33卷(第1期);第39-41页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103197159A (en) | 2013-07-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102890234B (en) | A kind of SRAM type FPGA application verification system and application verification method | |
| CN104019020B (en) | Loop control system measured by a kind of main pump digitizing nuclear power station | |
| CN205229440U (en) | A detecting system for detecting partial discharge detector | |
| CN103513095A (en) | Data acquisition device applied to power distribution line fault indicator detection | |
| CN102147426A (en) | Broadband triggering circuit of digital oscilloscope | |
| CN103675652B (en) | A kind of ADC chip testing based on non-homogeneous clock and collecting method | |
| US9425794B1 (en) | Testing system for power delivery network | |
| CN104330621A (en) | Electric appliance energy consumption tester | |
| CN108535575A (en) | Power quality analysis device based on short-distance wireless communication technology | |
| CN103197159B (en) | A kind of SRAM type FPGA simultaneous switching noise verification method | |
| CN104536282A (en) | Time-digital converter and time measuring device and method | |
| CN202522693U (en) | Device for detecting measure accuracy degree of electric energy meter | |
| CN204272138U (en) | A kind of eye pattern testing apparatus of high speed signal | |
| CN201796119U (en) | Programmable digital integrated circuit alternating-current parameter testing system | |
| CN104391176A (en) | Software and hardware frequency measurement circuit compatible with electric power system signals | |
| CN102932077A (en) | Method for measuring frequency spectrum occupancy rate | |
| CN204085642U (en) | A kind of air flow sensor test board | |
| CN103218268B (en) | A kind of SRAM type FPGA crosstalk verification method | |
| CN202710695U (en) | Cable detector | |
| CN105242062A (en) | Fan rotating speed detection apparatus | |
| CN104375027A (en) | Method and device for testing low-power consumption electronic device and low-power consumption POS terminal | |
| CN103760417A (en) | Simple AC signal phase acquisition circuit with frequency measurement function | |
| CN203414549U (en) | Ultra-low power test power meter | |
| CN103197179A (en) | Power quality detecting terminal used for power grids | |
| CN204087194U (en) | A kind of AVR single chip emulator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |