CN103187351B - Fabrication method of integrated circuit - Google Patents
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- CN103187351B CN103187351B CN201110446090.3A CN201110446090A CN103187351B CN 103187351 B CN103187351 B CN 103187351B CN 201110446090 A CN201110446090 A CN 201110446090A CN 103187351 B CN103187351 B CN 103187351B
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Abstract
The invention provides a fabrication method of an integrated circuit. The integrated circuit comprises a bulk silicon CMOS (Complementary Metal Oxide Semiconductor) circuit and an SOI MOS (Silicon-on-insulator Metal Oxide Semiconductor) circuit. The method comprises the step of forming an SOI substrate in a partial area of a bulk silicon substrate, so that the same semiconductor substrate can comprise the bulk silicon substrate and the SOI substrate simultaneously, the bulk silicon CMOS circuit and the SOI MOS circuit can be fabricated simultaneously on the same semiconductor substrate, and the compatibility of fabrication processes of the bulk silicon CMOS circuit and the SOI MOS circuit can be realized. As the bulk silicon CMOS circuit and the SOI MOS circuit are formed on the same semiconductor substrate, and a fabrication process of a passive device in the integrated circuit can be compatible with the fabrication processes of the bulk silicon CMOS circuit and the SOI MOS circuit, the fabrication technology is simplified.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of manufacture method of integrated circuit.
Background technology
CMOS (Complementary Metal Oxide Semiconductor, CMOS (Complementary Metal Oxide Semiconductor)) circuit refers to a kind of semiconductor circuit including PMOS and NMOS, it can be used for forming microprocessor (microprocessor), single-chip microcomputer (microcontroller), static random access memory (SRAM) and other Digital Logical Circuits.Cmos circuit has many advantages, and one of them the most significant advantage is exactly that power consumption is very low, and therefore, cmos circuit is widely used.PMOS, NMOS in cmos circuit are generally formed on body silicon substrate, and this cmos circuit be formed on body silicon substrate is referred to as Bulk CMOS circuit.
With the continuous progress of integrated circuit fabrication process, the volume of semiconductor device is just becoming more and more less, and the thing followed is a large amount of problems that the characteristic size of semiconductor device produces when approaching physics limit.This makes industry start to find the solution except simple reduction of device size, to improve the performance of semiconductor device further.SOI (Silicon On Insulator, silicon-on-insulator) technology is extensively sent out research as a kind of important developing direction by industry and is used.Compared with conventional bulk silicon substrate, SOI substrate at the bottom of top layer silicon and backing between introduce one deck buried oxide layer, this buried oxide layer is generally silica.By introducing this insulator of buried oxide layer, SOI substrate is provided with the incomparable advantage of body silicon substrate: the medium isolation that can realize components and parts in integrated circuit, completely eliminates the parasitic latch-up in Bulk CMOS circuit; Adopt the integrated circuit that this material is made, i.e. SOI MOS circuit (including the semiconductor circuit of PMOS and NMOS), also have that parasitic capacitance is little, integration density is high, speed is fast, technique is simple, short-channel effect is little and be specially adapted to the advantage such as low pressure, low consumption circuit, therefore can say that SOI technology will likely become the low pressure of deep-submicron, the mainstream technology of low power consumption integrated circuit.But, while SOI substrate possesses these advantages, the problems such as heat radiation is bad, floater effect can be brought, so that affect performance and the reliability of SOIMOS circuit.
Therefore, the so a kind of integrated circuit of necessary formation, it had both comprised Bulk CMOS circuit, also comprised SOI MOS circuit, and like this, integrated circuit can possess the advantage of Bulk CMOS circuit, SOI MOS circuit simultaneously, to improve the performance of whole integrated circuit.But because the processing procedure of Bulk CMOS circuit and SOI MOS circuit cannot be compatible in prior art, Bulk CMOS circuit, SOI MOS circuit need respectively in different Semiconductor substrate, as silicon chip makes, make that the manufacturing process of said integrated circuit is too loaded down with trivial details, fabrication cycle and production cost increase greatly.
Summary of the invention
The problem to be solved in the present invention is: comprise simultaneously Bulk CMOS circuit, SOI MOS circuit the manufacturing process of integrated circuit too loaded down with trivial details, fabrication cycle is long, production cost is excessive.
For addressing this problem, first the present invention forms SOI substrate at the regional area of an individual silicon substrate, same like this Semiconductor substrate can comprise body silicon substrate, SOI substrate simultaneously, make in same Semiconductor substrate, make Bulk CMOS circuit simultaneously, SOI MOS circuit becomes possibility, realize the compatibility of Bulk CMOS circuit, SOI MOS circuit manufacture procedure.Because Bulk CMOS circuit, SOI MOS circuit are formed in same Semiconductor substrate, in integrated circuit, the processing procedure of passive device also can be compatible with the processing procedure of Bulk CMOS circuit, SOI MOS circuit, simplifies manufacturing process.
Given this, the invention provides a kind of manufacture method of integrated circuit, it comprises following making step:
There is provided Semiconductor substrate, described Semiconductor substrate comprises first area, second area, and described first area is for the formation of SOI MOS circuit, and described second area is for the formation of Bulk CMOS circuit;
In the first area of described Semiconductor substrate, form buried oxide layer, described buried oxide layer and described semiconductor substrate surface have spacing;
The first trap is formed at the second area of described Semiconductor substrate;
Simultaneously above the buried oxide layer of described first area, in the first trap of second area, form fleet plough groove isolation structure, to be completely cut off in SOI MOS circuit, Bulk CMOS circuit and adjacent active regions;
Simultaneously between the adjacent shallow trench isolation structure of described first area and second area, form the second trap, the degree of depth of described second trap is less than the degree of depth of described first trap;
Simultaneously on the second trap of described first area and second area, form grid;
Form source electrode or drain electrode in the both sides of described grid, to form transistor in described SOI MOS circuit, Bulk CMOS circuit simultaneously simultaneously.
Optionally, the formation method of described buried oxide layer comprises:
Form hard mask on the semiconductor substrate;
Described hard mask forms graphical photoresist layer, and described graphical photoresist layer is formed with opening in the position of the described Semiconductor substrate first area of correspondence;
O +ion implanted is carried out to Semiconductor substrate first area, in the first area of described Semiconductor substrate, forms buried oxide layer, between described buried oxide layer and described semiconductor substrate surface, there is spacing.
Optionally, after forming described buried oxide layer, annealing in process is carried out to described integrated circuit.
Optionally, the temperature of described annealing in process is 600 DEG C ~ 1000 DEG C.
Optionally, before forming described first trap, two depth groove isolation constructions are formed in described Semiconductor substrate first area, so that Bulk CMOS circuit and adjacent active regions are completely cut off, after forming described depth groove isolation construction, between described depth groove isolation construction, form the first trap, then form described fleet plough groove isolation structure between two depth groove isolation constructions, the degree of depth of described depth groove isolation construction is greater than the degree of depth of described fleet plough groove isolation structure.
Optionally, described Semiconductor substrate also comprises the 3rd region, and described 3rd region is formed with high resistant grid.
Optionally, the manufacture method of described high resistant grid is as follows:
Deposition of gate material layer on the semiconductor substrate;
Described gate material layers forms graphical photoresist layer, and the position of described graphical photoresist layer first area and second area described in corresponding part is formed with opening;
To the gate material layers implanting p-type alloy be positioned at below described opening or N-type dopant;
Remove described graphical photoresist layer, described gate material layers is formed with photoresist layer in the position in the described opening of correspondence and described 3rd region of part;
Remove not by the gate material layers that described photoresist layer covers, simultaneously to form grid on the second trap of Semiconductor substrate first area and second area, form high resistant grid on Semiconductor substrate the 3rd region.
Optionally, the resistance of described Semiconductor substrate is greater than 1000 Ω.
Optionally, after forming described grid, plated metal on the semiconductor substrate, to form metal silicide in described grid, high resistant grid, source electrode, drain surface simultaneously.
Optionally, the described Semiconductor substrate being formed with transistor forms metal interconnect structure, and it comprises:
Interlayer dielectric layer, forms the conductive plug be connected with described source electrode, drain electrode, high resistant grid respectively in described interlayer dielectric layer;
Form the first metallic film, the second metallic film, the 3rd metallic film on the semiconductor substrate successively, successively the 3rd metallic film, the second metallic film, the first metallic film are etched, to form the first layer metal interconnection structure in metal interconnect structure.
Compared with prior art, the present invention has the following advantages:
SOI substrate is formed by the regional area at body silicon substrate, same like this Semiconductor substrate can comprise body silicon substrate, SOI substrate simultaneously, make in same Semiconductor substrate, make Bulk CMOS circuit simultaneously, SOI MOS circuit becomes possibility, realize the compatibility of Bulk CMOS circuit, SOI MOS circuit manufacture procedure.Because Bulk CMOS circuit, SOI MOS circuit are formed in same Semiconductor substrate, in integrated circuit, the processing procedure of passive device also can be compatible with the processing procedure of Bulk CMOS circuit, SOI MOS circuit, simplifies manufacturing process.
Accompanying drawing explanation
Fig. 1 is the Making programme figure of integrated circuit in embodiments of the invention.
Fig. 2 to Figure 15 is the cutaway view of integrated circuit in the process making integrated circuit in embodiments of the invention.
Embodiment
Below in conjunction with accompanying drawing, by specific embodiment, carry out clear, complete description to technical scheme of the present invention, obviously, described embodiment is only a part for embodiment of the present invention, instead of they are whole.According to these embodiments, those of ordinary skill in the art's obtainable other execution modes all under without the need to the prerequisite of creative work, all belong to protection scope of the present invention.
Fig. 1 is the Making programme figure of integrated circuit in embodiments of the invention.As shown in Figure 1, the manufacture method of described integrated circuit comprises the following steps:
S1: Semiconductor substrate is provided.
S2: form buried oxide layer in the first area of Semiconductor substrate, buried oxide layer and semiconductor substrate surface have spacing.
S3: form the first trap at the second area of Semiconductor substrate.
S4: simultaneously form fleet plough groove isolation structure, to be completely cut off in SOI MOS circuit, Bulk CMOS circuit and adjacent active regions above the buried oxide layer of Semiconductor substrate first area, in the first trap of Semiconductor substrate second area.
S5: simultaneously form the second trap between the adjacent shallow trench isolation structure of Semiconductor substrate first area and second area, the degree of depth of the second trap is less than the degree of depth of the first trap.
S6: simultaneously form grid on the second trap of Semiconductor substrate first area and second area, form high resistant grid on Semiconductor substrate the 3rd region.
S7: form side wall at the sidewall of grid, high resistant grid, then form the source electrode of transistor, drain electrode in the grid both sides of Semiconductor substrate first area, second area.
S8: plated metal on a semiconductor substrate, to form metal silicide in grid, high resistant grid, source electrode, drain surface simultaneously.
S9: form metal interconnect structure in the Semiconductor substrate being formed with transistor.
Describe the manufacture method of integrated circuit below in detail.
First step S1 is performed: provide Semiconductor substrate.
As shown in Figure 2, Semiconductor substrate 10 is provided.Semiconductor substrate 10 can be the common Semiconductor substrate comprising silicon, as silicon chip etc.In the present embodiment, Semiconductor substrate 10 is silicon substrate.High resistivity semiconductor substrate can reduce capacitive coupling in integrated circuit, reduce the various radio frequency loss relevant to Semiconductor substrate further, and therefore, in the present embodiment, Semiconductor substrate 10 is High resistivity substrate, and its resistance is greater than 1000 Ω.
Semiconductor substrate 10 at least comprises first area I, second area II, wherein, first area I is for the formation of the SOI MOS circuit (including the semiconductor circuit of PMOS and NMOS) in integrated circuit, and second area II is for the formation of the Bulk CMOS circuit (including the semiconductor circuit of PMOS and NMOS) in integrated circuit.In the present embodiment, Semiconductor substrate 10 also comprises the 3rd region III, and the 3rd region III is for the formation of the passive device of integrated circuit.
Then step S2 is performed: in the first area of Semiconductor substrate, form buried oxide layer, buried oxide layer and semiconductor substrate surface have spacing.
As shown in Figure 3, the object forming buried oxide layer 11 in Semiconductor substrate 10 first area I is in order to the first area I in Semiconductor substrate 10 forms SOI substrate.In prior art, the manufacture craft of SOI substrate has multiple, comprises SMIOX (O +ion implanted method), BESOI (wafer bonding back side etch), Smart-cut (smart cut technique).
In the present embodiment, utilize O +ion implanted technology to form SOI substrate in the first area I of Semiconductor substrate 10, its concrete manufacturing process comprises: as shown in Figure 3, forms hard mask 12 over the semiconductor substrate 10, and the thickness of hard mask 12 can be
hard mask 12 can be the suitable hard mask material such as pad oxide, silicon nitride, and its formation method can be the thin film deposition processes that thermal oxide growth, chemical vapour deposition (CVD) (CVD), ald (ALD) etc. are suitable.Then on hard mask 12, graphical photoresist layer 13 is formed, graphical photoresist layer 13 is formed with opening 14 in the position of corresponding Semiconductor substrate 10 first area I, remove the hard mask 12 be positioned at below opening 14, namely remove the hard mask 12 on Semiconductor substrate 10 first area I, then remove graphical photoresist layer 13.
Carry out O +ion implanted to Semiconductor substrate 10 first area I (namely not by Semiconductor substrate 10 that hard mask 12 covers), the silicon in oxonium ion and Semiconductor substrate 10 first area I reacts and generates buried oxide layer SiO
2, buried oxide layer 11 and semiconductor substrate surface 10a have spacing.In the present embodiment, the spacing between buried oxide layer 11 and semiconductor substrate surface 10a is 0.5 μm ~ 2 μm.Buried oxide layer 11 forms SOI substrate with the Semiconductor substrate 10 of the side of being located thereon and below.
But O +ion implanted can cause sizable damage to Semiconductor substrate 10, and the uniformity of buried oxide layer 11 is also bad.Therefore, need subsequently to carry out annealing in process to Semiconductor substrate 10.Annealing in process can help reparation be positioned at the damaged layer of the Semiconductor substrate 10 above buried oxide layer 11 and the uniformity of buried oxide layer 11 is consistent, and makes it to possess good insulation property.Experiment proves, when carrying out repeatedly annealing in process to Semiconductor substrate 10, obviously can reduce the defect of the Semiconductor substrate 10 be arranged in above buried oxide layer 11.In the present embodiment, the temperature of annealing in process is 600 DEG C ~ 1000 DEG C.
So far, in the first area I of Semiconductor substrate 10, define SOI substrate, cover because the region beyond the I of Semiconductor substrate first area is patterned immediately photoresist layer 13, therefore, the region beyond the I of Semiconductor substrate first area is still body silicon substrate.
Then step S3 is performed: form the first trap at the second area of Semiconductor substrate.
As shown in Figure 4, remove hard mask 12, then form oxide layer 19 over the semiconductor substrate 10, oxide layer 19 is formed graphical photoresist layer 15, and graphical photoresist layer 15 is formed with opening 16 in the position of corresponding Semiconductor substrate 10 second area II.The Semiconductor substrate 10 be positioned at below opening 16 is carried out to the ion implantation of one or many (more than twice or twice) P type alloy or N-type dopant, to form the first trap 17 at the second area II of Semiconductor substrate 10.Carrying out in the process of ion implantation to Semiconductor substrate 10 second area II, ion can cause damage to Semiconductor substrate 10, therefore, after carrying out ion implantation, need carry out annealing in process to whole Semiconductor substrate 10.Annealing in process can be repaired in ion implantation process the damage that Semiconductor substrate 10 causes.In the present embodiment, the temperature of annealing can be 900 DEG C ~ 1200 DEG C.
Certainly, in this step, also other trap can be formed again to make Bulk CMOS circuit in Semiconductor substrate 10 second area II.
In another embodiment of the present invention, before Semiconductor substrate 10 second area II forms the first trap 17, as shown in Figure 5, Figure 8, two depth groove isolation constructions 18 can be formed, to be completely cut off the adjacent active regions in Bulk CMOS circuit and Semiconductor substrate 10 further in Semiconductor substrate 10 second area II.Then, the first trap 17 is formed between two depth groove isolation constructions 18 of Semiconductor substrate 10 second area II, then between two depth groove isolation constructions 18, fleet plough groove isolation structure 25 is formed, the degree of depth of depth groove isolation construction 18 is greater than the degree of depth of the first trap 17, and is greater than the degree of depth of fleet plough groove isolation structure 25.
Then step S4 is performed: simultaneously above the buried oxide layer of Semiconductor substrate first area, in the first trap of Semiconductor substrate second area, form fleet plough groove isolation structure, to be completely cut off in SOI MOS circuit, Bulk CMOS circuit and adjacent active regions.
As shown in Figure 6, graphical photoresist layer 15 is removed.The oxide layer 19 of Semiconductor substrate 10 forms hard mask 20, as silicon nitride.Then on hard mask 20, form graphical photoresist layer 21, graphical photoresist layer 21 is formed with opening 22 in the position of corresponding semiconductor substrate section first area I, second area II.The hard mask 20 be positioned at below opening 22, oxide layer 19, Semiconductor substrate 10 are etched, with simultaneously above the buried oxide layer 11 of Semiconductor substrate first area I, formation shallow trench 23 in first trap 17 of Semiconductor substrate second area II.
As shown in Figure 7, graphical photoresist layer 21 is removed.Deposited oxide layer 24 over the semiconductor substrate 10, to fill shallow trench 23.Carry out chemico-mechanical polishing (CMP) process to oxide skin(coating) 24, carrying out in the process of chemical mechanical polish process to oxide skin(coating) 24, hard mask 20 is used as polish stop.
As shown in Figure 8, remove hard mask 20, above the buried oxide layer 11 of Semiconductor substrate first area I, in first trap 17 of Semiconductor substrate second area II, form fleet plough groove isolation structure 25.The fleet plough groove isolation structure 25 formed is for completely cutting off the adjacent active regions in SOI MOS circuit, Bulk CMOS circuit and Semiconductor substrate 10 (adjacent active regions in Bulk CMOS circuit and Semiconductor substrate can completely cut off by depth groove isolation construction further).
Certainly, in this step, above the buried oxide layer 11 of Semiconductor substrate first area I, fleet plough groove isolation structure 25 quantity that formed in first trap 17 of Semiconductor substrate second area II is not limited to two, its quantity can be three or more, can form multiple second trap like this in subsequent step S5.When fleet plough groove isolation structure 25 quantity in Semiconductor substrate first area I, second area II is three or more, be positioned at the fleet plough groove isolation structure 25 at the most two ends of first area I, second area II for being completely cut off the adjacent active regions of SOI MOS circuit, Bulk CMOS circuit and Semiconductor substrate 10.
Then step S5 is performed: simultaneously between the adjacent shallow trench isolation structure of Semiconductor substrate first area and second area, form the second trap, the degree of depth of the second trap is less than the degree of depth of the first trap.
As shown in Figure 9, region between the adjacent shallow trench isolation structure 25 of Semiconductor substrate first area I and second area II is carried out to the ion implantation of P type alloy or N-type dopant, the degree of depth of the first trap 17 is less than with the degree of depth forming the second trap 26, second trap 26 between the adjacent shallow trench isolation structure 25 of Semiconductor substrate first area I and second area II simultaneously.
Then step S6 is performed: simultaneously on the second trap of Semiconductor substrate first area and second area, form grid, on Semiconductor substrate the 3rd region, form high resistant grid.
As shown in Figure 10, deposition of gate material layer 27 over the semiconductor substrate 10, its material is polysilicon.Gate material layers 27 is formed graphical photoresist layer 28, graphical photoresist layer 28 is formed with opening 29 in the position of corresponding part first area I and second area II, and opening 29 is for defining transistor gate regions in SOI MOS circuit, Bulk CMOS circuit.To the gate material layers 27 implanting p-type alloy be positioned at below opening 29 or N-type dopant.
As shown in figure 11, remove graphical photoresist layer 28, again form graphical photoresist layer 30 over the semiconductor substrate 10, gate material layers 27 is coated with photoresist layer in the position of corresponding opening 29 and part the 3rd region III.
As shown in figure 12, remove the gate material layers 27 not being patterned immediately photoresist layer 30 and covering, to form grid 31 on second trap 26 of Semiconductor substrate first area I and second area II, form high resistant grid 32 on Semiconductor substrate the 3rd region III simultaneously.Then graphical photoresist layer 30 is removed.
Because the high resistant grid 32 of the 3rd region III did not inject P type alloy or N-type dopant, therefore, its resistance value is very large, can be used as the passive device with higher quality factor in integrated circuit.In integrated circuit, the quality factor (quality factor) of passive device weighs a major criterion of integrated circuit quality, quality factor is used for the efficiency of outlines device or circuit stored energy, when the quality factor of device or circuit is higher, represent that the power of its loss is fewer.And high resistant grid 32 is synchronous in the manufacturing process of transistor gate formation, does not need to utilize extra manufacture craft, decreases production cost.
Then step S7 is performed: form side wall at the sidewall of grid, high resistant grid, then form the source electrode of transistor, drain electrode in the grid both sides of Semiconductor substrate first area, second area.
As shown in figure 13, form graphical photoresist layer 33 over the semiconductor substrate 10, Semiconductor substrate 10 do not need formed source electrode, drain electrode region on cover photoresist layer, then implanting p-type alloy or N-type dopant, can form source electrode, the drain electrode 34 of transistor simultaneously in grid 31 both sides of first area I and second area II.
So far, the transistor in the SOI MOS circuit of Semiconductor substrate 10 first area I is formed, and the transistor in the Bulk CMOS circuit of Semiconductor substrate 10 second area II is formed.
Because SOI MOS circuit, Bulk CMOS circuit make to be formed in same Semiconductor substrate, after forming transistor in integrated circuits, also can form other semiconductor element in the Bulk CMOS circuit of the SOI MOS circuit of Semiconductor substrate 10 first area I, second area II simultaneously, in the present embodiment, do not list one by one.
Then step S8 is performed: plated metal on a semiconductor substrate, to form metal silicide in grid, high resistant grid, source electrode, drain surface simultaneously.
As shown in figure 14, remove graphical photoresist layer 33, sputtering technology can be utilized to deposit layer of metal over the semiconductor substrate 10, as titanium, cobalt etc., under the high temperature conditions, the metal such as titanium, cobalt can react with the silicon in Semiconductor substrate 10 and form metal silicide 35.Chemically etch away the metal do not reacted, metal silicide 35 has stayed grid 31, high resistant grid 32, source electrode, drain electrode 34 surface.Metal silicide 35 has many effects, and one of its effect is that the silicon in Semiconductor substrate 10 can be combined more closely with the electric conducting material of deposit subsequently.
Then step S9 is performed: in the Semiconductor substrate being formed with transistor, form metal interconnect structure.
Form required semiconductor element (comprising active device, passive device) in Semiconductor substrate 10 after, metal interconnect structure need be formed in Semiconductor substrate 10, so that semiconductor element is connected into circuit.
As shown in figure 15, form interlayer dielectric layer 36 over the semiconductor substrate 10, as silica, chemico-mechanical polishing (CMP) process is carried out to interlayer dielectric layer 36.Then etch interlayer dielectric layer 36, to form through hole in interlayer dielectric layer 36, these through holes define metal interconnected Path form.At the bottom of through hole and deposited on sidewalls barrier metal layer, as titanium nitride, spread to prevent the metal in metal interconnect structure in conductive plug.Deposit interconnecting metal over the semiconductor substrate 10, as aluminium, tungsten etc., to make through hole be filled by interconnecting metal, then chemical mechanical polish process is carried out to interconnecting metal, barrier metal layer, form conductive plug 37.Conductive plug 37 is connected with high resistant grid 32, source electrode, drain electrode 34.
Form the first metallic film 38 over the semiconductor substrate 10, as titanium etc.Then on the first metallic film 38, the second metallic film 39, the 3rd metallic film 40 is deposited successively, second metallic film 39 can be albronze, 3rd metallic film 40 can be titanium nitride, 3rd metallic film 40, second metallic film 39, first metallic film 38 is etched, to form sandwich metal structure 41.
So far, the first layer metal interconnection in metal interconnect structure is formed.After first layer metal interconnection is formed, can in silicon oxide layer deposited 42 in the sandwich metal structure 41 above high resistant grid 32, then on silicon oxide layer 42, metal level 43 is formed, like this, the 3rd metallic film 40 in sandwich metal structure 41, silicon oxide layer 42, metal level 43 form metal capacitance (MIM) 44.Metal capacitance 44 is connected with high resistant grid 32, forms RC circuit.Also other passive device can be formed, as inductance etc., in this citing that differs on first layer metal interconnection structure.
Also can continue to form second layer metal interconnection structure, the 3rd layer metal interconnection structure etc. again on first layer metal interconnection structure, until whole metal interconnect structure is formed.
After metal interconnect structure in Semiconductor substrate 10 is formed, semiconductor packaging can be utilized to be packaged together multiple Semiconductor substrate to be formed a complete integrated circuit.In the present embodiment, silicon through hole (through silicon via, TSV) technology can be utilized multiple Semiconductor substrate to be packaged together.TSV technology has lot of advantages, as having shorter interconnection path, lower resistance and inductance than routing bond package technology, effectively can improving the degree of integration and usefulness etc. of system with lower cost.
TSV technology can be divided into first through hole (via first), rear through hole (via last) two kinds of technology, its general principle forms aperture with etching or radium-shine mode on wafer or chip, wafer or chip can be passed through, aperture is filled again with materials such as copper, polysilicon, tungsten, thus form the rule passage connected, finally by wafer or chip wear down, by multiple wafer or chip in addition stacking, combine (bonding), thus complete encapsulation.
It should be noted that, in the present invention, the structure of integrated circuit is not restricted to the embodiment that the present invention provides, and other common semiconductor element that can simultaneously be formed in SOI MOS circuit, Bulk CMOS circuit is also within protection scope of the present invention.
In sum, the present invention has the following advantages:
SOI substrate is formed by the regional area at body silicon substrate, same like this Semiconductor substrate can comprise body silicon substrate, SOI substrate simultaneously, make in same Semiconductor substrate, make Bulk CMOS circuit simultaneously, SOI MOS circuit becomes possibility, realize the compatibility of Bulk CMOS circuit, SOI MOS circuit manufacture procedure.Because Bulk CMOS circuit, SOI MOS circuit are formed in same Semiconductor substrate, in integrated circuit, the processing procedure of passive device also can be compatible with the processing procedure of Bulk CMOS circuit, SOI MOS circuit, simplifies manufacturing process.
Above by the explanation of embodiment, professional and technical personnel in the field should be able to be made to understand the present invention better, and can reproduce and use the present invention.Those skilled in the art can be apparent to above-described embodiment do various changes and modifications when not departing from the spirit and scope of the invention according to principle described herein.Therefore, the present invention should not be understood to be limited to above-described embodiment shown in this article, and its protection range should be defined by appending claims.
Below in conjunction with accompanying drawing, by specific embodiment, carry out clear, complete description to technical scheme of the present invention, obviously, described embodiment is only a part for embodiment of the present invention, instead of they are whole.According to these embodiments, those of ordinary skill in the art's obtainable other execution modes all under without the need to the prerequisite of creative work, all belong to protection scope of the present invention.
Claims (9)
1. a manufacture method for integrated circuit, is characterized in that, comprises following making step:
There is provided Semiconductor substrate, described Semiconductor substrate comprises first area, second area, and described first area is for the formation of SOI MOS circuit, and described second area is for the formation of Bulk CMOS circuit;
In the first area of described Semiconductor substrate, form buried oxide layer, described buried oxide layer and described semiconductor substrate surface have spacing;
Two depth groove isolation constructions are formed, Bulk CMOS circuit and adjacent active regions to be completely cut off in described Semiconductor substrate second area;
Between described depth groove isolation construction, form the first trap, the degree of depth of described first trap is less than the degree of depth of depth groove isolation construction;
Simultaneously above the buried oxide layer of described first area, in the first trap of second area, form fleet plough groove isolation structure, to be completely cut off in SOI MOS circuit, Bulk CMOS circuit and adjacent active regions, the degree of depth of described depth groove isolation construction is greater than the degree of depth of described fleet plough groove isolation structure;
Simultaneously between the adjacent shallow trench isolation structure of described first area and second area, form the second trap, the degree of depth of described second trap is less than the degree of depth of described first trap;
Simultaneously on the second trap of described first area and second area, form grid;
Form source electrode or drain electrode in the both sides of described grid, to form transistor in described SOI MOS circuit, Bulk CMOS circuit simultaneously simultaneously.
2. the manufacture method of integrated circuit according to claim 1, is characterized in that, the formation method of described buried oxide layer comprises:
Form hard mask on the semiconductor substrate;
Described hard mask forms graphical photoresist layer, and described graphical photoresist layer is formed with opening in the position of the described Semiconductor substrate first area of correspondence;
Remove the hard mask be positioned at below described opening, then described graphical photoresist layer is removed, O +ion implanted is carried out to Semiconductor substrate first area, in the first area of described Semiconductor substrate, form buried oxide layer, between described buried oxide layer and described semiconductor substrate surface, there is spacing.
3. the manufacture method of integrated circuit according to claim 2, is characterized in that, after forming described buried oxide layer, carries out annealing in process to described integrated circuit.
4. the manufacture method of integrated circuit according to claim 3, is characterized in that, the temperature of described annealing in process is 600 DEG C ~ 1000 DEG C.
5. the manufacture method of integrated circuit according to claim 1, is characterized in that, described Semiconductor substrate also comprises the 3rd region, and described 3rd region is formed with high resistant grid.
6. the manufacture method of integrated circuit according to claim 5, is characterized in that, the manufacture method of described high resistant grid is as follows:
Deposition of gate material layer on the semiconductor substrate;
Described gate material layers forms graphical photoresist layer, and the position of described graphical photoresist layer first area and second area described in corresponding part is formed with opening;
To the gate material layers implanting p-type alloy be positioned at below described opening or N-type dopant;
Remove described graphical photoresist layer, described gate material layers is formed with photoresist layer in the position in the described opening of correspondence and described 3rd region of part;
Remove not by the gate material layers that described photoresist layer covers, simultaneously to form grid on the second trap of Semiconductor substrate first area and second area, form high resistant grid on Semiconductor substrate the 3rd region.
7. the manufacture method of integrated circuit according to claim 1, is characterized in that, the resistance of described Semiconductor substrate is greater than 1000 Ω.
8. the manufacture method of integrated circuit according to claim 5, is characterized in that, after forming described grid, plated metal on the semiconductor substrate, to form metal silicide in described grid, high resistant grid, source electrode, drain surface simultaneously.
9. the manufacture method of integrated circuit according to claim 5, is characterized in that, the described Semiconductor substrate being formed with transistor forms metal interconnect structure, and it comprises:
Interlayer dielectric layer, forms the conductive plug be connected with described source electrode, drain electrode, high resistant grid respectively in described interlayer dielectric layer;
Form the first metallic film, the second metallic film, the 3rd metallic film on the semiconductor substrate successively, successively the 3rd metallic film, the second metallic film, the first metallic film are etched, to form the first layer metal interconnection structure in metal interconnect structure.
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| US5740099A (en) * | 1995-02-07 | 1998-04-14 | Nec Corporation | Semiconductor memory device having peripheral circuit and interface circuit fabricated on bulk region out of silicon-on-insulator region for memory cells |
| CN101416300A (en) * | 2006-03-31 | 2009-04-22 | 先进微装置公司 | Semiconductor device comprising soi transistors and bulk transistors and a method of forming the same |
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| US5740099A (en) * | 1995-02-07 | 1998-04-14 | Nec Corporation | Semiconductor memory device having peripheral circuit and interface circuit fabricated on bulk region out of silicon-on-insulator region for memory cells |
| CN101416300A (en) * | 2006-03-31 | 2009-04-22 | 先进微装置公司 | Semiconductor device comprising soi transistors and bulk transistors and a method of forming the same |
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