CN103187254B - 一种双多晶硅栅的制造方法 - Google Patents
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
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Abstract
本发明公开了一种双层多晶硅栅的制造方法。所述制造方法包括:在所述待处理集成电路的氧化硅上淀积氮化硅;各向异性刻蚀所述氮化硅,在所述待处理集成电路的第一层多晶硅栅侧壁形成氮化硅侧墙;制作第二层多晶硅栅;以及漂洗所述氮化硅侧墙。
Description
技术领域
本发明涉及半导体集成电路制造技术领域,尤其涉及一种双多晶硅栅的制造方法。
背景技术
专业术语说明:
N阱:在衬底上扩散N型区;P阱:在衬底上扩散P型区;N+:N型重掺杂区;P+:P型重掺杂区;Fox:场氧化层;Pbody:P型掺杂体区。
MOS管是构成半导体集成电路的基本单元,MOS管由阱、源、漏和栅组成,多晶硅在半导体集成电路中常作为MOS管的栅极,即多晶硅栅。
在某些类型的集成电路中,比如某些BCD集成电路(双极-互补型MOS-功率双扩散MOS集成电路),包含有两层多晶硅并且都作为MOS管的栅极,分别称之为第一层多晶硅栅和第二层多晶硅栅。
以下以BCD集成电路为例,介绍双多晶硅栅的结构,如图1所示。
在图1中,列举了BCD集成电路中的一个低压NMOS和一个功率LDNMOS共两个MOS管,第一层多晶硅栅(图1中的多晶一)为功率LDNMOS的栅,第二层多晶硅栅(图1中的多晶二)为低压NMOS的栅,其中的厚氧化层为Fox,Fox覆盖的区域为场区,没有Fox覆盖的区域为有源区,有源区表面的薄氧化层为栅氧,多晶一下方和多晶二下方的栅氧分别称之为第一层栅氧和第二层栅氧,N+为MOS管的源、漏,Pbody为功率LDNMOS的体区。
在现有技术中,制造双多晶硅栅的方法如图2所示:
步骤201:在衬底上制作N阱和P阱(请参考图3);
步骤202:制作有源区和场区(请参考图4,在图4中被Fox覆盖的区域即场区,没被Fox覆盖的即为有源区);
步骤203:在有源区上生长第一层栅氧(请参考图5);
步骤204:淀积第一层多晶硅,并对第一层多晶硅进行光刻和刻蚀形成第一层多晶硅栅(请参考图6,即图6中的多晶一);
步骤205:进行Pbody掺杂(请参考图7);
步骤206:低压化学气相淀积氧化硅(LPTEOS)(请参考图8);
步骤207:Pbody高温推结(请参考图9);
步骤208:氧化硅湿法刻蚀(请参考图10);
步骤209:生长第二层栅氧(请参考图11);
步骤210:淀积第二层多晶硅(请参考图12);
步骤211:对第二层多晶硅进行光刻和刻蚀形成第二层多晶硅栅(请参考图13,即图13中的多晶二)。
以上步骤完成后,已经完成双多晶硅栅的制作,其他步骤都为本领域技术人员习知的标准工艺,比如制作N+和P+重掺杂区(请参考图14)。
本发明人在实现本发明的过程中发现,在上述制作方法中至少存在以下两个很难克服的缺点:第一是在步骤208中,当进行氧化硅湿法刻蚀时,是使用稀释的氢氟酸把裸露的LPTEOS和第一层栅氧腐蚀掉,多晶一下方的栅氧化层由于有多晶硅的遮蔽,不会被腐蚀掉,但是多晶一边缘的第一层栅氧很容易被腐蚀液损伤到,导致器件的可靠性下降;第二是在步骤211中,预留第二层多晶硅栅的区域被光刻胶覆盖,其他区域的光刻胶不被保留,然后采用干法刻蚀工艺把没有光刻胶覆盖的区域的多晶二刻蚀掉,然后去除光刻胶,这种刻蚀方法使得在多晶一的侧壁区域,多晶二的厚度(特指纵向厚度,请参见图12中的d1,下文同)比平坦区的多晶二的厚度d2大得多,所以刻蚀的工艺难度很大。
发明内容
本发明提供一种双多晶硅栅的制造方法,用以解决现有技术中存在的第一层多晶硅栅的边缘的第一层栅氧很容易被腐蚀液损伤到,导致器件的可靠性下降以及刻蚀第二层多晶硅的工艺难度大的问题。
本发明提供一种双多晶硅栅的制造方法,应用于一待处理集成电路,所述制造方法包括:在所述待处理集成电路的氧化硅上淀积氮化硅;对所述待处理集成电路的掺杂区进行热处理;各向异性刻蚀所述氮化硅,在所述待处理集成电路的第一多晶硅栅侧壁形成氮化硅侧墙;制作第二多晶硅栅;以及漂洗所述氮化硅侧墙;所述第一多晶硅栅和所述第二多晶硅栅在沿衬底方向上不重叠。
优选地,所述各向异性刻蚀所述氮化硅具体为使用等离子体干法垂直向下刻蚀。
优选地,所述氮化硅的厚度为1000~3000埃。
优选地,所述制作第二多晶硅栅具体包括:在所述待处理集成电路的有源区的表面和所述第一多晶硅栅上生长第二层栅氧;在所述第二层栅氧上淀积第二层多晶硅;以及刻蚀所述第二层多晶硅形成所述第二多晶硅栅。
优选地,所述热处理为高温推结,所述高温推结的温度为1050~1150摄氏度。
本发明有益效果如下:
本发明一实施例中采用了在氧化硅上淀积氮化硅,各向异性刻蚀氮化硅后在第一层多晶硅栅侧壁形成氮化硅侧墙,所以在进行氧化硅刻蚀时第一层多晶硅栅下方的第一层栅氧不会被损伤到,器件的可靠性提高,另外,由于氮化硅侧墙可以减缓第一层多晶硅栅产生的台阶,从而降低了第二层多晶硅刻蚀的工艺难度。
附图说明
图1为理想状态的双多晶硅栅的结构图;
图2为现有技术中制造双多晶硅栅的方法流程图;
图3-图14分别为图2中的制造方法中各步骤完成之后的结构图;
图15为本发明一实施例中双多晶硅栅的制造方法流程图;
图16-图24分别为图15中的制造方法中各步骤完成之后的结构图。
具体实施方式
本发明一实施例中提供一种双多晶硅栅的制造方法,用于处理一待处理集成电路,在本实施例中,以BCD集成电路为例。该待处理集成电路包括:衬底;N阱和P阱,形成于衬底上(请参考图3);场氧化层,设置于N阱和P阱上,形成有源区和场区,其中场氧化层覆盖的区域为场区,没有被场氧化层覆盖的区域为有源区(请参考图4);第一层栅氧,形成于有源区上(请参考图5);第一层多晶硅栅,形成于第一层栅氧上(请参见图6);掺杂区,形成于N阱上,其中在本实施例中掺杂区以Pbody为例,但是在实际运用中,可以按照器件结构和参数要求进行掺杂(请参考图7);氧化硅,覆盖于场氧化层、第一层栅氧和第一层多晶硅栅,其中该氧化硅为低压化学气相淀积氧化硅,即LPTEOS(请参考图8),LPTEOS的厚度一般为200~600埃,其作用是防止硅表面和第一层多晶硅栅的表面在后续的热处理过程中被氮化。请参考图15,图15为该制造方法的流程图,如图15所示,该方法包括:
步骤1501:在待处理集成电路的氧化硅上淀积氮化硅;
步骤1502:各向异性刻蚀氮化硅,在第一层多晶硅栅侧壁形成氮化硅侧墙;
步骤1503:制作第二层多晶硅栅;
步骤1504:漂洗氮化硅侧墙。
其中,步骤1501完成之后的结构图请参见图16,LPSIN代表低压化学气相淀积氮化硅,LPSIN的厚度为1000~3000埃,LPSIN可以防止硅表面和多晶一(即第一层多硅晶栅,下文同)的表面在后续的热处理过程中被氮化。
在步骤1501之后和步骤1502之前,还将掺杂区进行热处理,如图17所示,在本实施例中掺杂区以Pbody为例,而热处理以对Pbody高温推结为例,但是在实际运用中,可以按照器件结构和参数要求进行掺杂,并按照器件结构和参数要求进行热处理,本发明不作限制。高温推结在高温设备中进行,温度一般为1050~1150摄氏度。
在步骤1502中,各向异性刻蚀氮化硅,直至有源区的表面和场氧化层的表面上的氮化硅被刻蚀完,请参见图18,在本实施例中,使用等离子体干法刻蚀设备,垂直向下刻蚀LPSIN,当有源区表面和场氧化层表面的LPSIN被刻蚀完,即停止刻蚀,由于在多晶一的侧壁区域,LPSIN的厚度(特指纵向厚度,如图17中的d1,下文同)比平坦区的LPSIN厚度(图17中的d2)大得多,因此当完成刻蚀之后,多晶一侧壁区域的LPSIN被自动保留了下来,称之为氮化硅侧墙。
进一步,刻蚀氧化硅和第一层栅氧,请参考图19,在本实施例中,使用稀释的氢氟酸把图18中裸露的LPTEOS和第一层栅氧腐蚀掉,由于有氮化硅侧墙的掩蔽,多晶一的边缘的第一层栅氧不会被腐蚀液损伤到,因此器件的可靠性高。
步骤1503中,制作第二层多晶硅栅的具体过程为:在有源区的表面和第一层多晶硅栅上生长第二层栅氧,请参考图20,如图20所示,在本实施例中,在有源区的表面和多晶一的表面,生成了第二层栅氧;在第二层栅氧上和场氧化层上淀积第二层多晶硅,请参考图21,如图21所示,在本实施例中,在第二层栅氧和场氧化层上淀积第二层多晶硅;刻蚀第二层多晶硅形成第二层多晶硅栅,第二层多晶硅栅位于第二层栅氧的上方,请参考图22,在本实施例中,预留第二层多晶硅栅的区域被光刻胶覆盖,其他区域的光刻胶不被保留,然后采用干法刻蚀工艺把没有光刻胶覆盖的区域的第二层多晶硅刻蚀掉,然后去除光刻胶。如图22所示,第二层多晶硅栅(即图22中的多晶二)位于第二层栅氧的上方。而且由于有氮化硅侧墙的过渡作用,即减缓多晶一产生的陡直台阶,在多晶一侧壁区域的第二层多晶硅厚度(参见图21中的d3)与平坦区的第二层多晶硅的厚度(参见图21中的d4)之比不再像传统制造方法中那么大,刻蚀工艺的难度大大降低。
步骤1504中漂洗氮化硅侧墙具体请参见图23,使用热磷酸把氮化硅侧墙清洗掉。
以上步骤完成后,已经完成双多晶硅栅的制作,其他步骤都为本领域技术人员习知的标准工艺,比如制作N+和P+重掺杂区(请参考图24)。
本发明一实施例中采用了在氧化硅上淀积氮化硅,各向异性刻蚀氮化硅后在第一层多晶硅栅侧壁形成氮化硅侧墙,所以在进行氧化硅刻蚀时第一层多晶硅栅下方的第一层栅氧不会被损伤到,器件的可靠性提高,另外,由于氮化硅侧墙可以减缓第一层多晶硅栅产生的台阶,从而降低了第二层多晶硅刻蚀的工艺难度。
显然,本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样,倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内,则本发明也意图包含这些改动和变型在内。
Claims (5)
1.一种双多晶硅栅的制造方法,应用于一待处理集成电路,其特征在于,所述制造方法包括:
在所述待处理集成电路的氧化硅上淀积氮化硅;
对所述待处理集成电路的掺杂区进行热处理;
各向异性刻蚀所述氮化硅,在所述待处理集成电路的第一多晶硅栅侧壁形成氮化硅侧墙;
制作第二多晶硅栅;以及
漂洗所述氮化硅侧墙;所述第一多晶硅栅和所述第二多晶硅栅在沿衬底方向上不重叠。
2.如权利要求1所述的制造方法,其特征在于,所述各向异性刻蚀所述氮化硅具体为使用等离子体干法垂直向下刻蚀。
3.如权利要求1所述的制造方法,其特征在于,所述氮化硅的厚度为1000~3000埃。
4.如权利要求1所述的制造方法,其特征在于,所述制作第二多晶硅栅具体包括:
在所述待处理集成电路的有源区的表面和所述第一多晶硅栅上生长第二层栅氧;
在所述第二层栅氧上淀积第二层多晶硅;以及
刻蚀所述第二层多晶硅形成所述第二多晶硅栅。
5.如权利要求1所述的制造方法,其特征在于,所述热处理为高温推结,所述高温推结的温度为1050~1150摄氏度。
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