CN103178779B - A kind of signal generator with Amplitude Compensation function and method thereof - Google Patents
A kind of signal generator with Amplitude Compensation function and method thereof Download PDFInfo
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Abstract
The invention provides a kind of signal generator with Amplitude Compensation function and method thereof, wherein FPGA module includes: clock module, frequency sweep time totalizer, frequency sweep profile memory, skew multiplier, frequency word adder, frequency accumulator, carrier wave memorizer, amplitude-frequency compensating unit and compensation multiplier；The frequency sweep time accumulated value generated by frequency sweep time totalizer, a road produces outgoing carrier through frequency sweep profile memory, skew multiplier, frequency word adder, frequency accumulator, carrier wave memorizer；Another route amplitude-frequency compensating unit produces output and compensates, and is multiplied the swept-frequency signal after being compensated by compensating multiplier.Amplitude flatness problem during frequency sweep is solved by this signal generator and method thereof.
Description
Technical field
The present invention relates to test field of measuring technique, a kind of signal generator with Amplitude Compensation function and method thereof.
Background technology
Signal generator is as a kind of signal source, because it can produce different frequency, difform waveform, electronic system measurement, verify and safeguard in be widely used.Signal generator not only output waveform, the test for the ease of user is measured, and the most also exports synchronizing signal.In fields such as electronics, communication, computers, synchronizing signal has various definition.In the present invention, synchronizing signal refers in particular to be synchronized with a pulse signal of signal generator output waveform.
Along with the development of programmable logic technology, a lot of manufacturers all use DDS technology and FPGA technology to realize signal generator.Direct digital synthesizers (DirectDigitalSynthesis, hereinafter referred to as DDS) it is a kind of major technique in current frequency synthesis, there is low cost, high-resolution, fast conversion times, the feature such as output waveform Phase Continuation when can produce random waveform and switching, be widely adopted in signal generator designs.
Fig. 1 is typically to use the signal generator of DDS technology to realize the structured flowchart of frequency sweep function.Wherein, each sweep parameters of user setup is allocated to the depositor within FPGA by digital signal processor (DSP), thus controls the mode of operation of DDS.FPGA realizes the function of DDS, and its internal structure is as shown in Figure 2.Using two accumulators cumulative frequency base unit weight and frequency increment respectively, sum of the two is as the reading address of wave memorizer.What wave memorizer stored is the waveform sampling point of carrier wave, according to reading address output waveform sampling point.The digital quantity that wave memorizer exports is converted to staircase waveform by digital to analog converter.The effect of wave filter is the clutter in suppression staircase waveform, the waveform of output relative smooth.Analog channel is that the amplitude to output signal further processes, such as amplitude accurate adjustment, amplify, decay, skew etc..
In order to accurately measure the amplitude-frequency characteristic of tested network, as the swept-frequency signal of test source in frequency change procedure, its amplitude should be invariable.But, the amplitude flatness such as the swept-frequency signal of the existing signal generator of Fig. 1 structure is poor.This is uneven mainly due to the amplitude-versus-frequency curve of the signaling system being made up of DAC, wave filter, analog channel in this structure, even if therefore within bandwidth range, the amplitude of the waveform of the different frequency of the output of above-mentioned DDS signal generator is also inconsistent.Trace it to its cause and can be analyzed from these three part respectively.
(1) DAC: what DAC realized at present is not the sampling of preferable unit impact, its transmission function has the envelope trait of SINC function, or other nonlinear envelope shape mostly.
(2) wave filter: often select the wave filter that transient characteristic is precipitous to filter the harmonic wave of sinusoidal signal in DDS signal generator；But owing to the element quality factor of composition wave filter are big not, the frequency response curve in the range of cut-off frequency has recessed or becomes round cunning, or has ripple shape；
(3) analog channel: the amplifying circuit in analog channel is mainly made up of operational amplifier, according to the frequency response characteristic of operational amplifier, operational amplifier has decay to the amplitude of high-frequency signal.
Above-mentioned factor largely have impact on the amplitude flatness of output signal.In order to solve this problem, DDS signal generator has a process calibrated before dispatching from the factory: utilize the instrument such as circuit tester, energy meter to obtain amplitude-versus-frequency curve；Inverse according to amplitude-versus-frequency curve is by computed in software amplitude accurate adjustment coefficient.But the method for this software correction can only realize correcting on a frequency, and during frequency sweep, the frequency of output signal is in change, therefore cannot realize Amplitude Compensation during frequency sweep.
Summary of the invention
Present invention is primarily targeted at solution problems of the prior art, it is provided that a kind of signal generator with Amplitude Compensation function and method thereof, in order to solve amplitude flatness problem during frequency sweep.
It is an object of the invention to be achieved by following technical proposals:
A kind of signal generator with Amplitude Compensation function, including: FPGA module, DAC module, low pass filter and analog channel；Described FPGA module is used for generating swept-frequency signal；This swept-frequency signal passes sequentially through DAC module, low pass filter and analog channel and processes, and forms the swept-frequency signal of final output；It is characterized in that: described FPGA module includes: clock module, frequency sweep time totalizer, frequency sweep profile memory, skew multiplier, frequency word adder, frequency accumulator, carrier wave memorizer, amplitude-frequency compensating unit and compensation multiplier；
Described clock module, for providing master clock for other modules of FPGA module inside；
Described frequency sweep time totalizer, is used for control word Accumulating generation frequency sweep time, accumulated value frequency sweep time, and this frequency sweep time accumulated value is respectively sent to frequency sweep profile memory and amplitude-frequency compensating unit；
Described frequency sweep profile memory, for based on the frequency sweep curve pre-set, according to the frequency sweep curve sampling point that the output of described frequency sweep time accumulated value is corresponding；
Described skew multiplier, for being multiplied with frequency sweep deviation ratio by described frequency sweep curve sampling point, obtains the increment of swept frequency word；
Described frequency word adder, for being added with basic swept frequency word by the increment of described swept frequency word, obtains carrier wave swept frequency word；
Described frequency accumulator, for adding up described carrier wave swept frequency word, obtains carrier wave memorizer and reads address；
Described carrier wave memorizer, reads the corresponding sampling point of deposited carrier wave sampling point collection for reading address according to described carrier wave memorizer, and exports this outgoing carrier；
Described amplitude-frequency compensating unit, for reading the corresponding sampling point of deposited amplitude-frequency compensating curve according to described frequency sweep time accumulated value, and exports this output compensation；
Described compensation multiplier, receives outgoing carrier and output compensates, and for being multiplied with output compensation by outgoing carrier, obtains the swept-frequency signal after Amplitude Compensation.
Described amplitude-frequency compensating unit is provided with compensation postpone and amplitude-frequency compensation memory；
Described compensation postpones, receiving frequency-sweeping time accumulated value, for described frequency sweep time accumulated value is carried out delay disposal, obtains amplitude-frequency compensation memory and reads address；
Described amplitude-frequency compensation memory, reads the corresponding sampling point of deposited amplitude-frequency compensating curve for reading address according to described amplitude-frequency compensation memory, and exports this output compensation.
Described amplitude-frequency compensating unit is provided with compensation postpone and amplitude-frequency compensation memory；
Described amplitude-frequency compensation memory, for according to described frequency sweep time accumulated value read deposited amplitude-frequency compensating curve corresponding sampling point, and export this do not postpone output compensation；
Described compensation postpones, and receives this and does not postpones output and compensate, for not postponing to export compensation carry out delay disposal to described, and output after being postponed compensation.
The inverse of the amplitude-versus-frequency curve of the signaling system that described amplitude-frequency compensating curve is constituted by described DAC module, low pass filter, analog channel.
A kind of signal generating method with Amplitude Compensation function, FPGA module the swept-frequency signal generated, carry out digital-to-analogue conversion through DAC module, low pass filter carries out low-pass filtering and analog channel carries out amplitude process, forms the swept-frequency signal of final output；It is characterized in that: described FPGA module generates the process of swept-frequency signal, including:
With control word Accumulating generation frequency sweep time, accumulated value frequency sweep time, and this frequency sweep time accumulated value is respectively sent to frequency sweep profile memory and amplitude-frequency compensating unit；
Transmission processes to the frequency sweep time accumulated value of frequency sweep profile memory through following:
Based on the frequency sweep curve pre-set, according to the frequency sweep curve sampling point that the output of described frequency sweep time accumulated value is corresponding；
Described frequency sweep curve sampling point is multiplied with frequency sweep deviation ratio, obtains the increment of swept frequency word；
The increment of described swept frequency word is added with basic swept frequency word, obtains carrier wave swept frequency word；
Described carrier wave swept frequency word is added up, obtains carrier wave memorizer and read address；
Read address according to described carrier wave memorizer and read the corresponding sampling point of deposited carrier wave sampling point collection, and export this outgoing carrier；
Transmission processes to the frequency sweep time accumulated value of amplitude-frequency compensating unit through following:
Read the corresponding sampling point of deposited amplitude-frequency compensating curve according to described frequency sweep time accumulated value, and export this output compensation；
Outgoing carrier is multiplied with output compensation, obtains the swept-frequency signal after Amplitude Compensation.
Described transmission comprises the steps: to the processing procedure of the frequency sweep time accumulated value of amplitude-frequency compensating unit
Described frequency sweep time accumulated value is carried out delay disposal, obtains amplitude-frequency compensation memory and read address；
Read address according to described amplitude-frequency compensation memory and read the corresponding sampling point of deposited amplitude-frequency compensating curve, and export this output compensation.
Described transmission comprises the steps: to the processing procedure of the frequency sweep time accumulated value of amplitude-frequency compensating unit
According to described frequency sweep time accumulated value read deposited amplitude-frequency compensating curve corresponding sampling point, and export this do not postpone output compensation；
Do not postpone to export compensation carry out delay disposal to described, output after being postponed compensation.
The inverse of the amplitude-versus-frequency curve of the signaling system that described amplitude-frequency compensating curve is constituted by described DAC module, low pass filter, analog channel.
Pass through the embodiment of the present invention, before FPGA module output swept-frequency signal, change according to its frequency, first it is multiplied by this amplitude-frequency compensating curve, then through follow-up DAC, low pass filter, analog channel signaling system after, this swept-frequency signal remains permanent envelope, solves amplitude flatness problem during frequency sweep.
It addition, when the initial frequency of this signal generator frequency sweep, termination frequency shift, the fundamental quantity of frequency sweep deviation ratio and frequency word only need to be configured, it is not necessary to amendment frequency sweep profile memory, substantially increase system effectiveness.
Accompanying drawing explanation
Accompanying drawing described herein is used for providing a further understanding of the present invention, constitutes the part of the application, is not intended that limitation of the invention.In the accompanying drawings:
Fig. 1 is typically to use the signal generator of DDS technology to realize the structured flowchart of frequency sweep function；
Fig. 2 is FPGA module internal structure schematic diagram in existing signal generator；
Fig. 3 is embodiment of the present invention FPGA module inner function module structured flowchart；
Fig. 4 is that amplitude-frequency compensating curve calibrates flow chart；
Fig. 5 is the signal generating method flow chart with Amplitude Compensation function.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with embodiment and accompanying drawing, the present invention is described in further details.Here, the exemplary embodiment of the present invention and explanation thereof are used for explaining the present invention, but not as a limitation of the invention.
The signal generator with Amplitude Compensation function designed by the present invention is identical with the existing signal generator structure shown in Fig. 1 on hardware configuration, including: FPGA module, DAC module, low pass filter and analog channel.Described FPGA module is used for generating swept-frequency signal.This swept-frequency signal passes sequentially through DAC module, low pass filter and analog channel and processes, and forms the swept-frequency signal of final output.
Wherein, key design of the present invention is the functional module structure within FPGA, with the final amplitude flatness improving output swept-frequency signal.Fig. 3 is FPGA module inner function module structured flowchart.As shown in the figure, this FPGA module, including: clock module 400, frequency sweep time totalizer 401, frequency sweep profile memory 402, skew multiplier 403, frequency word adder 404, frequency accumulator 405, carrier wave memorizer 406, amplitude-frequency compensating unit and compensation multiplier 409.
Described clock module 400, for providing master clock 420 for other modules of FPGA module inside.
Described frequency sweep time totalizer 401, is used for frequency sweep time control word 431 Accumulating generation frequency sweep time accumulated value 421, and this frequency sweep time accumulated value 421 is respectively sent to frequency sweep profile memory 402 and amplitude-frequency compensating unit.The bit wide assuming frequency sweep time totalizer is N position, then
Frequency sweep cycle=master clock 420 cycle × 2N/ frequency sweep time control word 431 (formula 1)
Described frequency sweep profile memory 402, for based on the frequency sweep curve 432 pre-set, exporting the frequency sweep curve sampling point 422 of correspondence according to described frequency sweep time accumulated value 421.This frequency sweep curve 432 is before swept-frequency signal starts output, processor frequency sweep curve 432 corresponding for sweep method is write this frequency sweep profile memory 402.So, as long as not changing sweep method, processor is no need for reconfiguring frequency sweep profile memory.
Under normal circumstances, the latter more than address bit wide M of frequency sweep profile memory, is then given, as the reading address of the latter in the former high M position by bit wide N of frequency sweep time accumulated value 421.
Frequency sweep time totalizer adds up one week, then all frequency sweep curve sampling points 422 read from frequency sweep profile memory are exactly a frequency sweep cycle.
Described skew multiplier 403, for being multiplied with frequency sweep deviation ratio 433 by described frequency sweep curve sampling point 422, obtains the increment 423 of swept frequency word.This frequency sweep deviation ratio 433 is previously written skew multiplier 403 by processor.The multiplication formula of this skew multiplier 403 is as follows:
Increment 423=frequency sweep curve sampling point 422 × frequency sweep deviation ratio 433 (formula 2) of swept frequency word
Described frequency word adder 404, for being added with basic swept frequency word 434 by the increment 423 of described swept frequency word, obtains carrier wave swept frequency word 424, it is assumed that its bit wide is K position.This basic swept frequency word 434 is previously written frequency word adder 404 by processor.The addition formula of this frequency word adder 404 is as follows:
The increment 423 (formula 3) of carrier wave swept frequency word 424=basic swept frequency word 434+ swept frequency word
Described frequency accumulator 405, for adding up described carrier wave swept frequency word 424, obtains carrier wave memorizer and reads address 425.
For frequency accumulator 405, described carrier wave swept frequency word 424 is added up by it, it is assumed that at some moment M of main clock pulse, the result (i.e. address 425 read by carrier wave memorizer) of frequency accumulator 405 output is PM；The result of previous moment M-1 output is PM-1, then there is a following relation:
PM=PM-1+ carrier wave swept frequency word 424 (formula 4)
By formula 2,3,4 it should be apparent that frequency sweep curve determines the frequency variation pattern of swept-frequency signal.
On the other hand according to formula 2, as a example by the frequency sweep profile memory of 16 bit data bit wides, the scope of its frequency sweep curve is 0～0xFFFF.If user have modified the initial frequency of frequency sweep, terminates frequency, frequency sweep deviation ratio 433 and basic swept frequency word 434 the most only need to be revised, it is not necessary to amendment 2MThe frequency sweep curve of individual sampling point, is so greatly improved system effectiveness.The frequency word corresponding to the reckling between initial frequency and termination frequency can be calculated, with KW according to formula 4minRepresent；Frequency word corresponding to the maximum therebetween is with KWmaxRepresent.Still as a example by the frequency sweep profile memory of 16 bit data bit wides, then there is following relational expression between them:
Basic swept frequency word 434=KWmin(formula 5)
Frequency sweep deviation ratio 433=(KWmax-KWmin)/65535 (formula 6)
Described carrier wave memorizer 406, reads the corresponding sampling point of deposited carrier wave sampling point collection 435 for reading address 425 according to described carrier wave memorizer, and exports this outgoing carrier 426.This carrier wave sampling point collection 435 is pre-deposited carrier wave memorizer 406 by processor.This carrier wave sampling point integrates 435 as the sampling point set in a cycle of carrier wave shape.This carrier wave shape can be sine wave, square wave, sawtooth waveforms etc..This outgoing carrier 426 is exactly the Digital Sweep signal that frequency changes according to sweep method.Inside FPGA, it is permanent envelope, if being directly output to DAC, device and analog channel amplitude flatness are deteriorated the most after filtering.
Described amplitude-frequency compensating unit, for reading the corresponding sampling point of deposited amplitude-frequency compensating curve 436 according to described frequency sweep time accumulated value 421, and exports this output compensation 428.This amplitude-frequency compensating curve 436 is pre-deposited amplitude-frequency compensating unit by processor.
Described compensation multiplier 409, receives outgoing carrier 426 and output compensation 428, is multiplied for outgoing carrier 426 is compensated 428 with output, obtains the swept-frequency signal after Amplitude Compensation.
As it was noted above, the amplitude-versus-frequency curve of the signaling system being made up of DAC, wave filter, analog channel is uneven, but the equipment such as this curve negotiating circuit tester, energy meter can be measured.The present invention i.e. utilizes this point that swept-frequency signal is carried out full rate compensation.Its ultimate principle is to utilize A=A × (1/B) × B formula: A is the swept-frequency signal of permanent envelope herein；B is the uneven amplitude-versus-frequency curve of above-mentioned signaling system；1/B is the inverse of this amplitude-versus-frequency curve, referred to as amplitude-frequency compensating curve.The present invention is i.e. before FPGA module output swept-frequency signal, change according to its frequency, first it is multiplied by this amplitude-frequency compensating curve (i.e. the inverse of amplitude-versus-frequency curve), then through follow-up DAC, wave filter, analog channel signaling system after, this swept-frequency signal remains permanent envelope, solves amplitude flatness problem during frequency sweep.
Signal generator has a process calibrated before dispatching from the factory, and in order to obtain above-mentioned amplitude-frequency compensating curve, uses the flow process shown in Fig. 4.During calibration, carrier wave is shaped as sine wave, amplitude-frequency compensating curve is constant, frequency range highest frequency value required by from 1KHz to product of linear frequency sweep mode, frequency sweep in configuration, what so FPGA exported is the sine wave of linear frequency sweep, owing to without compensation, its envelope is constant amplitude.Utilize the measurement equipment such as circuit tester, energy meter just can measure amplitude-versus-frequency curve；After computed in software, so that it may obtain amplitude-frequency compensating curve.
Due to, outgoing carrier 426 is obtained after a series of resume module such as frequency sweep profile memory 402, skew multiplier 403, frequency word adder 404, frequency accumulator 405, carrier wave memorizer 406 by frequency sweep time accumulated value 421, and exports compensation 428 and obtained through the process of amplitude-frequency compensating unit by frequency sweep time accumulated value 421.Therefore, usual outgoing carrier 426 and output compensate and there is the time difference between 428.In order to make outgoing carrier 426 with output compensate 428 in sequential consistent, then need to arrange compensation delay cell in described amplitude-frequency compensating unit.
As it is shown on figure 3, described amplitude-frequency compensating unit is provided with compensation delay 407 and amplitude-frequency compensation memory 408.
Described compensation delay 407, receiving frequency-sweeping time accumulated value 421, for described frequency sweep time accumulated value 421 is carried out delay disposal, the frequency sweep time accumulated value after being postponed, read address 427 as amplitude-frequency compensation memory.
Described amplitude-frequency compensation memory 408, reads the corresponding sampling point of deposited amplitude-frequency compensating curve 436 for reading address 427 according to described amplitude-frequency compensation memory, and exports this output compensation 428.This amplitude-frequency compensating curve 436 is pre-deposited amplitude-frequency compensation memory 408 by processor.
The present embodiment is to make to postpone to frequency sweep time accumulated value 421, it is also possible to the output to amplitude-frequency compensation memory 408 is made to postpone, and purpose is all to make sequential between outgoing carrier 426 with output compensation 428 consistent, and concrete scheme is as follows:
Described amplitude-frequency compensating unit is provided with compensation postpone and amplitude-frequency compensation memory.
Described amplitude-frequency compensation memory, for according to described frequency sweep time accumulated value read deposited amplitude-frequency compensating curve corresponding sampling point, and export this do not postpone output compensation.This amplitude-frequency compensating curve is pre-deposited amplitude-frequency compensation memory by processor.
Described compensation postpones, and receives this and does not postpones output and compensate, for not postponing to export compensation carry out delay disposal to described, and output after being postponed compensation.
According to Fig. 3, there are two data paths between frequency sweep time totalizer 401 and compensation multiplier 409, starting point is frequency sweep time accumulated value 421, path 1:421 → 422 → 423 → 424 → 425 → 426；Path 2:421 → 427 → 428.The internal all modules of FPGA are all in 420 times work of main clock pulse, and the processing module of 1 process of path is the most, and the processing module of path 2 is less.Postpone without compensating, then the time delay of path 1 is greater than the time delay of path 2.In order to make the two time delay consistent, need, by compensation Postponement module 407, path 2 is carried out extra delay.Time delay between path 1,2 specifically differs, relevant with implementing of FPGA.
Fig. 5 is the signal generating method flow chart with Amplitude Compensation function.As it can be seen, the swept-frequency signal that this signal generating method is generated by FPGA module, carry out digital-to-analogue conversion through DAC module, low pass filter carries out low-pass filtering and analog channel carries out amplitude process, forms the swept-frequency signal of final output.Wherein, this FPGA module generates swept-frequency signal, including:
With frequency sweep time control word 431 Accumulating generation frequency sweep time accumulated value 421, and this frequency sweep time accumulated value 421 is respectively sent to frequency sweep profile memory 402 and amplitude-frequency compensating unit；
Transmission processes to the frequency sweep time accumulated value 421 of frequency sweep profile memory 402 through following:
Based on the frequency sweep curve 432 pre-set, export the frequency sweep curve sampling point 422 of correspondence according to described frequency sweep time accumulated value 421；
Described frequency sweep curve sampling point 422 is multiplied with frequency sweep deviation ratio 433, obtains the increment 423 of swept frequency word；
The increment 423 of described swept frequency word is added with basic swept frequency word 434, obtains carrier wave swept frequency word 424；
Described carrier wave swept frequency word 424 is added up, obtains carrier wave memorizer and read address 425；
Read address 425 according to described carrier wave memorizer and read the corresponding sampling point of deposited carrier wave sampling point collection 435, and export this outgoing carrier 426.
Transmission processes to the frequency sweep time accumulated value 421 of amplitude-frequency compensating unit through following:
Read the corresponding sampling point of deposited amplitude-frequency compensating curve 436 according to described frequency sweep time accumulated value 421, and export this output compensation 428.
With output, outgoing carrier 426 is compensated 428 be multiplied, obtain the swept-frequency signal after Amplitude Compensation.
As it was previously stated, wherein amplitude-frequency compensating curve 436 be DAC, the inverse of the amplitude-versus-frequency curve of signaling system that constituted of wave filter, analog channel.
Described transmission to the processing procedure of the frequency sweep time accumulated value 421 of amplitude-frequency compensating unit specifically includes following steps:
Described frequency sweep time accumulated value 421 is carried out delay disposal, the frequency sweep time accumulated value after being postponed, read address 427 as amplitude-frequency compensation memory；
Read address 427 according to described amplitude-frequency compensation memory and read the corresponding sampling point of deposited amplitude-frequency compensating curve 436, and export this output compensation 428.
Equally, this transmission can also be such as following step to the processing procedure of the frequency sweep time accumulated value 421 of amplitude-frequency compensating unit:
According to described frequency sweep time accumulated value read deposited amplitude-frequency compensating curve corresponding sampling point, and export this do not postpone output compensation；
Do not postpone to export compensation carry out delay disposal to described, output after being postponed compensation.
In sum, the invention provides a kind of signal generator with Amplitude Compensation function and method thereof, before FPGA module output swept-frequency signal, change according to its frequency, first it is multiplied by this amplitude-frequency compensating curve, then through follow-up DAC, low pass filter, analog channel signaling system after, this swept-frequency signal remains permanent envelope, solves amplitude flatness problem during frequency sweep.Further, when the initial frequency of this signal generator frequency sweep, termination frequency shift, only need to configure the fundamental quantity of frequency sweep deviation ratio and frequency word, it is not necessary to amendment frequency sweep profile memory, substantially increase system effectiveness.Persons skilled in the art are done the most creative any transformation under this design philosophy, are regarded as within protection scope of the present invention.
Claims (8)
1. there is a signal generator for Amplitude Compensation function, including: FPGA module, DAC module, low pass filter and analog channel；Described FPGA module is used for generating swept-frequency signal；This swept-frequency signal passes sequentially through DAC module, low pass filter and analog channel and processes, and forms the swept-frequency signal of final output；It is characterized in that: described FPGA module includes: clock module, frequency sweep time totalizer, frequency sweep profile memory, skew multiplier, frequency word adder, frequency accumulator, carrier wave memorizer, amplitude-frequency compensating unit and compensation multiplier；
Described clock module, for providing master clock for other modules of FPGA module inside；
Described frequency sweep time totalizer, is used for control word Accumulating generation frequency sweep time, accumulated value frequency sweep time, and this frequency sweep time accumulated value is respectively sent to frequency sweep profile memory and amplitude-frequency compensating unit；
Described frequency sweep profile memory, for based on the frequency sweep curve pre-set, according to the frequency sweep curve sampling point that the output of described frequency sweep time accumulated value is corresponding；
Described skew multiplier, for being multiplied with frequency sweep deviation ratio by described frequency sweep curve sampling point, obtains the increment of swept frequency word；
Described frequency word adder, for being added with basic swept frequency word by the increment of described swept frequency word, obtains carrier wave swept frequency word；
Described frequency accumulator, for adding up described carrier wave swept frequency word, obtains carrier wave memorizer and reads address；
Described carrier wave memorizer, reads the corresponding sampling point of deposited carrier wave sampling point collection for reading address according to described carrier wave memorizer, and exports outgoing carrier；
Described amplitude-frequency compensating unit, for reading the corresponding sampling point of deposited amplitude-frequency compensating curve according to described frequency sweep time accumulated value, and exports compensation；
Described compensation multiplier, receives outgoing carrier and output compensates, and for being multiplied with output compensation by outgoing carrier, obtains the swept-frequency signal after Amplitude Compensation.
There is the signal generator of Amplitude Compensation function the most as claimed in claim 1, it is characterised in that: described amplitude-frequency compensating unit is provided with compensation and postpones and amplitude-frequency compensation memory；
Described compensation postpones, receiving frequency-sweeping time accumulated value, for described frequency sweep time accumulated value is carried out delay disposal, obtains amplitude-frequency compensation memory and reads address；
Described amplitude-frequency compensation memory, reads the corresponding sampling point of deposited amplitude-frequency compensating curve for reading address according to described amplitude-frequency compensation memory, and exports this output compensation.
There is the signal generator of Amplitude Compensation function the most as claimed in claim 1, it is characterised in that: described amplitude-frequency compensating unit is provided with compensation and postpones and amplitude-frequency compensation memory；
Described amplitude-frequency compensation memory, for reading the corresponding sampling point of deposited amplitude-frequency compensating curve according to described frequency sweep time accumulated value, and output does not postpones output and compensates；
Described compensation postpones, and receives this and does not postpones output and compensate, for not postponing to export compensation carry out delay disposal to described, and output after being postponed compensation.
4. the signal generator with Amplitude Compensation function as described in claim 1,2 or 3, it is characterised in that: the inverse of the amplitude-versus-frequency curve of the signaling system that described amplitude-frequency compensating curve is constituted by described DAC module, low pass filter, analog channel.
5. there is a signal generating method for Amplitude Compensation function, FPGA module the swept-frequency signal generated, carry out digital-to-analogue conversion through DAC module, low pass filter carries out low-pass filtering and analog channel carries out amplitude process, forms the swept-frequency signal of final output；It is characterized in that: described FPGA module generates the process of swept-frequency signal, including:
With control word Accumulating generation frequency sweep time, accumulated value frequency sweep time, and this frequency sweep time accumulated value is respectively sent to frequency sweep profile memory and amplitude-frequency compensating unit；
Transmission processes to the frequency sweep time accumulated value of frequency sweep profile memory through following:
Based on the frequency sweep curve pre-set, according to the frequency sweep curve sampling point that the output of described frequency sweep time accumulated value is corresponding；
Described frequency sweep curve sampling point is multiplied with frequency sweep deviation ratio, obtains the increment of swept frequency word；
The increment of described swept frequency word is added with basic swept frequency word, obtains carrier wave swept frequency word；
Described carrier wave swept frequency word is added up, obtains carrier wave memorizer and read address；
Read address according to described carrier wave memorizer and read the corresponding sampling point of deposited carrier wave sampling point collection, and export outgoing carrier；
Transmission processes to the frequency sweep time accumulated value of amplitude-frequency compensating unit through following:
Read the corresponding sampling point of deposited amplitude-frequency compensating curve according to described frequency sweep time accumulated value, and export compensation；
Outgoing carrier is multiplied with output compensation, obtains the swept-frequency signal after Amplitude Compensation.
There is the signal generating method of Amplitude Compensation function the most as claimed in claim 5, it is characterised in that: the processing procedure of the frequency sweep time accumulated value of described transmission to amplitude-frequency compensating unit comprises the steps:
Described frequency sweep time accumulated value is carried out delay disposal, obtains amplitude-frequency compensation memory and read address；
Read address according to described amplitude-frequency compensation memory and read the corresponding sampling point of deposited amplitude-frequency compensating curve, and export this output compensation.
There is the signal generating method of Amplitude Compensation function the most as claimed in claim 5, it is characterised in that: the processing procedure of the frequency sweep time accumulated value of described transmission to amplitude-frequency compensating unit comprises the steps:
Read the corresponding sampling point of deposited amplitude-frequency compensating curve according to described frequency sweep time accumulated value, and output does not postpones output and compensates；
Do not postpone to export compensation carry out delay disposal to described, output after being postponed compensation.
8. the signal generating method with Amplitude Compensation function as described in claim 5,6 or 7, it is characterised in that: the inverse of the amplitude-versus-frequency curve of the signaling system that described amplitude-frequency compensating curve is constituted by described DAC module, low pass filter, analog channel.
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| CN104935258B (en) * | 2014-03-18 | 2019-08-13 | 苏州普源精电科技有限公司 | A kind of swept signal generator can produce multiple frequency markings |
| CN104734701A (en) * | 2015-04-08 | 2015-06-24 | 中国科学院光电技术研究所 | Low-stray DDS single-frequency signal generator |
| CN106502308B (en) * | 2016-09-20 | 2019-02-05 | 江苏大学 | A kind of wave generator system and production method of ultrasonic pulse pumping signal |
| CN110988464A (en) * | 2018-12-05 | 2020-04-10 | 苏州普源精电科技有限公司 | Calibration method and system for improving signal source precision |
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