CN103177772A - Flash memory test method - Google Patents
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- CN103177772A CN103177772A CN2011104289182A CN201110428918A CN103177772A CN 103177772 A CN103177772 A CN 103177772A CN 2011104289182 A CN2011104289182 A CN 2011104289182A CN 201110428918 A CN201110428918 A CN 201110428918A CN 103177772 A CN103177772 A CN 103177772A
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Abstract
A flash memory test method is used for choosing a flash memory having defects to recover a usable flash memory, wherein the flash memory at least includes a block, a page and a cell. The method comprises the following steps: inputting a test instruction to the flash memory, writing in, reading or comparing the flash memory, executing the test instruction to obtain the states of the block, the page and the cell in the flash memory, and marking the states in a flash memory distribution list to make a controller access at least one of the block, the page and the cell in a normal state through the flash memory distribution list. The block, the page and the cell for the normal use can be obtained through the test of the flash memory in the invention.
Description
Technical field
The present invention relates to a kind of flash memory method of testing, relate in particular to and a kind ofly be applied to pick out the defective flash memory of tool to be recycled into the method for available flash memory.
Background technology
In tradition, the flash memory with memory zone (comprising block, the page and structure cell) can produce phenomenon aging, that fail and damage along with the time of using, and then causes using the electronic installation of this flash memory to face situation about can't use.
Electronic product (such as intelligent mobile phone, digital camera, memory card etc.) by using this flash memory is the example explanation, when this electronic product after the service time through 2 years or 3 years, defective might occur or get back to the original manufacturer of this electronic product via recovery system.This traditional original manufacturer can decompose this electronic product, to reclaim available unit such as LCD display panel, printed circuit board (PCB) and flash memory (such as Sheffer stroke gate (NAND) flash memory) etc., and again via after assembling, test and packing, become the electronic product of low order comparatively and again sell in the mode of renewing product or new product.Yet, take flash memory as example, might find only to have this memory zone of part can be for normally after reclaiming, it is regional that for example originally flash memory has this memory of 64G, so damaged the memory zone of 10G after a period of time, make this flash memory that can't normally use this 64G, and then discarded this flash memory that uses.
Therefore can reclaim the flash memory that has 64G originally by flash memory method of testing provided by the present invention, via selecting, detect with the process that reconfigures of processing etc. and forming the flash memory that can use standard memory capacitys such as 32G, 16G, 8G, 4G, 2G or 1G or non-standard memory capacity, in order to reduce costs and to reach the purpose of environmental protection.
Summary of the invention
The object of the present invention is to provide a kind of flash memory method of testing, by flash memory being selected, detected and the method for processing, can be recovered in after tested in order to reach the purpose that still can normally use region of memory (for example memory region, the memory page and memory cell) in flash memory.
For solving above-mentioned purpose, the invention provides a kind of flash memory method of testing, be applied to select the defective flash memory of tool to be recycled into available flash memory, and this flash memory comprises block (block), the page (page) and structure cell (cell) at least, the method comprises step (a) input one test instruction to this flash memory, this flash memory is write, read the start with its one at least relatively; Step (b) obtains this block, this page and this structure cell after carrying out this test instruction its one at least is normal or up-set condition; Its one at least of this block of step (c) mark, this page and this structure cell is to the flash memory distribution list; And step (d) is according to using at least one of this block, this page and this structure cell be labeled as normal condition in this flash memory distribution list.
Compare with prior art, flash memory method of testing of the present invention can be by selecting, detect and processing, with in prior art because of the flash memory that has the part defective to continue again to use via again configuration with control that to become spendable memory with recovery regional, in order to the effect that reaches environmental protection, reduces costs etc.
moreover, also can select passing through by method of the present invention, detecting and this block of processing in flash memory later, the state of this page and this structure cell offers the memory control unit in external electronic, use for this memory control unit and can dynamically adjust and configure by the state in this flash memory, thereby reach the serviceable life that extends this flash memory, the security when stability when improving this electronic installation operation and increase data storing, test mode of the present invention wherein, system can carry out separately under the state of this electronic installation dormancy or carry out simultaneously when this electronic installation carries out data access.For example, but the instruction of sending program by main frame or controller when this flash memory system is programmed or during reading out data, the present invention can provide the bug check correcting unit (Error Correcting Codes) to this flash memory to monitor, dynamically to guarantee having regional this main frame or this controller of can supplying of normal this memory to carry out the action of access.
In addition, the impact that also can avoid this flash memory electric because being subjected to (for example destruction of leakage current) environmental impact to cause by method of the present invention.
In addition, method of the present invention can be carried out the above confirmation action of secondary at least, last time be judged as the region of memory of this block, this page and this structure cell normally in test though make, can be because be adjacent to abnormal this region of memory, and make by this method normal this region of memory is tested again, form abnormal state of affairs in order to avoid normal this region of memory to be subject to the interference of abnormal this region of memory and impact.
Description of drawings
Fig. 1 is the method flow diagram of the flash memory method of testing of first embodiment of the invention;
Fig. 2 is the structural representation of the flash memory in key diagram 1;
Fig. 3 is the view of flash memory after resetting in key diagram 1;
Fig. 4 is that flash memory in key diagram 1 is through the view of sequential testing;
Fig. 5 is that flash memory in Fig. 1 is through the view of random test;
Fig. 6 is the method flow diagram of the flash memory method of testing of second embodiment of the invention;
Fig. 7 is the method flow diagram of the flash memory method of testing of third embodiment of the invention;
Fig. 8 is the method flow diagram of the flash memory method of testing of fourth embodiment of the invention;
Fig. 9 is the method flow diagram of the flash memory method of testing of fifth embodiment of the invention;
Figure 10 is the method flow diagram of the flash memory method of testing of sixth embodiment of the invention;
Figure 11 is the structural representation of the flash memory method of testing of explanation Figure 10;
Figure 12 is the method flow diagram of the flash memory method of testing of seventh embodiment of the invention;
Figure 13 is the structural representation of the flash memory method of testing of explanation Figure 12;
Figure 14 is the method flow diagram of the flash memory method of testing of eighth embodiment of the invention; And
Figure 15 is the method flow diagram of the flash memory method of testing of ninth embodiment of the invention.
[primary clustering symbol description]
2 flash memories
22 blocks
24 pages
26 structure cells
262 normal structure cells
264 undesired structure cells
The TC test instruction
101-112 remembers the zone
Embodiment
For fully understanding purpose of the present invention, feature and effect, existing by following specific embodiment, and coordinate appended graphicly, the present invention is described in detail, illustrate as after:
With reference to Fig. 1, be the method flow diagram of the flash memory method of testing of first embodiment of the invention.In Fig. 1, this flash memory method of testing is applied to select the defective flash memory of tool to be recycled into available flash memory.Wherein, this flash memory 2 comprises the memory zone of block 22, the page 24 and structure cell 26 etc. at least, and this structure cell 26 also comprises normal structure cell 262 and undesired structure cell 264, as shown in Figure 2.Moreover, be defined as at this normal structure cell 262 access that data can be provided normally; Otherwise undesired structure cell 264 can't carry out the access of data normally.
The method step of this flash memory method of testing originates in step S11, input a test instruction TC to this flash memory 2, with this flash memory 2 is write, reads with relatively at least one action, for example this test instruction can be the instruction of erasing (ERASE command).In an embodiment, this flash memory 2 can be according to this test instruction TC to reset to the state with default value with this block 22, this page 24 with this structure cell 26, and for example this default value can be 0xFF.
For example, in the lump can be with reference to shown in Figure 3, in Fig. 3, this flash memory 2 is receiving this test instruction TC (instruction of for example erasing) afterwards, the content of this normal structure cell 262 of this page 24 that is arranged in this block 22 in this flash memory 2 is reset and is 0xFF, and the content in this undesired structure cell 264 is the non-0xFF that resets to.
Follow step S12, the one at least of obtaining after carrying out this test instruction TC in this block 22, this page 24 and this structure cell 26 is normal or up-set condition.In other words, can by the state in this block 22 of detecting, this page 24 and this structure cell 26, whether be normal or abnormal memory zone in order to distinguish.
Moreover this step S12 can comprise sequentially or obtain randomly one of them individual state of this block 22, this page 24 and this structure cell 26.Wherein, the mode of order can begin sequentially to detect from this memory regional 101 according to the putting in order of the regional 101-112 of this memory in this flash memory 2, and then detects this memory regional 102, until detected this memory regional 112 to obtain the regional state of this memory, as shown in Figure 4.In addition, random mode can be when this flash memory 2 has specific behavior (behave) or pattern (pattern), with specific detecting path to obtain the state in this memory zone, for example this detecting path system can detect this memory regional 101 of odd number, 103, state in 105 grades, as shown in Figure 5.
For example, follow aforesaid example, the state that this step S12 can be its one at least in this block 22 relatively, this page 24 and this structure cell 26 with this default value with the generation comparative result, also namely after receiving this instruction of erasing, this structure cell 26 is reset and is 0xFF, and whether be 0xFF by the content of detecting in this structure cell 26, and in order to judge that this structure cell 26 is these normal structure cells 262 or is this undesired structure cell 264.
Follow again step S13, its one at least of this block 22 of mark, this page 24 and this structure cell 26 is to the flash memory distribution list.In other words, after step S12, be to determine whether this structure cell 26 is normal structure cell 262 or undesired structure cell 264, and respectively this normal structure cell 262 of mark with this undesired structure cell 262 at this flash memory distribution list.
Step S14 then is according to using its one at least of this block, this page and this structure cell that have been labeled as normal condition in this flash memory distribution list.In other words, outside controller (controller) or main frame (host) can read normally by this flash memory distribution list should memory regional, and it is regional to avoid reading abnormal this memory.
With reference to Fig. 6, the method flow diagram of the flash memory method of testing of second embodiment of the invention.In Fig. 6, this flash memory method of testing more can comprise step S61 after step S12, repairs this structure cell of up-set condition by bug check correcting unit (Error Correcting Codes, ECC).Wherein, this bug check correcting unit has the maximum correction quantity of repairing for this structure cell.
Follow again step S62, calculate the structure cell correction quantity of repairing this structure cell of this up-set condition by this bug check correcting unit.
And after step S61 and S62, also comprise step S63, further this structure cell of judgement is proofreaied and correct the ratio that quantity accounts for this maximum correction quantity, makes when allowing ratio, this structure cell through repairing this up-set condition to be tagged to this flash memory distribution list with normal condition less than default when this ratio.Wherein, this default allowable value is 50%, also namely proofreaies and correct quantity system by this structure cell of proofreading and correct and occupies and can allow half ratio of the maximum correction quantity of proofreading and correct by this bug check correcting unit.As example, if this maximum correction quantity is 48, there are 24 and need as calculated to proofread and correct abnormal this structure cell, work as the quantity of this structure cell that need to proofread and correct lower than a half of this maximum correction quantity, through undesired this structure cell that this bug check correcting unit is proofreaied and correct, can be denoted as spendable normal this structure cell in this flash memory distribution list.
If not be the state of step S63, execution in step S64, default when allowing ratio greater than this when this ratio, will keep with up-set condition through this structure cell of repairing this up-set condition and be tagged to this flash memory distribution list.Due to, undesired this structure cell quantity that needs in this step S64 to proofread and correct is greater than these default ratio row of allowing, although abnormal this structure cell still can be proofreaied and correct by this bug check correcting unit, but for guaranteeing stability and the correctness of the access that whole this data in flash memory transmits, judge still that by this step this flash memory distribution list is labeled as abnormal this structure cell.
With reference to Fig. 7, be the method flow diagram of the flash memory method of testing of third embodiment of the invention.In Fig. 7, this flash memory method of testing more can comprise step S71 before step S11, control module sends the instruction of erasing (ERASE command) and programming instruction (programming command) to this flash memory 2, with at the upper state of waiting for (ready) or busy (busy) that produces of the status pin (for example stitch of R/B) of this flash memory 2.In another embodiment, this control module sends this erase instruction and this programming instruction to this flash memory 2, produces the state of corresponding addressing (address) with the status pin at the I/O of this flash memory 2.
Then step S72, judge this wait or busy state, has its one at least of normal this block 22, this page 24 and this structure cell 26 to test this flash memory 2.
Result according to this step S72, follow again execution in step S11 to step S14, make this flash memory 2 to judge for the second time more accurately by writing, read with mode relatively, make and to pass through step S11 to S14, strengthen in this step S71 to S72 and test by control module the result that obtains.
With reference to Fig. 8, be the method flow diagram of the flash memory method of testing of fourth embodiment of the invention.In Fig. 8, except having roughly the same step with previous embodiment, after also being included in step S71, follow step S81, erase instruction and this programming instruction to this flash memory sending this, determining at complete this of this flash memory erase instruction and this programming instruction, for example this scheduled wait time coefficient second or tens of seconds, there is the sufficient time to complete test to this flash memory in order to determine those instructions through the scheduled wait time.
Follow again step S82, receive the mark banner that this erase instruction and this programming instruction are completed in this flash memory executed.And following step S83, again more further according to this mark banner, judge again again whether this flash memory is this flash memory that reclaims, to follow execution in step S84 and S85.Wherein, this step S84, when this flash memory of judgement was not this flash memory that reclaims, this flash memory waited for receiving next test instruction; And this step S85 when this flash memory of judgement is the flash memory that reclaims, postpones one and extends the stand-by period and carry out this flash memory again and receive next test instruction to wait for.In other words, if this flash memory during for the flash memory that reclaims, gives the extra more suitable prolongation stand-by period, with etc. result to be tested and can guarantee to obtain test result more accurately.
With reference to Fig. 9, the method flow diagram of the flash memory method of testing of fifth embodiment of the invention.In Fig. 9, also can comprise step S91 judgement after this step S71 sends at control module and erases instruction and programming instruction to this flash memory 2, in the status pin of this flash memory 2 (for example R/B or I/O port) when keeping all the time noble potential (pull high) or electronegative potential (pull low), abandon the judgement of this wait or busy condition, and fetch again this wait or busy state after one period time delay.
With reference to Figure 10, be the method flow diagram of the flash memory method of testing of sixth embodiment of the invention.In Figure 10, also comprise step S101 after step S12, to the plurality of blocks of contiguous this block that up-set condition occurs execution in step S12 again, to carry out the detection that influences each other between those blocks.
For example, can be with reference to Figure 11, Figure 11 has this block BA-BI.When this block of judgement BE was detected as abnormal block, judgement was positioned at this block BE contiguous this block BB, BD, BH and BF again.Wherein, this block BB, BD, BH and BF might when last time judging, be judged as normal block.
With reference to Figure 12, be the method flow diagram of the flash memory method of testing of seventh embodiment of the invention.In Figure 12, also comprise step S121 after step S12, to the plural page of contiguous this page that up-set condition occurs execution in step S12 again, carry out the detection that influences each other of those pages with page group (page group).
For example, can be with reference to Figure 13, Figure 13 has this page PA-PI.When judgement this page PB is detected as abnormal block, take this page group (for example PA, PB, PC are defined as the page group) again judgement and this page PB as this page PA and PC with this page group.Wherein, this page PA and PC might when last time judging, be judged as the normal page.
With reference to Figure 14, the method flow diagram of the flash memory method of testing of eighth embodiment of the invention.In Figure 14; this flash memory method of testing comprises step S141 after step S12; this structure cell quantity of monitoring bug check correcting unit (the Error Correcting Codes) up-set condition of repairing, take according to its one at least of this block of variable quantity mark, this page and this structure cell of this structure cell quantity as normally or up-set condition.In other words, when for example carrying out reading command, can by the quantity of proofreading and correct in this bug check correcting unit of monitoring, there be N/R state that (for example each quantity of proofreading and correct is indefinite) occurs in order to judgement.If produce abnormal state, represent that this flash memory has unsettled this block, this page and this structure cell.
With reference to Figure 15, the method flow diagram of the flash memory method of testing of ninth embodiment of the invention.In Figure 15, this flash memory method of testing comprises step S151 after step S14, after certain test duration, then re-execute step S11 to step S14, change up-set condition with its one at least of avoiding this block, this page and this structure cell through being labeled as normal condition into because of electric leakage.
The present invention is open with preferred embodiment hereinbefore, but those of ordinary skill in the art it should be understood that this embodiment only is used for describing the present invention, do not limit the scope of the invention and should not be read as.It should be noted that variation and the displacement of all and this embodiment equivalence all should be made as and be covered by in category of the present invention.Therefore, protection scope of the present invention when with claim the person of being defined be as the criterion.
Claims (21)
1. a flash memory method of testing, is characterized in that, is applied to select the defective flash memory of tool being recycled into available flash memory, and this flash memory comprises block, the page and structure cell at least, and the method comprises:
The input test instruction is to this flash memory, this flash memory is write, read and one of them action of comparing;
One of them that obtains this block, this page and this structure cell after carrying out this test instruction is normally or up-set condition;
One of them of this block of mark, this page and this structure cell is individual to the flash memory distribution list; And
According to using at least one in this block, this page and this structure cell that has been labeled as normal condition in this flash memory distribution list.
2. flash memory method of testing as claimed in claim 1, is characterized in that, step (a) comprises according to this test instruction with in this block, this page and this structure cell, one of them resets to the state with default value.
3. flash memory method of testing as claimed in claim 2, is characterized in that, one of them the state that comprises relatively this block, this page and this structure cell in step (b) with this default value with the generation comparative result.
4. flash memory method of testing as claimed in claim 3, is characterized in that, step (c) comprise according in this this block of comparative result mark, this page and this structure cell one of them.
5. flash memory method of testing as claimed in claim 4, is characterized in that, this test instruction is the instruction of erasing.
6. flash memory method of testing as claimed in claim 5, is characterized in that, this predetermined value is 0xFF.
7. flash memory method of testing as claimed in claim 1 or 2, is characterized in that, step (b) comprises sequentially or randomly obtain one of them individual state of this block, this page and this structure cell.
8. flash memory method of testing as claimed in claim 1, is characterized in that, (b) comprises afterwards in step:
(e) repair this structure cell of up-set condition by the bug check correcting unit, wherein this bug check correcting unit has a maximum correction quantity of repairing for this structure cell; And
(f) calculate the structure cell correction quantity of repairing this structure cell of this up-set condition by this bug check correcting unit.
9. flash memory method of testing as claimed in claim 8, is characterized in that, (f) also comprises afterwards in step:
(g) judge that this structure cell proofreaies and correct the ratio that quantity accounts for this maximum correction quantity so that when this ratio less than presetting when allowing ratio, this structure cell through repairing this up-set condition is tagged to this flash memory distribution list with normal condition.
10. flash memory method of testing as claimed in claim 8, is characterized in that, (g) more comprises afterwards in step:
(h) default when allowing ratio greater than this when this ratio, will keep with up-set condition through this structure cell of repairing this up-set condition and be tagged to this flash memory distribution list.
11. flash memory method of testing as described in claim 9 or 10 is characterized in that this default allowable value is 50%.
12. flash memory method of testing as claimed in claim 1 is characterized in that, (a) also comprises before in step:
(i) control module sends erase instruction and programming instruction to this flash memory, waits for or busy state to produce on the status pin of this flash memory; And
(j) judge this wait or busy state, its one at least of normal this block, this page and this structure cell is arranged to test this flash memory cording.
13. flash memory method of testing as claimed in claim 12, it is characterized in that, this step (i) also is included in to be sent this and erases instruction and this programming instruction to this flash memory, through certain scheduled wait time to determine at complete this of this flash memory erase instruction and this programming instruction.
14. flash memory method of testing as claimed in claim 13 is characterized in that, also comprises:
(k) receive the mark banner that this erase instruction and this programming instruction are completed in this flash memory executed; And
(l) according to this mark banner, judge again again whether this flash memory is this flash memory that reclaims.
15. flash memory method of testing as claimed in claim 14 is characterized in that, comprises afterwards when this flash memory of judgement is this flash memory that reclaims in step (l), the delay prolongation stand-by period carries out this flash memory again and receives next test instruction to wait for.
16. flash memory method of testing as claimed in claim 12, it is characterized in that, comprise when this wait or busy when keeping noble potential or electronegative potential in step (i), abandon the judgement of this wait or busy condition, and fetch again this wait or busy state after one period time delay.
17. flash memory method of testing as claimed in claim 1 is characterized in that, (b) also comprises afterwards in step:
(m) to a plurality of blocks of contiguous this block that up-set condition occurs execution in step (b) again, to carry out the detection that influences each other between these blocks.
18. flash memory method of testing as claimed in claim 1 is characterized in that, (b) also comprises afterwards in step:
(n) to a plurality of pages of contiguous this page that up-set condition occurs execution in step (b) again, group carries out the detection that influences each other of these pages with the page.
19. flash memory method of testing as claimed in claim 1 is characterized in that, (a) also comprises before in step:
(o) keep noble potential or electronegative potential according to the transmission port of this flash memory, obtain the data of wrong this page to judge this transmission port.
20. flash memory method of testing as claimed in claim 1 is characterized in that, (b) comprises afterwards in step:
(p) this structure cell quantity of monitoring bug check up-set condition that correcting unit is repaired is take individual according to one of them of this block of variable quantity mark, this page and this structure cell of this structure cell quantity as normally or up-set condition.
21. flash memory method of testing as claimed in claim 1 is characterized in that, (d) comprises afterwards in step:
(q) after certain test duration, then re-execute step (a) to step (d), one of them of this block, this page and this structure cell through being labeled as normal condition is individual changes up-set condition into because of electric leakage to avoid.
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Application publication date: 20130626 |