CN103176350A - Mask fabricating method for maximizing quantity of chips on wafer - Google Patents
Mask fabricating method for maximizing quantity of chips on wafer Download PDFInfo
- Publication number
- CN103176350A CN103176350A CN2011104419627A CN201110441962A CN103176350A CN 103176350 A CN103176350 A CN 103176350A CN 2011104419627 A CN2011104419627 A CN 2011104419627A CN 201110441962 A CN201110441962 A CN 201110441962A CN 103176350 A CN103176350 A CN 103176350A
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- Prior art keywords
- cutting road
- width
- cutting
- test pattern
- alignment mark
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Abstract
The invention relates to a mask fabricating method for maximizing quantity of chips on a wafer. The method comprises utilizing a multi-cutting path width when cutting paths on the mask are fabricated. By utilizing the design of the multi-cutting path width to the cutting paths of the mask, the mask fabricating method provided by the invention is capable of not only satisfying the requirement of cutting test, but also satisfying the increase of all the bare chips and the requirement of timely shipment to clients.
Description
Technical field
The present invention relates to semi-conductor chip and make the field, particularly relate to a kind of maximized mask manufacturing method of number of chips on wafer that makes.
Background technology
Along with the competition in the universal and market of electronic product, no matter be IC design corporation or wafer foundry, invariably trying every possible means maximizes chip (Chip) quantity on same wafer.Therefore the reduced width of Cutting Road (scriber line) each producer target of making great efforts especially on wafer.Rule of thumb, if reduce the Cutting Road width of 10um, just number of chips can increase by 1～2%, therefore the cost of one chip reduces.
But, due to the needs of wafer foundry because of production technology, often need to place test pattern (Testing Pattern) or alignment mark (Align.Mark) at Cutting Road, and because of the board restriction, test pattern or alignment mark can not dwindle infinitely.
Therefore, how can further reduce the Cutting Road width, increase the nude film total amount on a wafer, be the problem of needing at present solution badly.
Summary of the invention
For the defective that exists in prior art and deficiency, the objective of the invention is to make the maximized mask manufacturing method of number of chips on wafer, both can keep essential test pattern or alignment mark, can realize the purpose that Cutting Road dwindles again.
In order to achieve the above object, the present invention proposes a kind of maximized mask manufacturing method of number of chips on wafer that makes, and described method comprises: adopt multiple Cutting Road width when making the Cutting Road on light shield.
Preferred as technique scheme needs to place the wider width of the Cutting Road of test pattern or alignment mark, and the width of Cutting Road that does not need to place test pattern or alignment mark is narrower.
Preferred as technique scheme, the width that needs to place the Cutting Road of test pattern or alignment mark is standard Cutting Road width, does not need to place the width of Cutting Road of test pattern or alignment mark less than standard Cutting Road width.
Preferred as technique scheme do not need to place the width of Cutting Road of test pattern or alignment mark for satisfying the minimum widith of cutting.
The Cutting Road of the mask manufacturing method light shield that the present invention proposes adopts the design of multiple Cutting Road width, and the method both can satisfy the demand of test cutting, also can satisfy the increase of nude film total amount (Gross die) and shipment in real time to client's demand.
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail.For the person of ordinary skill in the field, from detailed description of the invention, above and other purpose of the present invention, feature and advantage will be apparent.
Description of drawings
Fig. 1 is the Cutting Road width indication figure of light shield in prior art;
Fig. 2 is according to the Cutting Road width indication figure of the first light shield of mask manufacturing method making of the present invention;
Fig. 3 is according to the Cutting Road width indication figure of the second light shield of mask manufacturing method making of the present invention.
Embodiment
During the tradition light shield manufacture, adopt identical cutting width, as shown in Figure 1, A1, A2, A3 are the Cutting Road width of standard, and wherein the part Cutting Road is not put any test pattern.And science and technology is flourishing now, and it is less that the size of nude film (Die Size) also can design, so cutting also intangibly becomes the problem that wasting space affects nude film total amount (Gross Die).
The present invention proposes a kind of maximized mask manufacturing method of number of chips on wafer that makes, and is when making light shield, and the Cutting Road on it adopts multiple Cutting Road width.
Particularly, need to place the wider width of the Cutting Road of test pattern or alignment mark, and it is narrower not need to place the width of Cutting Road of test pattern or alignment mark.
For example, needing the width of the Cutting Road of placement test pattern or alignment mark is standard Cutting Road width of the prior art, the width that does not need to place the Cutting Road of test pattern or alignment mark can be less than standard Cutting Road width, more preferably, the width that does not need to place the Cutting Road of test pattern or alignment mark gets final product to satisfying the follow-up minimum widith that wafer is cut into nude film.
Referring to Fig. 2 and Fig. 3, on light shield, A4, A5 Application standard Cutting Road width are for putting alignment mark or test pattern; As long as and B1, B2, B3, B4 can put less Cutting Road width and satisfy back segment cutting factory demand.Follow-up light shield manufacture and wafer production and prior art are as good as.Then the actual floor plan (Floor Plan) of putting light shield is offered test and cut factory, in order to making dependence test and cutting machine setting.
Although; the present invention clearly demonstrates by above embodiment and accompanying drawing thereof; yet in the situation that do not deviate from spirit of the present invention and essence thereof; the person of ordinary skill in the field works as can make according to the present invention various corresponding variations and correction, but these corresponding variations and correction all should belong to the protection domain of claim of the present invention.
Claims (4)
1. one kind makes the maximized mask manufacturing method of number of chips on wafer, it is characterized in that, described method comprises: adopt multiple Cutting Road width when making the Cutting Road on light shield.
2. mask manufacturing method according to claim 1, is characterized in that, need to place the wider width of the Cutting Road of test pattern or alignment mark, and the width of Cutting Road that does not need to place test pattern or alignment mark is narrower.
3. mask manufacturing method according to claim 1 and 2, it is characterized in that, width that need to place the Cutting Road of test pattern or alignment mark is standard Cutting Road width, does not need to place the width of Cutting Road of test pattern or alignment mark less than standard Cutting Road width.
4. mask manufacturing method according to claim 3, is characterized in that, do not need to place the width of Cutting Road of test pattern or alignment mark for satisfying the minimum widith of cutting.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011104419627A CN103176350A (en) | 2011-12-26 | 2011-12-26 | Mask fabricating method for maximizing quantity of chips on wafer |
| TW101138537A TW201327028A (en) | 2011-12-26 | 2012-10-19 | Mask production method for maximizing the number of chips on a wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011104419627A CN103176350A (en) | 2011-12-26 | 2011-12-26 | Mask fabricating method for maximizing quantity of chips on wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103176350A true CN103176350A (en) | 2013-06-26 |
Family
ID=48636319
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011104419627A Pending CN103176350A (en) | 2011-12-26 | 2011-12-26 | Mask fabricating method for maximizing quantity of chips on wafer |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN103176350A (en) |
| TW (1) | TW201327028A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116068844A (en) * | 2023-03-10 | 2023-05-05 | 合肥晶合集成电路股份有限公司 | Mask plate and preparation method of wafer |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI714865B (en) * | 2017-06-28 | 2021-01-01 | 矽創電子股份有限公司 | Wafer structure |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0318012A (en) * | 1989-06-14 | 1991-01-25 | Matsushita Electron Corp | Reticle for reducing-projection exposure apparatus |
| JPH0721624B2 (en) * | 1988-11-08 | 1995-03-08 | 日本電気株式会社 | Reticle for semiconductor integrated circuit |
| JP2002023344A (en) * | 2000-07-05 | 2002-01-23 | Seiko Epson Corp | Method for arranging scribing line, reticle and exposure method |
| JP2005283609A (en) * | 2004-03-26 | 2005-10-13 | Sharp Corp | Reticle for reduction projection aligner |
| CN101533229A (en) * | 2008-03-10 | 2009-09-16 | 精工电子有限公司 | Reticle for projection exposure apparatus and exposure method using the same |
| CN101750899A (en) * | 2008-12-04 | 2010-06-23 | 上海华虹Nec电子有限公司 | Lithography layout and method for measuring lithography deformation thereof |
-
2011
- 2011-12-26 CN CN2011104419627A patent/CN103176350A/en active Pending
-
2012
- 2012-10-19 TW TW101138537A patent/TW201327028A/en unknown
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0721624B2 (en) * | 1988-11-08 | 1995-03-08 | 日本電気株式会社 | Reticle for semiconductor integrated circuit |
| JPH0318012A (en) * | 1989-06-14 | 1991-01-25 | Matsushita Electron Corp | Reticle for reducing-projection exposure apparatus |
| JP2002023344A (en) * | 2000-07-05 | 2002-01-23 | Seiko Epson Corp | Method for arranging scribing line, reticle and exposure method |
| JP2005283609A (en) * | 2004-03-26 | 2005-10-13 | Sharp Corp | Reticle for reduction projection aligner |
| CN101533229A (en) * | 2008-03-10 | 2009-09-16 | 精工电子有限公司 | Reticle for projection exposure apparatus and exposure method using the same |
| CN101750899A (en) * | 2008-12-04 | 2010-06-23 | 上海华虹Nec电子有限公司 | Lithography layout and method for measuring lithography deformation thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116068844A (en) * | 2023-03-10 | 2023-05-05 | 合肥晶合集成电路股份有限公司 | Mask plate and preparation method of wafer |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201327028A (en) | 2013-07-01 |
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|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20130626 |