CN103165463B - The manufacture method of semiconductor device - Google Patents
The manufacture method of semiconductor device Download PDFInfo
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- CN103165463B CN103165463B CN201110426377.XA CN201110426377A CN103165463B CN 103165463 B CN103165463 B CN 103165463B CN 201110426377 A CN201110426377 A CN 201110426377A CN 103165463 B CN103165463 B CN 103165463B
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Abstract
The invention provides a kind of manufacture method of semiconductor device, comprise and semiconductor base is provided, there is the first conduction type; On semiconductor base, form epitaxial loayer, there is the first conduction type; Multiple first groove is formed in epitaxial loayer; Multiple first insulation liner layer is formed on the sidewall and bottom surface of the first groove; The wall doping epitaxial loayer of the first admixture along the first groove of the first conduction type will be had, to form multiple first doped region; First insulating material is inserted the first groove; Multiple second groove is formed in above-mentioned epitaxial loayer; Multiple second insulation liner layer is formed on the sidewall and bottom surface of the second groove; The wall doping epitaxial loayer of the second admixture along the second groove of the second conduction type will be had, to form multiple second doped region; Second insulating material is inserted the second groove.
Description
Technical field
The invention relates to a kind of manufacture method of semiconductor device, relate to a kind of manufacture method with the semiconductor device of super contact structure especially.
Background technology
Existing rectilinear diffusion metal-oxide half field effect transistor (VDMOSFET) mainly forms P-N junction by N-type extension (epitaxy) drift (drift region) district and its overlying p-type matrix (base) fusion district, and the withstand voltage mainly P-N junction of semiconductor element is born.When improving the operating voltage of semiconductor element, the dopant concentration of N-type extension drift region must be reduced and promote its thickness.Relative, the withstand voltage mode of above-mentioned lifting P-N junction also can increase the conducting resistance (Ron) of element simultaneously, and conducting resistance also can be subject to the dopant concentration of N-type extension drift region and the restriction of thickness.And the rectilinear diffusion metal-oxide half field effect transistor with super junction (Super-junction) structure can improve the dopant concentration of N-type extension drift region, and then improve the conducting resistance (Ron) of element.
Prior art utilizes multilayer epitaxial (multi-epi technology, COOLMOS
tM) technology forms super junction (Super-junction) structure, above-mentioned multilayer epitaxial technology needs the process cycles repeatedly comprising extension, implant P type admixture, High temperature diffusion.Therefore, above-mentioned multilayer epitaxial technology has that processing step is many, high in cost of production shortcoming, and the more difficult micro of component size.
Therefore, in this technical field, have and need a kind of manufacture method with the semiconductor device of super contact structure, to meet the demand and to overcome the shortcoming of prior art.
Summary of the invention
In view of this, one embodiment of the invention provides a kind of manufacture method of semiconductor device, and the manufacture method of above-mentioned semiconductor device comprises provides semiconductor substrate, has one first conduction type; On above-mentioned semiconductor base, form an epitaxial loayer, there is above-mentioned first conduction type; Multiple first groove is formed in above-mentioned epitaxial loayer; Compliance forms multiple first insulation liner layer on the sidewall and bottom surface of above-mentioned first groove; Carry out one first doping process, will the wall doping above-mentioned epitaxial loayer of one first admixture along above-mentioned first groove of above-mentioned first conduction type be had, to form multiple first doped region; One first insulating material is inserted above-mentioned first groove; Multiple second groove is formed in above-mentioned epitaxial loayer; Compliance forms multiple second insulation liner layer on the sidewall and bottom surface of above-mentioned second groove; Carry out one second doping process, will the wall doping above-mentioned epitaxial loayer of one second admixture along above-mentioned second groove of one second conduction type be had, to form multiple second doped region; One second insulating material is inserted above-mentioned second groove.
The present invention reaches effect of charge balance by the dopant concentration controlling N-type region territory and territory, p type island region.The dopant concentration that thus can reduce N-type epitaxy layer about can be down to about 1E14 ~ 4E13 from 2E15, can select required concentration according to element design.In addition, super contact structure of the present invention must not carry out extra epitaxy technique, thus can save process costs.Further, semiconductor element formed thereon can have less component size.
Accompanying drawing explanation
Fig. 1 to Fig. 7 is the profile of the manufacture method of the semiconductor device of one embodiment of the invention.
Drawing reference numeral:
500 ~ semiconductor device; 200 ~ semiconductor base;
201 ~ interface; 202 ~ epitaxial loayer;
203,213 ~ end face; 204 ~ the first grooves;
205,219 ~ bottom surface; 206 ~ the first insulation liner layer;
208,216 ~ doping process; 207,221 ~ sidewall;
210 ~ the first doped regions; 212 ~ the first insulating material;
218 ~ the second grooves; 220 ~ the second insulation liner layer;
222 ~ the second doped regions; 224 ~ gate oxidation layer pattern;
226 ~ grid layer pattern; 228 ~ grid structure;
230 ~ the second insulating material; 232 ~ the first wellblocks;
234 ~ source area; 236 ~ interlayer dielectric layer;
238 ~ contact hole opening; 240 ~ Wiring area;
242 ~ contact hole plug; 250 ~ super contact structure;
300 ~ active region; 302 ~ termination environment;
θ 1, θ 2 ~ angle.
Embodiment
To describe in detail with each embodiment below and along with the example of graphic explanation, as reference frame of the present invention.In graphic or specification describe, similar or identical part all uses identical figure number.And in the drawings, the shape of embodiment or thickness can expand, and to simplify or conveniently to indicate.Moreover the part of each element to describe explanation respectively, will it should be noted that in figure the element not illustrating or describe, for having the form usually known known to the knowledgeable in art in graphic.
Fig. 1 to Fig. 7 be the semiconductor device of one embodiment of the invention process section.The semiconductor device of the embodiment of the present invention comprises golden oxygen half thin-film transistor (MOSFET) with super junction (super junction) structure, such as, be the rectilinear diffusion metal-oxide half field effect transistor (VDMOSFET) of super junction.As shown in Figure 1, first, provide semiconductor substrate 200, there is one first conduction type.Then, carry out an epitaxial growth process, on this semiconductor base, form an epitaxial loayer 202.In an embodiment of the present invention, semiconductor base 200 and epitaxial loayer 202 have identical conduction type, and the dopant concentration of semiconductor base 200 is greater than the dopant concentration of epitaxial loayer 202.Therefore, in this example, semiconductor base 200 can be N-type heavy doping (N+) semiconductor base 200, and epitaxial loayer 202 can be N-type light dope (N-) epitaxial loayer 202.As shown in Figure 1, epitaxial loayer 202 can comprise an active region 300 and the termination environment 302 around active region 300.In an embodiment of the present invention, active region 300 provides semiconductor element formed thereon, and termination environment 302 is as the insulation between different semiconductor device.
Then, please refer to Fig. 2, the generation type of the first groove 204 is described.Such as low-pressure chemical vapor deposition (LPCVD) can be carried out and form a hard mask (Hard Mask), then a lithography process and Patternized technique is carried out, a mask pattern (figure does not show) is covered on the active region 300 of epitaxial loayer 202, define the forming position of the first groove, carry out an anisotropic etch process again, remove the portion of epi layer 202 do not covered by mask pattern, to form multiple first groove 204 in the active region 300 of epitaxial loayer 202.In an embodiment of the present invention, the bottom surface 205 of the first groove 204 can the interface 201 of contact semiconductor substrate 200 and epitaxial loayer 202, or is positioned at epitaxial loayer 202 (meaning is namely close to interface 201).
After removing above-mentioned mask pattern, then, carry out such as thermal oxidation (thermal oxidation) growth method, compliance forms the first insulation liner layer 206 on the sidewall 207 and bottom surface 205 of the first groove 204.In an embodiment of the present invention, the first insulation liner layer 206 can be oxide liner layer, and it can reduce the stress of epitaxial loayer 202, and can be used as the screen oxide (pre-implant oxide) of follow-up doping process, to reduce channelling effect.
Then, please refer to Fig. 3, carry out a doping process 208, will two the opposing sidewalls 207 respectively doped portion epitaxial loayer 202 of one first admixture along each the first groove 204 of the first conduction type be had, to form multiple first doped region 210.In an embodiment of the present invention, primarily of the width of the first groove 204 and the doping angle θ 1 of degree of depth decision doping process 208, such as can between 0 to 10 degree (°).In addition, in an embodiment of the present invention, and the first admixture can be and comprise phosphorus (the N-type admixture of P), Huo Arsenic (As).In an embodiment of the present invention, after carrying out doping process 208, can carry out a diffusion technology, its technological temperature is approximately 800 DEG C to 1500 DEG C, is uniformly distributed to make the first admixture in the first doped region 210.The conduction type carrying out the first doped region 210 after diffusion technology is N-type, and the dopant concentration of the first doped region 210 is greater than the dopant concentration of epitaxial loayer 202, and is less than the dopant concentration of semiconductor base 200.As shown in Figure 3, the first doped region 210 surrounds the first groove 204 substantially, and the degree of depth of the first doped region 210 is greater than the degree of depth of the first groove 204, and therefore the bottom surface of the first groove 204 is positioned at the first doped region 210.
Then, please refer to Fig. 4, a depositing operation of such as Low Pressure Chemical Vapor Deposition (LPCVD) can be carried out, or a coating process of such as spin-on-glass (SOG), one first insulating material 212 is inserted the first groove 204, and covers the first insulation liner layer 206.And then carry out a flatening process of such as chemical mechanical milling tech (CMP), remove the first insulating material 212 unnecessary on the end face 203 of epitaxial loayer 202.In an embodiment of the present invention, the first insulating material 212 can comprise oxidation material or non-impurity-doped polycrystalline silicon material, and the end face 213 of the first insulating material 212 carried out after flatening process aligns with the end face 203 of epitaxial loayer 202.
Refer again to Fig. 4, the generation type of the second groove 218 is then described, for convenience of description, only show second groove 218 in this example.But in other embodiments, the quantity of the second groove 218 can be two or more, determines according to element design.Such as low-pressure chemical vapor deposition (LPCVD) can be carried out and form a hard mask (Hard Mask), then a lithography process and Patternized technique is carried out, on the active region 300 of epitaxial loayer 202, cover a mask pattern (figure does not show), define the forming position of the second groove.In an embodiment of the present invention, the first groove and the second groove are crisscross arranged, and the meaning i.e. both sides of the second groove are adjacent first trenches respectively.But, then carry out an anisotropic etch process, remove the portion of epi layer 202 do not covered by mask pattern, to form the second groove 218 in the active region 300 of epitaxial loayer 202.In an embodiment of the present invention, the bottom surface 219 of the second groove 218 can the interface 201 of contact semiconductor substrate 200 and epitaxial loayer 202, or is positioned at epitaxial loayer 202 (meaning is namely close to interface 201).In an embodiment of the present invention, the first groove 204 and the second groove 218 can have identical width and the degree of depth, or according to element characteristic adjustment groove width and the degree of depth.
After removing above-mentioned mask pattern, then, carry out such as thermal oxidation (thermal oxidation) growth, compliance forms the second insulation liner layer 220 on the sidewall 221 and bottom surface 219 of the second groove 218.In an embodiment of the present invention, the second insulation liner layer 220 can be oxide liner layer, and it can reduce the stress of epitaxial loayer 202, and can be used as the screen oxide (pre-implant oxide) of follow-up doping process, to reduce channelling effect.
Then, please refer to Fig. 5, carry out a doping process 216, to two the opposing sidewalls 221 respectively doped portion epitaxial loayer 202 of one second admixture along each the second groove 218 of the second conduction type be had, to form multiple second doped regions 222 of the sidewall 221 of adjacent second groove 218 in active region 300.In an embodiment of the present invention, determine the doping angle θ 2 of the second doping process 216 primarily of the width of the second groove 218 and the degree of depth, such as can between 0 to 10 degree (°).In addition, in an embodiment of the present invention, and the second admixture can be the P type admixture comprising boron (B).In an embodiment of the present invention, after carrying out doping process 216, can carry out a diffusion technology, its technological temperature is approximately 800 DEG C to 1500 DEG C, to make the second admixture in the second doped region 222 be uniformly distributed, so that the conduction type of the second doped region 222 is reversed to P type.Therefore, the conduction type carrying out the second doped region 222 after diffusion technology is P type, and the dopant concentration of the second doped region 222 is greater than the dopant concentration of epitaxial loayer 202, and is less than the dopant concentration of semiconductor base 200.As shown in Figure 5, the second doped region 222 surrounds the second groove 218 substantially, and the degree of depth of the second doped region 222 is greater than the degree of depth of the second groove 218, and therefore the bottom surface of the second groove 218 is positioned at the second doped region 222.
Then, please refer to Fig. 6, a depositing operation of such as Low Pressure Chemical Vapor Deposition (LPCVD) can be carried out, or a coating process of such as spin-on-glass (SOG), one second insulating material 230 is inserted the second groove 218, and covers the second insulation liner layer 220.And then carry out a flatening process of such as chemical mechanical milling tech (CMP), remove the second insulating material 230 unnecessary on the end face 203 of epitaxial loayer 202.In an embodiment of the present invention, the second insulating material 230 can comprise oxidation material or non-impurity-doped polycrystalline silicon material, and the end face 213 of the second insulating material 230 carried out after flatening process aligns with the end face 203 of epitaxial loayer 202.Through above-mentioned technique, each first doped region 210 and conduction type that tool contrary adjacent one another are with second doped region 222, what thus form one embodiment of the invention one surpasses contact structure 250.In other embodiments, the first doped region 210 of super contact structure 250 and the conduction type of the second doped region 222 can exchange.
Fig. 6 to Fig. 7 to be illustrated on super contact structure 250 Production Example as the semiconductor element of rectilinear diffusion metal-oxide half field effect transistor (VDMOSFET).Then, please refer to Fig. 6, comprehensively on epitaxial loayer 202, sequentially form a grid oxic horizon (figure do not show) and a grid layer (scheming not show).In an embodiment of the present invention, such as thermal oxidation method (thermal oxidation), chemical vapour deposition technique (chemical vapordeposition can be utilized, CVD) or the thin film deposition mode such as atomic layer chemical vapor deposition method (atomic layer CVD, ALD) form grid oxic horizon.The thin film deposition modes such as such as chemical vapour deposition technique (CVD), physical vaporous deposition (PVD), atomic layer deposition method (ALD), sputtering method, galvanoplastic can be utilized to form grid layer.In an embodiment of the present invention, grid oxic horizon can comprise such as oxide (oxide), nitride (nitride), nitrogen oxide (oxynitride), oxycarbide (oxycarbide) or its combination.In an embodiment of the present invention, grid layer can be a polysilicon layer.Then, can on the active region 300 of epitaxial loayer 202 coverage diagram patterning photoresist layer (figure do not show), to define the forming position of gate oxidation layer pattern 224 as shown in Figure 6 and grid layer pattern 226, again with patterning photoresist layer for cover curtain, utilize anisotropic etching mode, remove partial gate oxide and grid layer, to form the multiple grid structures 228 be made up of gate oxidation layer pattern 224 and grid layer pattern 226 in active region 300.In an embodiment of the present invention, grid structure 228 covers the first groove 204 respectively and covers the portion of epi layer 202 of adjacent first trenches 204, and the second groove 218 comes out from grid structure 228.Afterwards, patterning photoresist layer is removed.As shown in Figure 6, the sidewall of grid structure 228 is positioned at the border of the first doped region 210, come out from the first doped region 210 in meaning and part first doped region 210.
Then, please refer to Fig. 6, grid structure 228 can be utilized for cover curtain, carry out one the 3rd doping process, in the active region 300 of the epitaxial loayer 202 do not covered by grid structure 228, form one first wellblock 232 with the second conduction type.As shown in Figure 6, the first wellblock 232 between two adjacent grid structures 228, and overlaps with the second groove 218 part.As shown in Figure 6, the first wellblock 232 can overlap with grid structure 228 part, and the first wellblock 232 is positioned at the top of the second doped region 222.In an embodiment of the present invention, first wellblock 232 can be considered a p type wells district 232, and the border on the first adjacent epitaxial layer 202 surface, wellblock 232 is positioned at the first doped region 210, and the first wellblock 232 conduction type being positioned at the first doped region 210 is reversed to P type.Afterwards, patterning photoresist layer (figure does not show) can be used to be cover curtain, to carry out a doping process, in the first wellblock 232, form plurality of source regions 234.In an embodiment of the present invention, the conduction type of the source area 234 in the first wellblock 232 is reversed to N-type, and the dopant concentration of source area 234 is greater than the dopant concentration of the first wellblock 232.As shown in Figure 6, a side of the adjacent different gate 228 of source area 234 difference.Further, two adjacent grid structures 228 share first wellblock 232, and therefore, two source areas 234 of above-mentioned two adjacent grid structures 228 are all formed in same first wellblock 232.The lower interface location that can adjust the first doped region 210 and the second doped region 222 according to element characteristic being positioned at source area 234 can be designed in first doped region 210 of each super contact structure 250 and the interface of the second doped region 222.In addition, N type semiconductor substrate 200 is considered as the drain finally forming rectilinear diffusion metal-oxide half field effect transistor (VDMOSFET).
Then, please refer to Fig. 7, a depositing operation of such as chemical vapour deposition technique (CVD) can be carried out, comprehensive formation one interlayer dielectric layer (ILD) 236, cover epitaxial loayer 202 and grid structure 228.Afterwards, can on interlayer dielectric layer (ILD) 236 coverage diagram patterning photoresist layer (figure do not show), to define the forming position of contact hole opening 238 as shown in Figure 7, again with patterning photoresist layer for cover curtain, utilize anisotropic etching mode, remove part interlayer dielectric layer 236, to form contact hole opening 238.As shown in Figure 7, the epitaxial loayer 202 in part first wellblock 232 between part source area 234 and source area 234 comes out from contact hole opening 238.
Then, refer again to Fig. 7, carry out a doping process, in the portion of epi layer 202 come out from contact hole opening 238, form multiple Wiring areas 240 with the second conduction type.In an embodiment of the present invention, the conduction type of Wiring area 240 is P type.As shown in Figure 7, the different sides 221 of adjacent second groove 218 of Wiring area 240 difference, and each Wiring area 240 is adjacent with a source area 234, and be positioned at the top of the second doped region 222.
Then, refer again to Fig. 7, a depositing operation of such as sputtering method can be carried out, comprehensive formation one electric conducting material, and insert contact hole opening 238, to form multiple contact hole plug 242.Through above-mentioned technique, completing is such as the semiconductor device 500 with super contact structure 250 of the embodiment of the present invention of rectilinear diffusion metal-oxide half field effect transistor (VDMOSFET).
The manufacture method of the semiconductor device 500 of the embodiment of the present invention is using N-type VDMOSFET as embodiment.But in other embodiments, above-mentioned first conduction type and the second conduction type can exchange, to form P type VDMOSFET.
The embodiment of the present invention provides a kind of semiconductor device 500 with super contact structure 250.The super contact structure 250 of the embodiment of the present invention etches formation one groove in a low-doped n type epitaxial loayer.Then, implant the N-type region territory of high dopant concentration (compared to N-type epitaxy layer) with low angle, backfill insulating material is after above-mentioned groove, then etching forms another groove.Afterwards, implant the territory, p type island region of high dopant concentration (compared to N-type epitaxy layer) with low angle, complete the super contact structure of P-N column.Compared to prior art, the super contact structure 250 of the embodiment of the present invention reaches effect of charge balance (charge balance) by the dopant concentration controlling N-type region territory and territory, p type island region.The dopant concentration that thus can reduce N-type epitaxy layer about can be down to about 1E14 ~ 4E13 from 2E15, can select required concentration according to element design.In addition, the super contact structure 250 of the embodiment of the present invention must not carry out extra epitaxy technique, thus can save process costs.Further, semiconductor element formed thereon can have less component size.
Although the present invention discloses as above with embodiment; so itself and be not used to limit the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is as the criterion when defining depending on accompanying claim.
Claims (12)
1. a manufacture method for semiconductor device, is characterized in that, the manufacture method of described semiconductor device comprises the following steps:
Semiconductor substrate is provided, there is one first conduction type;
On described semiconductor base, form an epitaxial loayer, there is described first conduction type;
Multiple first groove is formed in described epitaxial loayer;
Compliance forms multiple first insulation liner layer on the sidewall and bottom surface of described first groove;
Carry out one first doping process, by one first admixture with described first conduction type along described first groove described wall doping described in epitaxial loayer, to form multiple first doped region;
One first insulating material is inserted described first groove;
Multiple second groove is formed in described epitaxial loayer;
Compliance forms multiple second insulation liner layer on the sidewall and bottom surface of described second groove;
Carry out one second doping process, by one second admixture with one second conduction type along described second groove described wall doping described in epitaxial loayer, to form multiple second doped region;
One second insulating material is inserted described second groove; And
Form multiple grid structure, wherein said grid structure covers described first groove respectively and covers the described epitaxial loayer of part of adjacent described first groove, and the sidewall of wherein said grid structure is located within the border of described first doped region;
Described first groove is covered by described grid structure, and the bottom surface of described first groove is positioned at described first doped region.
2. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, described first conduction type is N-shaped, and described second conduction type is p-type.
3. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, the dopant concentration of described semiconductor base is greater than the dopant concentration of described epitaxial loayer.
4. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, more comprise after carrying out described first doping process and carry out one first diffusion technology, described first admixture is made to be uniformly distributed in the first doped region described in each, and more comprise after carrying out described second doping process and carry out one second diffusion technology, described second admixture is uniformly distributed in the second doped region described in each.
5. the manufacture method of semiconductor device as claimed in claim 4, it is characterized in that, the described epitaxial loayer being arranged in described first doped region has described first conduction type, and the described epitaxial loayer being wherein arranged in described second doped region has described second conduction type.
6. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, the described bottom surface of described first groove and described second groove is in described epitaxial loayer.
7. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, described first and second insulating material comprise oxidation material, and the end face of described first and second insulating material aligns with an end face of described epitaxial loayer.
8. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, described first groove and described second groove are crisscross arranged.
9. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, one of them of the first adjacent described second doped region, doped region described in each.
10. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, described first doped region and described second doped region are column.
The manufacture method of 11. semiconductor devices as claimed in claim 1, is characterized in that, the dopant concentration of described first doped region and described second doped region is greater than the dopant concentration of described epitaxial loayer.
The manufacture method of 12. semiconductor devices as claimed in claim 1, is characterized in that, comprises after described second insulating material is inserted described second groove:
In the described epitaxial loayer do not covered by described grid structure, form one first wellblock, there is described second conduction type;
In described first wellblock, form plurality of source regions, have described first conduction type, wherein said source area is adjacent described grid structure respectively;
Form an interlayer dielectric layer, cover described epitaxial loayer and described grid structure;
Remove the described interlayer dielectric layer of part, form a contact hole opening, the described epitaxial loayer of part of described second groove and adjacent described second groove comes out from described contact hole opening;
In the described epitaxial loayer of part come out from described contact hole opening, form multiple Wiring area, there is described second conduction type; And
One electric conducting material is inserted described contact hole opening, to form a contact hole plug.
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| CN115148601A (en) * | 2021-03-30 | 2022-10-04 | 无锡华润华晶微电子有限公司 | Semiconductor structure and preparation method thereof |
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| EP1872396A4 (en) * | 2005-04-22 | 2009-09-23 | Icemos Technology Corp | Superjunction device having oxide lined trenches and method for manufacturing a superjunction device having oxide lined trenches |
| JP2007087985A (en) * | 2005-09-20 | 2007-04-05 | Sanyo Electric Co Ltd | Insulated-gate semiconductor device and method of manufacturing same |
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