CN103137692A - 高压ldmos器件及其制造方法 - Google Patents

高压ldmos器件及其制造方法 Download PDF

Info

Publication number
CN103137692A
CN103137692A CN2011103944374A CN201110394437A CN103137692A CN 103137692 A CN103137692 A CN 103137692A CN 2011103944374 A CN2011103944374 A CN 2011103944374A CN 201110394437 A CN201110394437 A CN 201110394437A CN 103137692 A CN103137692 A CN 103137692A
Authority
CN
China
Prior art keywords
isolation structure
drift region
ldmos device
oxygen isolation
gate oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2011103944374A
Other languages
English (en)
Inventor
李亮
吴苑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Original Assignee
Shanghai Hua Hong NEC Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Hua Hong NEC Electronics Co Ltd filed Critical Shanghai Hua Hong NEC Electronics Co Ltd
Priority to CN2011103944374A priority Critical patent/CN103137692A/zh
Publication of CN103137692A publication Critical patent/CN103137692A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816Lateral DMOS transistors, i.e. LDMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642Isolation within the component, i.e. internal isolation
    • H01L29/0649Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823456MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明公开了一种高压LDMOS器件,在不影响原先整体布局且不增加任何成本的前提下,利用多晶硅栅极对轻掺杂漏区的电场调节作用,通过调整漂移区中的二氧化硅的形貌为m形,栅极为n形,减薄了多晶硅栅极一端下方的绝缘层厚度,从而增强了多晶硅栅极对轻掺杂漏区的电荷感应,使得表面耗尽区展宽,电场分布减弱,最终实现高压LDMOS器件源漏间耐压能力的提高。本发明还公开了所述高压LDMOS器件的制造方法,其可以与低压LDMOS器件一起制造,这种情况下完全兼容于现有工艺步骤,几乎不增加任何成本。

Description

高压LDMOS器件及其制造方法
技术领域
本发明涉及一种LDMOS(Laterally Diffused Metal OxideSemiconductor,横向扩散MOS晶体管)器件。
背景技术
请参阅图1,在硅衬底10上形成有多个LDMOS器件,每个LDMOS器件四周都被隔离结构11所包围,而与其他LDMOS器件相隔离。图1示意性地在其左半部分A显示了一种现有的高压LDMOS器件,在其右半部分B显示了一种现有的低压LDMOS器件。
每个LDMOS器件都是在硅衬底10中具有埋层12,埋层12之上为外延层10a,在外延层10a中具有阱区13和漂移区14。在隔离结构11之上、以及漂移区14的部分表面区域都具有二氧化硅15作为场氧隔离结构(或浅槽隔离结构)。高压LDMOS区域A的硅衬底10之上具有一层较厚的栅氧化层16。低压LDMOS区域B的硅衬底10之上具有一层较薄的栅氧化层17。每个LDMOS器件在栅氧化层16(或17)之上都具有多晶硅栅极21。多晶硅栅极21的一端在漂移区14中的二氧化硅15之上,另一端在阱区13之上的栅氧化层16(或17)之上。由于漂移区14中的二氧化硅15凸出于硅片表面,因此多晶硅栅极21都呈台阶状。漂移区14中且紧邻二氧化硅15远离多晶硅栅极21的一侧具有一个重掺杂区作为漏极23。阱区13中且在多晶硅栅极21的另一端外侧具有两个重掺杂区分别作为衬底引出区24和源极22。
高压LDMOS器件和低压LDMOS器件往往是在同一片硅片上一起生产制造。所述“高压”、“低压”并非指源漏极之间的耐压,而是针对栅极而言。图1所示的高压LDMOS器件和低压LDMOS器件一起制造的方法包括如下步骤:
第1步,请参阅图2a,硅片10上已通过隔离结构11完成了各个LDMOS器件之间的隔离,每个LDMOS器件的形成区域A(或B)中都已通过外延、离子注入、退火等工艺形成了外延层10a、埋层12、阱区13和漂移区14。所述埋层12在硅衬底10和外延层10a之间,而阱区13、漂移区14在外延层10a中。在隔离结构11的上方以及漂移区14的部分表面上有二氧化硅15作为场氧隔离结构(或浅槽隔离结构)。
第2步,请参阅图2b,在整个硅片热氧化生长一层二氧化硅16,该层二氧化硅16直接作为高压LDMOS区域A的厚栅氧化层。
二氧化硅15与二氧化硅16,在相接触的区域融为一体。但为清楚表明不同步骤制造,图2b中仍有分界,其余各幅图的处理方式与此相同。
第3步,请参阅图2c,采用光刻工艺,使光刻胶20覆盖高压LDMOS区域A,而低压LDMOS区域B未被光刻胶20覆盖。再采用刻蚀工艺,将低压LDMOS区域B中所氧化的二氧化硅16去除掉。这一步的刻蚀也可能会将二氧化硅15刻蚀掉一定的厚度。
第4步,请参阅图2d,在整个硅片表面暴露出硅的区域——就是低压LDMOS区域B中除二氧化硅15以外的区域,通过热氧化生长工艺形成一层二氧化硅17,该层二氧化硅17直接作为低压LDMOS区域B的薄栅氧化层。
第5步,请参阅图1,在每个LDMOS器件的形成区域A(或B)中,通过多晶硅淀积、光刻和刻蚀工艺在栅氧化层16(或17)之上形成多晶硅栅极21。并且多晶硅栅极21的一端在漂移区14的二氧化硅15之上,另一端在阱区13之上。通过离子注入、退火工艺在阱区13中形成源区22和衬底引出区24,在漂移区14中形成漏区23。
发明内容
本发明所要解决的技术问题是提供一种具有较高耐压能力的的高压LDMOS器件。为此,本发明还要提供所述高压LDMOS器件的制造方法。
为解决上述技术问题,本发明高压LDMOS器件包括有漂移区和栅极,在漂移区中具有二氧化硅作为场氧隔离结构或浅槽隔离结构;所述场氧隔离结构的上表面的中间部分具有一个下凹部;该场氧隔离结构因此横向分为第一端部、中间凹陷部和第二端部;所述栅极呈n形即中间高两边低;中间高的部分在所述场氧隔离结构的一个端部之上,一端低的部分在所述场氧隔离结构的中间凹陷部之上,另一端低的部分在栅氧化层之上。
所述高压LDMOS器件单独制造的方法包括如下步骤:
第1步,形成高压LDMOS器件的埋层、阱区、漂移区和场氧隔离结构或浅槽隔离结构,其中在漂移区的部分表面上具有一个场氧隔离结构或浅槽隔离结构;
第2步,在整个硅片热氧化生长一层二氧化硅作为高压LDMOS器件的栅氧化层;
第3步,采用光刻和刻蚀工艺,将漂移区中的场氧隔离结构的中间部分刻蚀掉一部分,形成一个下凹部;该漂移区中的场氧隔离结构因此横向分为第一端部、中间凹陷部和第二端部;
第4步,形成多晶硅栅极、源极、漏极和衬底引出区;其中多晶硅栅极呈n形即中间高两头低,中间高的部分在漂移区中的场氧隔离结构的一端部之上,一端低的部分在在漂移区中的场氧隔离结构的中间凹陷部之上,另一端低的部分在栅氧化层之上。
所述高压LDMOS器件与低压LDMOS器件一起制造的方法包括如下步骤:
第1步,硅片上已通过隔离结构完成了各个LDMOS器件之间的隔离,且已形成每个LDMOS器件的外延层、埋层、阱区、漂移区和场氧隔离结构或浅槽隔离结构;其中在漂移区的部分表面上具有一个场氧隔离结构或浅槽隔离结构;
第2步,在整个硅片热氧化生长一层二氧化硅作为高压LDMOS区域的栅氧化层;
第3步,采用光刻和刻蚀工艺,将高压LDMOS区域中漂移区中的场氧隔离结构的中间部分去除掉一部分、以及将低压LDMOS区域于第2步所氧化的二氧化硅全部去除掉;
第4步,在整个硅片表面暴露出硅的区域热氧化生长一层二氧化硅作为低压LDMOS区域的栅氧化层;
第5步,形成各个LDMOS器件的多晶硅栅极、源极、漏极和衬底引出区;其中高压LDMOS区域中的多晶硅栅极呈n形即中间高两头低,中间高的部分在漂移区中的场氧隔离结构的一端部之上,一端低的部分在在漂移区中的场氧隔离结构的中间凹陷部之上,另一端低的部分在栅氧化层之上。
本发明高压LDMOS器件在不影响原先整体布局且不增加任何成本的前提下,利用多晶硅栅极对轻掺杂漏区的电场调节作用,通过调整漂移区之上的二氧化硅的形貌(m形)和栅极的形貌(n形),减薄了多晶硅栅极一端下方的绝缘层厚度,从而增强了多晶硅栅极对漂移区的电荷感应,使得表面耗尽区展宽,电场分布减弱,最终实现高压LDMOS器件源漏间耐压能力的提高。
本发明高压LDMOS器件可以与低压LDMOS器件一起制造,这种情况下完全兼容于现有工艺步骤,几乎不增加任何成本。
本发明高压LDMOS器件也可以单独制造,从而满足各种其他需要。
附图说明
图1是现有的高压LDMOS器件的剖面图;
图2a~图2d是现有的高压LDMOS器件和低压LDMOS器件一起制造的各步骤剖面图;
图3是本发明高压LDMOS器件的剖面图;
图4a~图4b是本发明高压LDMOS器件和低压LDMOS器件一起制造的各步骤剖面图。
图中附图标记说明:
10为硅衬底;10a为外延层;11为隔离结构;12为埋层;13为阱区;14为漂移区;15为二氧化硅(场氧隔离结构、或浅槽隔离结构);16为厚栅氧化层;17为薄栅氧化层;20为光刻胶;21为多晶硅栅极;22为源极;23为漏极;24为衬底引出区;A为高压LDMOS区域;B为低压LDMOS区域。
具体实施方式
请参阅图3,在硅衬底10上形成有多个LDMOS器件,每个LDMOS器件四周都被隔离结构11所包围,而与其他LDMOS器件相隔离。图3示意性地在其左半部分A显示了本发明高压LDMOS器件,在其右半部分B显示的仍为现有的低压LDMOS器件。此处所述“高压”、“低压”并非指源漏极之间的耐压,而是针对栅极而言。
本发明高压LDMOS器件是在高压LDMOS区域A内形成的,具体结构包括:在硅衬底10中具有埋层12,埋层12之上为外延层10a。在外延层10a中具有阱区13和漂移区14。在隔离结构11之上具有二氧化硅15a,在漂移区14的部分表面之上具有二氧化硅15b,均作为场氧隔离结构(或浅槽隔离结构)。其中在二氧化硅15b的上表面的中间部分具有一个下凹部。这样该二氧化硅15b横向可分为正常厚度的第一端部、小于正常厚度的中间凹陷部、正常厚度的第二端部。在硅衬底10之上具有一层栅氧化层16。在栅氧化层16和二氧化硅15b之上为多晶硅栅极21,多晶硅栅极21大致呈n形,即中间高两边低。多晶硅栅极21中间高的部分在二氧化硅15b的第一端部之上,一端低的部分在二氧化硅15b的中间凹陷部之上,另一端低的部分在阱区13之上的栅氧化层16之上。漂移区14中且紧邻二氧化硅15b远离多晶硅栅极21的那一侧具有一个重掺杂区作为漏极23。阱区13中且在多晶硅栅极21的另一端外侧具有两个重掺杂区分别作为衬底引出区24和源极22。
图3所示的本发明高压LDMOS器件中,漂移区14中的二氧化硅15b的第一端部和第二端部的宽度优选为0.4μm。
在漂移区之上的二氧化硅包括栅氧化层16,还包括场氧隔离结构(或浅槽隔离结构)15b,由于两者为同一材质实际上是融为一体的。高压LDMOS器件的漂移区上方的二氧化硅呈m形,即横向分为栅氧化层(最低)、场氧隔离结构的第一端部(最高)、场氧隔离结构的中间凹陷部、场氧隔离结构的第二端部(最高)、栅氧化层(最低)。这种特殊的形貌增强了其上形成的n形多晶硅栅极21对漂移区14的电荷感应,从而实现了本发明高压LDMOS器件的源漏耐压能力的提高,比相同尺寸的现有LDMOS器件可提高1~5V的崩溃电压。
图3所示的本发明高压LDMOS器件可以单独制造,也可以和低压LDMOS器件一起制造,后者更为经济,其具体包括如下步骤:
第1步,请参阅图2a,硅片10上已通过隔离结构11完成了各个LDMOS器件之间的隔离,每个LDMOS器件的形成区域A(或B)中都已通过外延、离子注入、退火等工艺形成了外延层10a、埋层12、阱区13和漂移区14。所述埋层12在硅衬底10和外延层10a之间,而阱区13、漂移区14在外延层10a中。在隔离结构11的上方以及漂移区14的部分表面上有二氧化硅15作为场氧隔离结构(或浅槽隔离结构)。
第2步,请参阅图2b,在整个硅片热氧化生长一层二氧化硅16,该层二氧化硅16作为高压LDMOS区域A的厚栅氧化层。这一步可能也会使漂移区14中的二氧化硅15b的厚度略有增加,但几乎不明显。
第3步,请参阅图4a,采用光刻工艺,使光刻胶20覆盖高压LDMOS区域A,但暴露出高压LDMOS区域A中漂移区14中的二氧化硅15b的中间部分,而低压LDMOS区域B完全未被光刻胶20覆盖。再采用刻蚀工艺,将高压LDMOS区域A中漂移区14中的二氧化硅15b的中间部分、以及低压LDMOS区域B中所氧化的二氧化硅16去除掉。从而在二氧化硅15b的上表面形成一个下凹部。该二氧化硅15b也由此横向分为正常厚度的第一端部、小于正常厚度的中间凹陷部、正常厚度的第二端部。
之所以保留二氧化硅15b的第一端部、第二端部,是由于光刻胶20必须完全保护厚栅氧化层16不被刻蚀,因而边界必须超出到二氧化硅15b一部分所致。具体边界超出多少,取决于光刻工艺的套刻精度。
优选地,二氧化硅15b的上表面被刻蚀掉的厚度约为厚栅氧化层16的两倍,例如为
Figure BDA0000115334790000081
第4步,请参阅图4b,在整个硅片表面暴露出硅的区域——就是低压LDMOS区域B中的外延层10a的表面,通过热氧化生长工艺形成一层二氧化硅17,该层二氧化硅17直接作为低压LDMOS区域B的薄栅氧化层。
第5步,请参阅图3,在每个LDMOS器件的形成区域A(或B)中,通过多晶硅淀积、光刻和刻蚀工艺在栅氧化层16(或17)之上形成多晶硅栅极21。对高压LDMOS区域A而言,多晶硅栅极21的一端在漂移区14中的二氧化硅15b的中间凹陷部之上,另一端在阱区13之上的栅氧化层16之上,大致呈中间高、两头低的n形。对低压LDMOS区域B而言,多晶硅栅极仍呈台阶状。通过离子注入、退火工艺在阱区13中形成源区22和衬底引出区24,在漂移区14中形成漏区23。
上述方法的第3步中,优选采用湿法腐蚀工艺将漂移区中的场氧隔离结构的中间部分刻蚀掉一部分,同时将低压LDMOS区域于第2步所氧化的二氧化硅全部去除掉。
图3所示的本发明高压LDMOS器件如果单独制造,只需将上述方法各步骤中涉及低压LDMOS区域B的内容去除,再删除第4步即可。此时在所述方法第3步中,可采用干法刻蚀或湿法腐蚀工艺将漂移区中的场氧隔离结构的中间部分刻蚀掉一部分。
上述方法各步骤中,只对具有创新性的内容进行了详细描述,其余各种结构的制造工艺均为现有技术,不再赘述。
以上仅为本发明的优选实施例,并不用于限定本发明。对于本领域的技术人员来说,本发明可以有各种更改和变化。凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。

Claims (8)

1.一种高压LDMOS器件,包括漂移区和栅极,在漂移区中具有二氧化硅作为场氧隔离结构或浅槽隔离结构;其特征是,所述场氧隔离结构的上表面的中间部分具有一个下凹部;该场氧隔离结构因此横向分为第一端部、中间凹陷部和第二端部;所述栅极呈n形即中间高两边低;中间高的部分在所述场氧隔离结构的一个端部之上,一端低的部分在所述场氧隔离结构的中间凹陷部之上,另一端低的部分在栅氧化层之上。
2.根据权利要求1所述的高压LDMOS器件,其特征是,在漂移区之上的二氧化硅包括栅氧化层,还包括场氧隔离结构或浅槽隔离结构;所述漂移区之上的二氧化硅呈m形即横向分为栅氧化层、场氧隔离结构的第一端部、场氧隔离结构的中间凹陷部、场氧隔离结构的第二端部、栅氧化层。
3.根据权利要求1所述的高压LDMOS器件,其特征是,所述场氧隔离结构的第一端部、第二端部的宽度均为0.4μm。
4.如权利要求1所述的高压LDMOS器件单独制造的方法,其特征是,包括如下步骤:
第1步,形成高压LDMOS器件的埋层、阱区、漂移区和场氧隔离结构或浅槽隔离结构,其中在漂移区的部分表面上具有一个场氧隔离结构或浅槽隔离结构;
第2步,在整个硅片氧化一层二氧化硅作为高压LDMOS器件的栅氧化层;
第3步,采用光刻和刻蚀工艺,将漂移区中的场氧隔离结构的中间部分刻蚀掉一部分,形成一个下凹部;该漂移区中的场氧隔离结构因此横向分为第一端部、中间凹陷部和第二端部;
第4步,形成多晶硅栅极、源极、漏极和衬底引出区;其中多晶硅栅极呈n形即中间高两头低,中间高的部分在漂移区中的场氧隔离结构的一端部之上,一端低的部分在在漂移区中的场氧隔离结构的中间凹陷部之上,另一端低的部分在栅氧化层之上。
5.根据权利要求4所述的高压LDMOS器件单独制造的方法,其特征是,所述方法第3步中,漂移区中的场氧隔离结构的中间部分刻蚀掉的厚度为第2步所氧化的栅氧化层的两倍厚度。
6.如权利要求1所述的高压LDMOS器件与低压LDMOS器件一起制造的方法,其特征是,包括如下步骤:
第1步,硅片上已通过隔离结构完成了各个LDMOS器件之间的隔离,且已形成每个LDMOS器件的外延层、埋层、阱区、漂移区和场氧隔离结构或浅槽隔离结构;其中在漂移区的部分表面上具有一个场氧隔离结构或浅槽隔离结构;
第2步,在整个硅片热氧化生长一层二氧化硅作为高压LDMOS区域的栅氧化层;
第3步,采用光刻和刻蚀工艺,将高压LDMOS区域中漂移区中的场氧隔离结构的中间部分去除掉一部分、以及将低压LDMOS区域于第2步所氧化的二氧化硅全部去除掉;
第4步,在整个硅片表面暴露出硅的区域热氧化生长一层二氧化硅作为低压LDMOS区域的栅氧化层;
第5步,形成各个LDMOS器件的多晶硅栅极、源极、漏极和衬底引出区;其中高压LDMOS区域中的多晶硅栅极呈n形即中间高两头低,中间高的部分在漂移区中的场氧隔离结构的一端部之上,一端低的部分在在漂移区中的场氧隔离结构的中间凹陷部之上,另一端低的部分在栅氧化层之上。
7.根据权利要求6所述的高压LDMOS器件与低压LDMOS器件一起制造的方法,其特征是,所述方法第3步中,漂移区中的场氧隔离结构的中间部分刻蚀掉的厚度为第2步所氧化的栅氧化层的两倍厚度。
8.根据权利要求6所述的高压LDMOS器件与低压LDMOS器件一起制造的方法,其特征是,所述方法第3步中,采用湿法腐蚀工艺将漂移区中的场氧隔离结构的中间部分刻蚀掉一部分,同时将低压LDMOS区域于第2步所氧化的二氧化硅全部去除掉。
CN2011103944374A 2011-12-02 2011-12-02 高压ldmos器件及其制造方法 Pending CN103137692A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2011103944374A CN103137692A (zh) 2011-12-02 2011-12-02 高压ldmos器件及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2011103944374A CN103137692A (zh) 2011-12-02 2011-12-02 高压ldmos器件及其制造方法

Publications (1)

Publication Number Publication Date
CN103137692A true CN103137692A (zh) 2013-06-05

Family

ID=48497276

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011103944374A Pending CN103137692A (zh) 2011-12-02 2011-12-02 高压ldmos器件及其制造方法

Country Status (1)

Country Link
CN (1) CN103137692A (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104795325A (zh) * 2014-01-17 2015-07-22 北大方正集团有限公司 场效应管的制造方法
EP3255678A1 (en) * 2016-06-12 2017-12-13 Semiconductor Manufacturing International Corporation (Shanghai) Semiconductor device and fabrication method thereof
CN108242467A (zh) * 2016-12-27 2018-07-03 无锡华润上华科技有限公司 Ldmos器件及其制作方法
CN109148304A (zh) * 2018-09-04 2019-01-04 盛世瑶兰(深圳)科技有限公司 一种晶体管及其制作方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101572270A (zh) * 2008-05-02 2009-11-04 台湾积体电路制造股份有限公司 金属氧化物半导体晶体管
CN101728392A (zh) * 2008-10-22 2010-06-09 台湾积体电路制造股份有限公司 具有减少的导通电阻的高压器件
CN102254947A (zh) * 2010-05-21 2011-11-23 松下电器产业株式会社 半导体装置及其制造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101572270A (zh) * 2008-05-02 2009-11-04 台湾积体电路制造股份有限公司 金属氧化物半导体晶体管
CN101728392A (zh) * 2008-10-22 2010-06-09 台湾积体电路制造股份有限公司 具有减少的导通电阻的高压器件
CN102254947A (zh) * 2010-05-21 2011-11-23 松下电器产业株式会社 半导体装置及其制造方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104795325A (zh) * 2014-01-17 2015-07-22 北大方正集团有限公司 场效应管的制造方法
EP3255678A1 (en) * 2016-06-12 2017-12-13 Semiconductor Manufacturing International Corporation (Shanghai) Semiconductor device and fabrication method thereof
CN107492495A (zh) * 2016-06-12 2017-12-19 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US10411115B2 (en) 2016-06-12 2019-09-10 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor device including a recessed insulation region and fabrication method thereof
CN108242467A (zh) * 2016-12-27 2018-07-03 无锡华润上华科技有限公司 Ldmos器件及其制作方法
WO2018121132A1 (zh) * 2016-12-27 2018-07-05 无锡华润上华科技有限公司 Ldmos器件及其制作方法
CN109148304A (zh) * 2018-09-04 2019-01-04 盛世瑶兰(深圳)科技有限公司 一种晶体管及其制作方法

Similar Documents

Publication Publication Date Title
US8759912B2 (en) High-voltage transistor device
KR101962834B1 (ko) 반도체 초접합 전력 소자 및 그 제조방법
CN107180871B (zh) 半导体器件
CN103681848B (zh) 金属氧化物半导体场效应晶体管及其制造方法
JP6198292B2 (ja) 半導体装置および半導体装置の製造方法
CN100524820C (zh) 横向双扩散金属氧化物半导体ldmos元件及其加工方法
CN102769037A (zh) 减少表面电场的结构及横向扩散金氧半导体元件
US8836067B2 (en) Transistor device and manufacturing method thereof
US10236375B2 (en) High voltage metal oxide semiconductor device and manufacturing method thereof
US8896057B1 (en) Semiconductor structure and method for manufacturing the same
CN103137692A (zh) 高压ldmos器件及其制造方法
CN104377244A (zh) 一种降低ldmos导通电阻的器件结构
CN104051320B (zh) 半导体元件的制造方法
KR20140112629A (ko) Ldmos 소자와 그 제조 방법
CN104576732B (zh) 一种寄生FinFET的横向双扩散半导体器件
TWI601295B (zh) 斷閘極金氧半場效電晶體
CN106298923B (zh) 高压金属氧化物半导体晶体管元件以及其制造方法
CN110867443B (zh) 半导体功率器件
KR100947941B1 (ko) 반도체 소자 및 그 제조방법
CN102751326A (zh) 功率横向双扩散金氧半导体元件及高压元件
US8569134B2 (en) Method to fabricate a closed cell trench power MOSFET structure
CN101916783A (zh) 一种凹陷沟道的横向和纵向扩散型场效应晶体管及其制造方法
US7074658B2 (en) Structure for an LDMOS transistor and fabrication method for thereof
CN202205758U (zh) 对称高压mos器件
US10622440B2 (en) High voltage metal oxide semiconductor device and manufacturing method thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
ASS Succession or assignment of patent right

Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING

Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI

Effective date: 20140115

C41 Transfer of patent application or patent right or utility model
COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI

TA01 Transfer of patent application right

Effective date of registration: 20140115

Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399

Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation

Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge

Applicant before: Shanghai Huahong NEC Electronics Co., Ltd.

C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20130605