CN106298923B - 高压金属氧化物半导体晶体管元件以及其制造方法 - Google Patents

高压金属氧化物半导体晶体管元件以及其制造方法 Download PDF

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CN106298923B
CN106298923B CN201510294231.2A CN201510294231A CN106298923B CN 106298923 B CN106298923 B CN 106298923B CN 201510294231 A CN201510294231 A CN 201510294231A CN 106298923 B CN106298923 B CN 106298923B
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gate structure
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semiconductor substrate
drift region
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萧世楹
游焜煌
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United Microelectronics Corp
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Abstract

本发明公开一种高压金属氧化物半导体晶体管元件以及其制造方法。上述制造方法包括下列步骤。在半导体基底上形成栅极结构，半导体基底具有第一区和第二区，第一区位于栅极结构的第一部的一侧，而第二区位于栅极结构的第二部的一侧。在半导体基底和栅极结构上形成图案化掩模层，图案化掩模层覆盖半导体基底的第一区和栅极结构的第一部，栅极结构的第二部暴露于图案化掩模层之外。进行一注入制作工艺，用以于第二区中形成一漂移区域。进行一蚀刻制作工艺，用以移除部分的未被图案化掩模层覆盖的栅极结构的第二部。在蚀刻制作工艺之后，第二部的厚度小于第一部的厚度。

Description

高压金属氧化物半导体晶体管元件以及其制造方法
技术领域
本发明涉及一种高压金属氧化物半导体晶体管元件以及其制造方法，尤其是涉及一种具有降低寄生电容效果的高压金属氧化物半导体晶体管元件以及其制造方法。
背景技术
在具有高压处理能力的功率元件中，双扩散金属氧化物半导体 (double-diffused MOS，DMOS)晶体管元件持续受到重视。常见的DMOS晶体管元件有垂直双扩散金属氧化物半导体(vertical double-diffused MOS，VDMOS)与横向双扩散金属氧化物半导体(LDMOS)晶体管元件。而LDMOS 晶体管元件因具有较高的操作频宽与操作效率，以及易与其他集成电路整合的平面结构，现已广泛地应用于高电压操作环境中，如中央处理器电源供应 (CPU power supply)、电源管理***(power management system)、直流/交流转换器(AC/DC converter)以及高功率或高频段的功率放大器等等。LDMOS晶体管元件主要的特征为利用设置具有低掺杂浓度、大面积的横向扩散漂移区域来缓和源极端与漏极端之间的高电压，因此可使LDMOS晶体管元件获得较高的击穿电压(breakdown voltage)。在漏极延伸型金属氧化物半导体(drain extending MOS，DEMOS)晶体管中，漂移区域设置于栅极与漏极之间，漏极与栅极之间的寄生电容会造成元件操作时的负面影响。举例来说，当用于功率放大器时，功率附加效率(power added efficiency，PAE)会因为较大的栅极漏极电容而降低，故有必要经由结构设计来减小栅极与漏极之间的寄生电容。
发明内容
本发明的目的在于提供了一种高压金属氧化物半导体(high voltage metal-oxide-semiconductor，HV MOS)晶体管元件以及其制造方法，利用蚀刻制作工艺移除部分的靠近漂移区域的栅极结构，由此降低栅极与漏极之间的寄生电容。
为达上述目的，根据本发明的一实施例，本发明提供了一种高压金属氧化物半导体晶体管元件的制造方法，包括下列步骤。首先，提供一半导体基底。在半导体基底上形成一栅极结构，栅极结构包括一第一部以及一第二部，半导体基底具有一第一区以及一第二区，第一区位于栅极结构的第一部的一侧，而第二区位于栅极结构的第二部的一侧。然后，在半导体基底以及栅极结构上形成一图案化掩模层，图案化掩模层覆盖半导体基底的第一区以及栅极结构的第一部，且栅极结构的第二部暴露于图案化掩模层之外。进行一注入制作工艺，用以于第二区中形成一漂移区域。进行一蚀刻制作工艺，用以移除部分的未被图案化掩模层覆盖的栅极结构的第二部。在蚀刻制作工艺之后，第二部的厚度小于第一部的厚度。
根据本发明的一实施例，本发明还提供了一种高压金属氧化物半导体晶体管元件，包括一半导体基底、一栅极结构以及一漂移区域。栅极结构设置于半导体基底上，栅极结构包括一第一部以及一第二部，第二部的厚度小于第一部的厚度。漂移区域设置于栅极结构的第二部的一侧。
通过本发明所提供的高压金属氧化物半导体晶体管元件的制造方法，栅极结构于靠近漂移区域的部分可具有较小的厚度，由此可在较不影响晶体管元件的其他元件特性的状况下达到降低栅极与漏极之间寄生电容的效果。
附图说明
图1与图2为本发明第一实施例的高压金属氧化物半导体晶体管元件的制造方法示意图；
图3与图4为本发明第二实施例的高压金属氧化物半导体晶体管元件的制造方法示意图；
图5与图6为本发明第三实施例的高压金属氧化物半导体晶体管元件的制造方法示意图；
图7与图8为本发明第四实施例的高压金属氧化物半导体晶体管元件的制造方法示意图。
主要元件符号说明
10 半导体基底
11 漂移区域
11A 第三部
11B 第四部
12 轻掺杂区
13 源极区
14 漏极区
20 栅极介电层
30 栅极结构
30A 第一部
30B 第二部
40 图案化掩模层
50 层间介电层
91 注入制作工艺
92 蚀刻制作工艺
100 高压金属氧化物半导体晶体管元件
200 高压金属氧化物半导体晶体管元件
300 高压金属氧化物半导体晶体管元件
D1 第一方向
D2 第二方向
H1 第一厚度
H2 第二厚度
R1 第一区
R2 第二区
S1 第一侧表面
S2 第二侧表面
S3 第三侧表面
SP 间隙壁
SP1 第一间隙壁
SP2 第二间隙壁
SP3 第三间隙壁
T1 第一上表面
T2 第二上表面
T3 第三上表面
T4 第四上表面
具体实施方式
请参阅图1与图2。图1与图2所绘示为本发明第一实施例的高压金属氧化物半导体晶体管元件的制造方法示意图。本实施例的高压金属氧化物半导体晶体管元件的制造方法包括下列步骤。首先，如图1所示，提供一半导体基底10，并于半导体基底10上形成一栅极结构30。本实施例的半导体基底10可包括硅基底(silicon substrate)、外延硅基底(epitaxial silicon substrate)、硅锗半导体基底(silicon germanium substrate)、碳化硅基底(silicon carbide substrate)或硅覆绝缘(silicon-on-insulator,SOI)基底等，但并不以此为限。本实施例的栅极结构30可包括多晶硅栅极、金属栅极或其他适合的材料所形成的栅极结构。此外，一栅极介电层20可形成于半导体基底10上并至少部分位于栅极结构30与半导体基底10之间。栅极结构30包括一第一部30A 以及一第二部30B，半导体基底10具有一第一区R1以及一第二区R2，第一区R1位于栅极结构30的第一部30A的一侧，而第二区R2位于栅极结构 30的第二部30B的一侧。更明确地说，栅极结构30的第一部30A与第二部 30B为于一水平的第一方向D1上彼此直接接触且相连的区块，故第一部30A 与第二部30B两者的上表面等高且互相对齐，且第一部30A与第二部30B 两者的下表面也等高且互相对齐。第一区R1与第二区R2于第一方向D1上分别位于栅极结构30的两侧，且第一区R1与第二区R2分别对应后续要形成的源极区与漏极区，但并不以此为限。
然后，在半导体基底10以及栅极结构30上形成一图案化掩模层40。本实施例的图案化掩模层40可包括光致抗蚀剂、绝缘材料或其他适合的掩模材料。图案化掩模层40覆盖半导体基底10的第一区R1以及栅极结构30的第一部30A，且栅极结构30的第二部30B以及半导体基底10的第二区R2 暴露于图案化掩模层40之外。换句话说，本实施例的图案化掩模层40并未覆盖栅极结构30的第二部30B与半导体基底10的第二区R2，但本发明并不以此为限。接着，进行一注入制作工艺91，用以于第二区R2中形成一漂移区域11。由于进行注入制作工艺91时，图案化掩模层40并未覆盖栅极结构30中靠近第二区R2的第二部30B，故可以自对准(self-aligned)的方式于栅极结构30的第二部30B的一侧形成漂移区域11。在本实施例中，半导体基底10优选具有一第一导电型态或包括有一第一导电型态的区域，而漂移区域11优选具有第二导电型态，而第二导电型态与第一导电型态互补 (complementary)。举例来说，本实施例中第一导电型态可为p型，第二导电型态可为n型，但并不以此为限。换句话说，半导体基底10可为p型半导体基底或具有p型阱的半导体基底，而漂移区域11可为n型阱，但并不以此为限。此外，本实施例的注入制作工艺91优选可为一具有一定倾斜角度的注入制作工艺，由此使漂移区域11于一垂直的第二方向D2上与栅极结构 30部分重叠，但并不以此为限。
如图1至图2所示，本实施例的制造方法可还包括移除图案化掩模层40 并形成一轻掺杂区12、一源极区13、一漏极区14以及间隙壁(sidewall spacer)SP，由此形成如图2所示的高压金属氧化物半导体(high voltage metal-oxide-semiconductor，HV MOS)晶体管元件100。轻掺杂区12与源极区13形成于第一区R1中，且轻掺杂区12位于源极区13与栅极结构30之间。漏极区14形成于漂移区域11中，而间隙壁SP形成于栅极结构30的侧表面上。源极区13的边缘可与对应的间隙壁SP的边缘切齐，而漏极区14 可利用另一图案化掩模定义，以使得漏极区14可较远离对应的间隙壁SP，但并不以此为限。在本实施例中，当半导体基底10为p型半导体基底或具有p型阱的半导体基底且漂移区域11为n型阱时，源极区13与漏极区14 优选可分别为一n型掺杂区，而轻掺杂区12优选可为一n型轻掺杂区，但并不以此为限。
下文将针对本发明的不同实施例进行说明，且为简化说明，以下说明主要针对各实施例不同的部分进行详述，而不再对相同的部分作重复赘述。此外，本发明的各实施例中相同的元件以相同的标号进行标示，用以方便在各实施例间互相对照。
请参阅图3与图4并请一并参考图1。图3与图4所绘示为本发明第二实施例的高压金属氧化物半导体晶体管元件的制造方法示意图。如图3与图 4所示，与上述第一实施例不同的地方在于，本实施例的制造方法还包括于图1所示的注入制作工艺91之后，进行一蚀刻制作工艺92，用以移除部分的未被图案化掩模层40覆盖的栅极结构30的第二部30B。值得说明的是，蚀刻制作工艺92并未完全移除栅极结构30的第二部30B，而仅对栅极结构 30的第二部30B进行部分蚀刻，由此降低栅极结构30的第二部30B的厚度。在蚀刻制作工艺92进行时，栅极结构30的第一部30A被图案化掩模层40 覆盖而不会被蚀刻，故栅极结构30的第一部30A可维持原有的高度。换句话说，在蚀刻制作工艺92之后，栅极结构30的第二部30B的第二厚度H2 小于栅极结构30的第一部30A的第一厚度H1，且第二部30B的第二上表面T2会低于第一部30A的第一上表面T1。此外，在蚀刻制作工艺92之后，栅极结构30的第一部30A的一第一侧表面S1与第二部30B的第二上表面 T2直接相连。因此，上述的相连的第一上表面T1、第一侧表面S1以及第二上表面T2于栅极结构30靠近第二区R2以及漂移区域11的一侧形成阶梯状的缺口，由此降低栅极结构30与后续形成于漂移区域11的漏极区(图3未绘示)之间于水平的第一方向D1上的边缘电容(fringing capacitance)。
此外，如图3所示，本实施例的图案化掩模层40并未覆盖半导体基底 10的第二区R2，因此于蚀刻制作工艺92时，一部分的漂移区域11被蚀刻制作工艺92移除。更明确地说，本实施例的蚀刻制作工艺92可通过控制制作工艺时间而使得蚀刻动作停止在栅极结构30以及漂移区域11中，换句话说可控制蚀刻栅极结构30以及漂移区域11的深度来避免于蚀刻制作工艺92 中暴露出的栅极结构30与漂移区域11被完全移除。在本实施例中，可视栅极结构30的厚度设计来决定蚀刻制作工艺92对栅极结构30的蚀刻深度，并控制蚀刻深度的偏移范围，由此维持后续形成的晶体管元件的电性状况与均匀性。
更进一步说明，本实施例的漂移区域11可包括互相接触且连接的一第三部11A以及一第四部11B，栅极结构30覆盖漂移区域11的第三部11A，且漂移区域11的第四部11B未被栅极结构30覆盖而暴露于栅极结构30之外。因此，在蚀刻制作工艺92之后，漂移区域11的第四部11B的一第四上表面T4低于第三部11A的一第三上表面T3，且第三部11A的一第三侧表面S3与第四部11B的第四上表面T4相连。本实施例的蚀刻制作工艺92优选为一各向异性(anisotropic)蚀刻制作工艺，由此避免漂移区域11的第三部 11A被蚀刻而影响到漂移区域11与栅极结构30之间的电性状况。因此，栅极结构30的第二部30B的一第二侧表面S2优选与漂移区域11的第三部11A 的第三侧表面S3大体上切齐，但并不以此为限。上述的第一上表面T1、第一侧表面S1、第二上表面T2、第二侧表面S2、第三侧表面S3以及第四上表面T4也于第二区R2以及栅极结构30靠近第二区R2的一侧形成阶梯状的缺口。此外，由于本实施例的蚀刻制作工艺92利用图案化掩模层40进行，故不需额外的黄光制作工艺，由此可减少对于制造成本的影响。值得说明的是，在本发明的其他实施例中，虽然图案化掩模层40未覆盖半导体基底10 的第二区R2，但仍可通过调整蚀刻制作工艺92的制作工艺参数以及蚀刻选择比使得蚀刻制作工艺92在第二区R2停止在第二区R2的栅极介电层20 上而未蚀刻第二区R2的半导体基底10。
接着，如图3至图4所示，本实施例的制造方法可还包括移除图案化掩模层40并形成轻掺杂区12、源极区13、漏极区14以及间隙壁SP，由此形成如图4所示的高压金属氧化物半导体晶体管元件200。与上述第一实施例不同的地方在于，由于本实施例的部分的栅极结构30与部分的漂移区域11 被蚀刻制作工艺移除，故间隙壁SP的形成位置上会有所不同。举例来说，本实施例的间隙壁SP可包括一第一间隙壁SP1、一第二间隙壁SP2以及一第三间隙壁SP3。第一间隙壁SP1形成于栅极结构30的第一部30A的靠近第一区R1的一第一侧表面S1上。第二间隙壁SP2形成于第一部30A的靠近第二区R2的另一第一侧表面S1以及第二部30B的第二上表面T2上。第三间隙壁SP3形成于第二部30B的第二侧表面S2、漂移区域11的第三部11A 的第三侧表面S3以及漂移区域11的第四部11B的第四上表面T4上。并且从图4可知，第一间隙壁SP1、第二间隙壁SP2与第三间隙壁SP3互相分离。此外，本实施例的制造方法可还包括形成一层间介电层50覆盖栅极结构30、漂移区域11、源极区13以及漏极区14，并可于层间介电层50中形成分别与栅极结构30、源极区13以及漏极区14连接的导电插塞(未图示)，但并不以此为限。
如图4所示，本实施例的高压金属氧化物半导体晶体管元件200包括半导体基底10、栅极结构30以及漂移区域11。栅极结构30设置于半导体基底10上，栅极结构30包括第一部30A以及第二部30B，第二部30B的厚度小于第一部30A的厚度，且漂移区域11设置于栅极结构30的第二部30B 的一侧。栅极结构30的第一部30A的第一上表面T1与栅极结构30的第二部30B的第二上表面T2不共平面(not coplanar)。此外，高压金属氧化物半导体晶体管元件200还包括源极区13以及漏极区14。源极区13与漏极区14分别设置于半导体基底10中，源极区13设置于与栅极结构30的第一部 30A相邻的一侧，且至少部分的漏极区14设置于漂移区域11中。此外，高压金属氧化物半导体晶体管元件200还包括多个间隙壁SP设置于栅极结构 30的第一部30A的第一侧表面S1上以及第二部30B的第二侧表面S2上。此外，其中一间隙壁SP(第三间隙壁SP3)设置于漂移区域11的第三部11A 的第三侧表面S3上以及栅极结构30的第二部30B的第二侧表面S2上。
在本实施例中，源极区13的一上表面与漏极区14的一上表面不共平面，但并不以此为限。由于本实施例的栅极结构30的第二部30B以及漂移区域 11的第四部11B被部分蚀刻而于第二区R2以及栅极结构30靠近第二区R2 的一侧形成阶梯状的缺口，故可降低栅极结构30与漏极区14之间于水平的第一方向D1上的边缘电容，并进而达到使高压金属氧化物半导体晶体管元件200中栅极与漏极之间的寄生电容降低的效果。举例来说，与上述第一实施例的高压金属氧化物半导体晶体管元件100相比较，本实施例的高压金属氧化物半导体晶体管元件200在栅极结构30的第二部30B的蚀刻深度约为 0.1微米的状况下可维持相当的截止频率(cut-off frequency)，并可使栅极漏极电容(Cgd)降低约25％，且同时提升击穿电压(break down voltage)。此外，通过改变漂移区域11的掺杂浓度也可在降低栅极漏极电容的程度以及其他电性(例如击穿电压与截止频率)之间获得更平衡的结果。另一方面，由于栅极结构30的第二部30B的蚀刻深度不同会影响高压金属氧化物半导体晶体管元件200的电性表现，因此栅极结构30的第二部30B的蚀刻深度控制在目标值±8％的范围内，且优选控制在目标值±3％的范围内，由此确保高压金属氧化物半导体晶体管元件200的电性状况与均匀性。
请参阅图5与图6。图5与图6所绘示为本发明第三实施例的高压金属氧化物半导体晶体管元件的制造方法示意图。如图5至图6所示，与上述第二实施例不同的地方在于，本实施例的制造方法是先进行蚀刻制作工艺92 再进行注入制作工艺91，也就是说注入制作工艺91于蚀刻制作工艺92之后进行，且部分的半导体基底10的第二区R2被蚀刻制作工艺92移除，由此可避免漂移区域11形成之后其第四部11B的第四上表面T4被蚀刻制作工艺 92影响，故对于高压金属氧化物半导体晶体管元件的电性状况有正面的帮助。
请参阅图7与图8。图7与图8所绘示为本发明第四实施例的高压金属氧化物半导体晶体管元件的制造方法示意图。如图7至图8所示，与上述第二实施例不同的地方在于，在本实施例的蚀刻制作工艺92中，图案化掩模层40还覆盖半导体基底10的第二区R2。因此，不论上述的注入制作工艺在蚀刻制作工艺92之前或之后进行，高压金属氧化物半导体晶体管元件300 中的漂移区域11均不会被蚀刻制作工艺蚀刻。换句话说，本实施例的漂移区域11的第三部11A的第三上表面T3与第四部11B的第四上表面T4等高，而由于漂移区域11并未被蚀刻，故相对于上述第二实施例的高压金属氧化物半导体晶体管元件200来说，本实施例的高压金属氧化物半导体晶体管元件300的栅极漏极电容(Cgd)的降低幅度较小，但其他电性表现(例如击穿电压与截止频率)仍可维持相当的状况。值得说明的是，在本发明的其他实施例中，也可使图案化掩模层40未覆盖半导体基底10的第二区R2，而是通过调整蚀刻制作工艺92的制作工艺参数以及蚀刻选择比使得蚀刻制作工艺 92在第二区R2停止在第二区R2的栅极介电层20上而未蚀刻第二区R2的半导体基底10。
综上所述，本发明的高压金属氧化物半导体晶体管元件的制造方法是利用蚀刻制作工艺移除部分的栅极结构，使得栅极结构于靠近漂移区域的部分可具有较小的厚度，由此可在较不影响元件特性的状况下达到降低栅极与漏极之间寄生电容的效果。对于当高压金属氧化物半导体晶体管元件用于功率放大器时，可因为栅极与漏极之间寄生电容的降低而获得功率附加效率 (power added efficiency，PAE)的提升。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (12)

1.一种高压金属氧化物半导体(high voltage metal-oxide-semiconductor，HV MOS)晶体管元件的制造方法，包括：
提供一半导体基底；
在该半导体基底上形成一栅极结构，其中该栅极结构包括第一部以及第二部，该半导体基底具有第一区以及第二区，该第一区位于该栅极结构的该第一部的一侧，而该第二区位于该栅极结构的该第二部的一侧；
在该半导体基底以及该栅极结构上形成一图案化掩模层，其中该图案化掩模层覆盖该半导体基底的该第一区以及该栅极结构的该第一部，且该栅极结构的该第二部暴露于该图案化掩模层之外；
进行一注入制作工艺，用以于该第二区中形成一漂移区域；
进行一蚀刻制作工艺，用以移除部分的未被该图案化掩模层覆盖的该栅极结构的该第二部，其中在该蚀刻制作工艺之后，该第二部的厚度小于该第一部的厚度，其中该栅极结构的该第一部与该栅极结构的该第二部互相接触且连接，且于该蚀刻制作工艺之后，该第一部的一侧表面与该第二部的一上表面直接相连；以及
于该第一部的该侧表面形成第一间隙壁以及于该第二部的一侧表面上形成第二间隙壁，且该第一间隙壁与该第二间隙壁互相分离，
其中该蚀刻制作工艺于该注入制作工艺之后进行，且一部分的该漂移区域被该蚀刻制作工艺移除。
2.如权利要求1所述的高压金属氧化物半导体晶体管元件的制造方法，其中该注入制作工艺于该蚀刻制作工艺之后进行。
3.如权利要求1所述的高压金属氧化物半导体晶体管元件的制造方法，还包括：
在该半导体基底的该第一区中形成一源极区；以及
在该漂移区域中形成一漏极区。
4.如权利要求3所述的高压金属氧化物半导体晶体管元件的制造方法，其中该源极区包括一n型掺杂区，该漏极区包括一n型掺杂区，且该漂移区域包括一n型阱。
5.如权利要求1所述的高压金属氧化物半导体晶体管元件的制造方法，其中该漂移区域包括互相连接的第三部以及第四部，该栅极结构覆盖该漂移区域的该第三部，且该漂移区域的该第四部暴露于该栅极结构之外。
6.如权利要求5所述的高压金属氧化物半导体晶体管元件的制造方法，其中于该蚀刻制作工艺之后，该第四部的一上表面低于该第三部的一上表面，且该第三部的一侧表面与该第四部的该上表面相连。
7.如权利要求6所述的高压金属氧化物半导体晶体管元件的制造方法，还包括于该漂移区域的该第三部的该侧表面上以及该栅极结构的该第二部的一侧表面上形成第三间隙壁。
8.一种高压金属氧化物半导体(high voltage metal-oxide-semiconductor，HV MOS)晶体管元件，包括：
半导体基底；
栅极结构，设置于该半导体基底上，其中该栅极结构包括第一部以及第二部，该第二部的厚度小于该第一部的厚度，该第一部与该第二部互相接触且连接，且该第一部的一侧表面与该第二部的一上表面直接相连；
第一间隙壁，设置于该第一部的该侧表面上；
第二间隙壁，设置于该第二部的一侧表面上，且该第一间隙壁与该第二间隙壁互相分离；以及
漂移区域，设置于该栅极结构的该第二部的一侧，
其中该漂移区域包括互相连接的第三部以及第四部，该栅极结构覆盖该漂移区域的该第三部，且该漂移区域的该第四部未被该栅极结构覆盖，
其中该第四部的上表面低于该第三部的上表面，且该第三部的一侧表面与该第四部的该上表面相连，
该高压金属氧化物半导体晶体管元件还包括第三间隙壁，设置于该漂移区域的该第三部的该侧表面上以及该栅极结构的该第二部的一侧表面上。
9.如权利要求8所述的高压金属氧化物半导体晶体管元件，其中该栅极结构的该第一部的上表面与该栅极结构的该第二部的上表面不共平面(not coplanar)。
10.如权利要求8所述的高压金属氧化物半导体晶体管元件，还包括：
源极区，设置于该半导体基底中；以及
漏极区，设置于该半导体基底中，其中至少部分的该漏极区设置于该漂移区域中，且该源极区设置于与该栅极结构的该第一部相邻的一侧。
11.如权利要求10所述的高压金属氧化物半导体晶体管元件，其中该源极区的上表面与该漏极区的上表面不共平面(not coplanar)。
12.如权利要求10所述的高压金属氧化物半导体晶体管元件，其中该源极区包括一n型掺杂区，该漏极区包括一n型掺杂区，且该漂移区域包括一n型阱。
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