CN103137498B - 半导体封装结构及其制作方法 - Google Patents

半导体封装结构及其制作方法 Download PDF

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CN103137498B
CN103137498B CN201210087616.8A CN201210087616A CN103137498B CN 103137498 B CN103137498 B CN 103137498B CN 201210087616 A CN201210087616 A CN 201210087616A CN 103137498 B CN103137498 B CN 103137498B
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heat
conducting block
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CN103137498A (zh
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潘玉堂
周世文
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Chipmos Technologies Inc
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Abstract

一种半导体封装结构的制作方法。提供一导电基材。透过一第一粘着层将一导热块贴附于导电基材的部分一第二表面上。对导电基材的一第一表面进行一半蚀刻步骤，而形成一开口。图案化剩余的导电基材，以形成多个引脚并暴露部分导热块。每一引脚具有一第一部分与一第二部分。第一部分的厚度大于第二部分的厚度。第一部分的一第一下表面与第二部分的一第二下表面齐平。将一芯片配置于被暴露出的部分导热块上且与引脚的第二部分电性连接。形成一封装胶体以包覆芯片、部分引脚及部分导热块。导热块的一第一底面与封装胶体的一第二底面齐平。

Description

半导体封装结构及其制作方法
技术领域
本发明是有关于一种半导体元件及其制作方法，且特别是有关于一种半导体封装结构及其制作方法。
背景技术
芯片封装的目的在于保护裸露的芯片、降低芯片接点的密度及提供芯片良好的散热。常见的封装方法是芯片透过打线接合(wire bonding)或覆晶接合(flip chipbonding)的方式而安装至一导线架或一线路板上，以使芯片上的接点可电性连接至导线架或线路板上。如此一来，芯片的接点分布可藉由导线架或线路板重新配置，以符合下一层级的外部元件的接点分布。
然而随着技术提升以及元件尺寸微型化的趋势，芯片的尺寸逐渐缩小。因此，当芯片的尺寸缩小时，芯片与导线架的引脚间的距离相对地增加，连接芯片与引脚的焊线长度也因此增长。如此一来，可能造成元件的传输信号衰减、电性效能降低、生产成本提高。再者，较长的焊线也可能在进行封胶工艺时，产生线塌(collapse)或线偏移(wire sweep)的状况，进而影响产品的可靠度。
发明内容
本发明提供一种半导体封装结构，其具有较佳的可靠度。
本发明提供一种半导体封装结构的制作方法，用以制作上述的半导体封装结构。
本发明提出一种半导体封装结构的制作方法，其包括以下步骤。提供一导电基材，其中导电基材具有彼此相对的一第一表面与一第二表面。透过一第一粘着层将一导热块贴附于导电基材的部分第二表面上。对导电基材的第一表面进行一半蚀刻步骤，以移除部分导电基材，而形成一开口于第一表面。图案化剩余的导电基材，以形成多个彼此电性绝缘的引脚，并暴露部分导热块，其中每一引脚具有一第一部分与一第二部分，第一部分的厚度大于第二部分的厚度，且第一部分的一第一下表面与第二部分的一第二下表面齐平。将一芯片配置于被暴露出的部分导热块上，其中引脚的第二部分邻近且环绕芯片的周围，而芯片与引脚的第二部分电性连接。形成一封装胶体以包覆芯片、部分引脚以及部分导热块。
本发明提出一种半导体封装结构，其包括一导热块、多个引脚、一第一粘着层、一芯片以及一封装胶体。导热块具有彼此相对的一第一顶面与一第一底面。引脚配置于导热块的第一顶面上，并暴露出部分第一顶面。引脚彼此电性绝缘，其中每一引脚具有一第一部分与一第二部分，且第一部分的厚度大于第二部分的厚度，而第一部分的一第一下表面与第二部分的一第二下表面齐平。第一粘着层配置于引脚与导热块之间。芯片配置于导热块被暴露出的部分第一顶面上，其中引脚的第二部分邻近且环绕芯片的周围，芯片与引脚的第二部分电性连接。封装胶体包覆芯片、部分引脚以及部分导热块。
基于上述，由于本发明是对导电基材进行半蚀刻步骤及图案化步骤来形成同时具有不同厚度的第一部分及第二部分的引脚。因此，当芯片设置于导热块上时，本发明的半导体封装结构除了可具有较佳的散热效能外，亦可透过引脚的第二部分邻近且环绕芯片的设计来缩短采用打线接合时芯片与引脚之间的焊线距离，以避免现有长焊线线塌(collapse)或线偏移(wire sweep)的状况，可有效提升产品的可靠度。再者，当芯片采用覆晶接合的方式与引脚的第二部分电性连接时，亦可有效降低封装厚度，使半导体封装结构具有较薄的封装厚度。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附附图作详细说明如下。
附图说明
图1为本发明的一实施例的一种半导体封装结构的俯视示意图。
图2A至图2E为本发明的一实施例的一种半导体封装结构的制作方法的剖面示意图。
图3A至图3B为本发明的另一实施例的一种半导体封装结构的制作方法的局部步骤的剖面示意图。
具体实施方式
图1为本发明的一实施例的一种半导体封装结构的俯视示意图。图2A至图2E为本发明的一实施例的一种半导体封装结构的制作方法的剖面示意图。请先参考图2A，本实施例的半导体封装结构的制作方法包括以下步骤。首先，提供一导电基材110，其中导电基材110具有彼此相对的一第一表面112与一第二表面114，且导电基材110的材质例如是金属，包括铜、铜合金、铁镍合金或其他适当的金属材质。当然，导电基材110的材质亦可是其他具有导电性质的材料。
接着，请再参考图2A，透过一第一粘着层120将一导热块130贴附于导电基材110的部分第二表面114上，其中第一粘着层120位于导热块130与导电基材110之间，且导热块130暴露出导电基材110的部分第二表面114。具体来说，本实施例的导热块130具有彼此相对的一第一顶面132与一第一底面134，其中第一顶面132连接第一粘着层120，且导热块130的材质包括铜、铝、铜合金、铝合金、铁镍合金或其他具有导电性质的材料。
接着，请参考图2B，对导电基材110的第一表面112进行一半蚀刻(half-etching)步骤，以移除部分导电基材110，而形成一开口113于导电基材110的第一表面112，其中位于开口113内的部分导电基材110的厚度小于原本导电基材110的厚度。
接着，请同时参考图1与图2C，图案化剩余的导电基材110，以形成多个彼此电性绝缘的引脚140，并暴露部分导热块130，即导热块130的部分第一顶面132，其中图案化剩余的导电基材110的方法例如是蚀刻法。
特别是，在本实施例中，每一引脚140具有一第一部分142与一第二部分144，其中第一部分142的厚度T1大于第二部分144的厚度T2，且第一部分142的一第一下表面143与第二部分144的一第二下表面145实质上齐平。此外，本实施例的任两相邻的引脚140的第一部分142的间距为P1，而任两相邻的引脚140的第二部分144的间距为P2，则较佳地0.8P1≤P2≤1.2P1。于此，任两相邻的引脚140的第二部分144的间距P2例如是介于40微米至60微米之间，较佳地，介于50微米至60微米之间，此间距P2可依据芯片的接垫152之间的间距来调整，于此并不加以限制。
之后，请同时参考图1与图2D，将一芯片150配置于被暴露出的部分导热块130上，即导热块130的部分第一顶面132上，其中引脚140的第二部分144邻近且环绕芯片150的周围，而芯片150与引脚140的第二部分144电性连接。在本实施例中，芯片150是透过一第二粘着层125而固定于被暴露出的部分导热块130上，即第二粘着层125配置于导热块130的部分第一顶面132与芯片150之间，且芯片150透过多条焊线160与引脚140的第二部分144电性连接。
最后，请同时参考图1与图2E，形成一封装胶体170以包覆芯片150、部分引脚140以及部分导热块130，并填满引脚140之间的间隙，其中导热块130的第一底面134与封装胶体170的一第二底面172实质上齐平。当然，于其他未绘示的实施例中，导热块130的第一底面134亦可包覆于封装胶体170内。较佳地，封装胶体170可暴露出引脚140的部分第一部分142以形成一般的导线架(如图2E所示)，亦或，可视实际所需而不暴露出引脚140以形成一QFN结构(未绘示)。至此，已完成半导体封装结构100a的制作。
在结构上，请再参考图2E，本实施例的半导体封装结构100a包括第一粘着层120、第二粘着层125、导热块130、引脚140、芯片150、焊线160以及封装胶体170。详细来说，导热块130具有彼此相对的第一顶面132与第一底面134。引脚140配置于导热块130的第一顶面132上，并暴露出部分第一顶面132。引脚140彼此电性绝缘，且每一引脚140具有第一部分142与第二部分144，其中第一部分142的厚度T1大于第二部分144的厚度T2，而第一部分142的第一下表面143与第二部分144的第二下表面145实质上齐平。第一粘着层120配置于引脚140与导热块130之间，其中引脚140透过第一粘着层120而固定于导热块130上。芯片150配置于导热块130被暴露出的部分第一顶面132上，其中引脚140的第二部分144邻近且环绕芯片150的周围，而芯片150透过第二粘着层125固定导热块130被暴露出的部分第一顶面132上，且芯片150透过焊线160与引脚140的第二部分144电性连接。封装胶体170包覆芯片150、部分引脚140以及部分导热块130。于此，导热块130的第一底面134外露于封装胶体170并与封装胶体170的第二底面172实质上齐平。
由于本实施例是对导电基材110进行半蚀刻步骤及图案化步骤来形成具有第一部分142及第二部分144的引脚140，其中第一部分142的厚度T1大于第二部分144的厚度T2。因此，当芯片150设置于导热块130上时，芯片150所产生的热可透过导热块130的第一底面134快速地传递至外界，而使本实施例的半导体封装结构100a具有较佳的散热效能。再者，可利用引脚140的第二部分144邻近且环绕芯片150的设计，使芯片150藉由打线接合的方式以透过焊线160来电性连接引脚140的第二部分144。如此一来，可有效缩短采用打线接合时芯片150与引脚140之间的焊线距离，以避免现有长焊线线塌(collapse)或线偏移(wire sweep)的状况，可有效提升产品的可靠度。
图3A至图3B为本发明的另一实施例的一种半导体封装结构的制作方法的局部步骤的剖面示意图。本实施例沿用前述实施例的元件标号与部分内容，其中采用相同的标号来表示相同或近似的元件，并且省略了相同技术内容的说明。关于省略部分的说明可参照前述实施例，本实施例不再重复赘述。
请先参考图3B，本实施例的半导体封装结构100b与前述实施例的半导体封装结构100a主要的差异是在于：半导体封装结构100b更包括多个凸块165，其中凸块165配置于芯片150与引脚140的第二部分144之间，且芯片150是藉由覆晶接合的方式以透过凸块165与引脚140的第二部分144电性连接。由于本实施例的芯片150是采用覆晶接合的方式与引脚140的第二部分144电性连接，且引脚140的第二部分144的厚度T2小于第一部分142的厚度T1，因此可有效降低整体封装厚度，使半导体封装结构100b具有较薄的封装厚度。
在工艺上，本实施例的半导体封装结构100b可以采用与前述实施例的半导体封装结构100a大致相同的制作方式，并且在图2C的步骤后，即图案化剩余的导电基材110，以形成彼此电性绝缘的引脚140之后，藉由覆晶接合的方式使芯片150透过凸块165与引脚140的第二部分144电性连接。接着，依序进行图2E的步骤，即便可大致完成半导体封装结构100b的制作。
当然，图2A至图2E以及图3A至3B所绘示的工艺仅是作为举例说明之用，部分步骤为目前封装工艺中常见的技术。本领域的技术人员当可依据实际状况调整、省略或增加可能的步骤，例如以阵列方式配置多个导热块130于导电基材110上，之后再进行单体化步骤以同时大量制作多个半导体封装结构100a(或100b)，以符合量产及降低成本的需求，此处不再逐一赘述。
综上所述，由于本发明是对导电基材进行半蚀刻步骤及图案化步骤来形成同时具有不同厚度的第一部分及第二部分的引脚。因此，当芯片设置于导热块上时，本发明的半导体封装结构除了可具有较佳的散热效能外，亦可透过引脚的第二部分邻近且环绕芯片的设计来缩短采用打线接合时芯片与引脚之间的焊线距离，以避免现有长焊线线塌(collapse)或线偏移(wire sweep)的状况，可有效提升产品的可靠度。再者，当芯片采用覆晶接合的方式与引脚的第二部分电性连接时，亦可有效降低封装厚度，使半导体封装结构具有较薄的封装厚度。
虽然本发明已以实施例揭露如上，然其并非用以限定本发明，任何所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，故本发明的保护范围当视后附的权利要求所界定者为准。

Claims (8)

1.一种半导体封装结构的制作方法，包括：
提供一导电基材，该导电基材具有彼此相对的一第一表面与一第二表面；
透过一第一粘着层将一导热块贴附于该导电基材的部分该第二表面上；
对该导电基材的该第一表面进行一半蚀刻步骤，以移除部分该导电基材，而形成一开口于该第一表面；
图案化剩余的该导电基材，以形成多个彼此电性绝缘的引脚，并暴露部分该导热块，其中各该引脚具有一第一部分与一第二部分，该第一部分的厚度大于该第二部分的厚度，且该第一部分的一第一下表面与该第二部分的一第二下表面齐平；
将一芯片配置于被暴露出的部分该导热块上，其中所述多个引脚的所述多个第二部分邻近且环绕该芯片的周围，而该芯片与所述多个引脚的所述多个第二部分电性连接；以及
形成一封装胶体以包覆该芯片、部分所述多个引脚以及部分该导热块，任两相邻的所述多个引脚的所述多个第一部分的间距为P1，而任两相邻的所述多个引脚的所述多个第二部分的间距为P2，则0.8P1≤P2≤1.2P1，该导热块的一第一底面与该封装胶体的一第二底面实质上齐平。
2.如权利要求1所述的半导体封装结构的制作方法，其特征在于，任两相邻的所述多个引脚的所述多个第二部分的间距介于40微米至60微米之间。
3.如权利要求1所述的半导体封装结构的制作方法，其特征在于，该芯片透过多条焊线与所述多个引脚的所述多个第二部分电性连接。
4.如权利要求1所述的半导体封装结构的制作方法，其特征在于，该芯片透过多个凸块与所述多个引脚的所述多个第二部分电性连接。
5.一种半导体封装结构，包括：
一导热块，具有彼此相对的一第一顶面与一第一底面；
多个引脚，配置于该导热块的该第一顶面上，并暴露出部分该第一顶面，所述多个引脚彼此电性绝缘，其中各该引脚具有一第一部分与一第二部分，且该第一部分的厚度大于该第二部分的厚度，而该第一部分的一第一下表面与该第二部分的一第二下表面齐平；
一第一粘着层，配置于所述多个引脚与该导热块之间；
一芯片，配置于该导热块被暴露出的部分该第一顶面上，其中所述多个引脚的所述多个第二部分邻近且环绕该芯片的周围，该芯片与所述多个引脚的所述多个第二部分电性连接；以及
一封装胶体，包覆该芯片、部分所述多个引脚以及部分该导热块，任两相邻的所述多个引脚的所述多个第一部分的间距为P1，而任两相邻的所述多个引脚的所述多个第二部分的间距为P2，则0.8P1≤P2≤1.2P1，该导热块的一第一底面与该封装胶体的一第二底面实质上齐平。
6.如权利要求5所述的半导体封装结构，其特征在于，任两相邻的所述多个引脚的所述多个第二部分的间距介于40微米至60微米之间。
7.如权利要求5所述的半导体封装结构，其特征在于，更包括多条焊线，配置于该芯片与所述多个引脚的所述多个第二部分之间，其中该芯片透过所述多个焊线与所述多个引脚的所述多个第二部分电性连接。
8.如权利要求5所述的半导体封装结构，其特征在于，更包括多个凸块，配置于该芯片与所述多个引脚的所述多个第二部分之间，其中该芯片透过所述多个凸块与所述多个引脚的所述多个第二部分电性连接。
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