CN103109365A - Seed layer deposition in microscale features - Google Patents

Seed layer deposition in microscale features Download PDF

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Publication number
CN103109365A
CN103109365A CN2011800180865A CN201180018086A CN103109365A CN 103109365 A CN103109365 A CN 103109365A CN 2011800180865 A CN2011800180865 A CN 2011800180865A CN 201180018086 A CN201180018086 A CN 201180018086A CN 103109365 A CN103109365 A CN 103109365A
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workpiece
coating
deposition
barrier
approximately
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CN103109365B (en
Inventor
丹尼尔·L·古德曼
亚瑟·柯格勒
约翰内斯·邱
刘震球
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ASM Nexx Inc
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Nexx Systems Inc
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    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00—Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/001—Apparatus specially adapted for electrolytic coating of wafers, e.g. semiconductors or solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors
    • H01L2221/1073—Barrier, adhesion or liner layers
    • H01L2221/1084—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L2221/1089—Stacks of seed layers

Abstract

A method and system for coating the interior surfaces of microscale hole features fabricated into the substantially planar surface of a work piece: The method comprises providing a work piece with a barrier metal coating that is substantially uniform, and is applied by a substantially surface reaction limited process. The workpiece has a coating, on its planar surface, of a thick metal layer anchored to the barrier metal coat and disposed to provide substantially uniform electrical conduction capability to the microscale features located on the workpiece. An electrical contact path is provided to the electrically conductive coating at the perimeter of the work piece. The workpiece is immersed in a chemical bath of metal ions, which fully contacts the interior surfaces of the microscale hole features. An electric potential is applied at the perimeter of the work piece to deposit metal ions onto all surfaces in one step.

Description

Seed layer deposition in microscopic feature
Technical field
Embodiment disclosed by the invention is broadly directed to the method and apparatus for the fluid treatment workpiece, be specifically related to for the workpiece that is coated with the high resistivity metal film the method and apparatus of the recessed plated metal of microcosmic, relate more specifically to utilize copper to be coated with this surperficial method and apparatus after applied barrier metals for the inner surface in perforation silicon via hole (TSV) feature.
Background technology
Recently developed and connected silicon via hole (TSV) structure as the method for making three-dimensional (3D) electronics integrated device.These TSV structures must form metal bolt in the aperture in silicon or other backing materials, and wherein typical hole dimension has approximately the diameter of 1 to 30 micron and the degree of depth of 10 to 250 microns.In order to make the TSV structure, at first etching is portalled in silicon or backing material, utilize insulating material (for example, silicon dioxide) be coated with the hole, it is covered by the barrier material such as titanium, tantalum or its nitride (being titanium nitride or tantalum nitride) subsequently, utilizes subsequently the electric conducting material such as copper to come filler opening.The usual manner that is used for utilizing copper to fill TSV is to use to electroplate, it utilizes a kind of in variety of way preferably copper is deposited on bottom, described hole by electroplating, and make copper flat surfaces (or field) upper deposit more of vias inside than silicon substrate, Here it is, and known copper is from bottom to top inlayed the electroplating processes method of filling.In order to complete this conventional method, must form plating seed layer, with the electroplating film of growing thereon, Seed Layer and plating filling step material are identical materials usually, both are copper usually, and routine forms the copper plating seed layer by physical vapor deposition (PVD).In the situation that higher depth-width ratio TSV structure (compared to mosaic texture), the difficult point of the conventional method of use PVD metal level is that the physical vapor deposition metal is coated with on the inner surface in TSV hole few, therefore can the imperfect and insufficient barrier of formation and seed metal layer in those zones.Because the ballistic transport character of PVD (ballistic transport nature), along with the degree of depth of TSV with diameter than (namely, depth-width ratio) increase, the above-mentioned shortcoming of PVD is more obvious, will be described this in more detail below with reference to prior art.
Favourable in order to realize business that three-dimensional IC makes and the advantage of reliability, to make having than high depth to the TSV hole of diameter ratio, 10 or higher depth-width ratio more favourable.The conventional alternative method that metal level is deposited in high depth-width ratio TSV feature is ald (ALD) or chemical vapor deposition (CVD).ALD is by one of atomic layer of a series of surface-limited reaction atomic layer ground depositing metallic films, in fact the surface-limited reaction does not consider the micro-geometry on surface, because provide the mode of theoretical ideal to be coated with the TSV internal feature to have metal level, but, ALD processes slower, and is therefore commercially impracticable for a lot of manufacturing TSV use.CVD be known and viable commercial with TiN, TaN or W barrier metals are deposited on the mode in high depth-width ratio hole, still, have been found that, because the metal organic precursor material is unstable and expensive, for copper or other Seed Layer metals, it is commercially also impracticable.Also there is defective in conventional wet processed such as electrochemical deposition (ECD) and electroless metal deposition when microstructure is made in commercialization.In the situation that electroless metal deposition, the reactant that can comprise because of fluid and catalyst react on the TSV inner surface and produce chemical potential.Electroless metal deposition requires a series of Chemical Pretreatment, to set up reaction gesture (reaction potential) between bearing metal and seed metal reactant, and must strictly control pretreated chemical analysis and sedimentation chemistry bath, all these all can cause processing very expensive and being difficult to operation without electric metal.Substituting conventional wet processed method, namely conventional ECD, also exist other to cause not being suitable for the defective of manufacturing.For example, utilize conventional ECD mode that seed metal is deposited on and (for example be coated with the high impedance barrier metals, very large difficult point on the inner surface of the TSV feature of the substrate TiN with impedance of 10 to 100ohms/square) is, along with electric current flows to substrate center from substrate perimeter, larger diametral voltage can occur and fall in barrier metals, this larger voltage drop meeting causes producing between the margin and center zone of substrate the difference of undesirable available driving electromotive force.Be formed to electrically contacting of substrate at the edge of substrate, and circuit enters electrochemical bath via barrier metals and completes.The high impedance metal level causes from the larger voltage drop at edge to the center of substrate subsequently.U.S. Patent Publication No. 2005/0199502 and U. S. application number 11/123,117 have proposed to overcome the usual manner of the defects of conventional ECD, a kind of method wherein is provided, make by beginning to deposit to substrate center from edges of substrate with chemical addition agent, to stop the further deposition on the copper seed metal, when using deposited copper as front conductive layer, realize preferred deposition on the not coated region of barrier metals thus.The potential challenges that this method exists is, control to produce sufficient nuclear power gesture (nucleation potential) between barrier metals and copper metallic face to the chemical addition agent concentration in proper range.Therefore, confirmed that conventional method and equipment are not sufficient to make the TSV structure.
Description of drawings
Except other advantages, the advantage of above-mentioned technology also can better be understood with reference to following detailed description in conjunction with the drawings.In the drawings, similarly reference number is used to represent part identical in different views.Accompanying drawing is not to draw to scale, and specific part has been carried out emphasizing to illustrate principle of the present invention.
Figure 1A-1C shows the viewgraph of cross-section of the microscopic feature of the different phase of making in routine;
Fig. 2 shows the standardization overvoltage, as the function of the position on wafer or workpiece;
Fig. 3 shows the viewgraph of cross-section of the application's disclosed embodiment;
Fig. 4 is the flow chart of the application's disclosed embodiment;
Fig. 5 is the schematic diagram of the electroplating processes unit that is suitable for using in the application's disclosed embodiment;
Fig. 6 shows having on the TiN barrier of different impedances the directly impedance situation of the Cu of plating, wherein not only is difficult to control whole uniformity, but also always has centerand edge difference, and this is especially serious in higher barrier impedance position.
Fig. 7 is photo, show the structure of the plating Cu on naked barrier wafer being carried out drawstring test (tape pull test), drawstring test in the situation that center to the edge overpotential of supposition usual manner change and be employed to detect tack (only the part of wafer can the good tack of optimised realization, only the central area in the case, perhaps wafer edge region, but not whole wafer);
Fig. 8 (a) is photo, show the via hole (core fails to reach via bottom) that does not have conduction Cu PVD layer and be filled, and Fig. 8 (b) is another photo, show the via hole that utilizes system and handling process according to exemplary embodiment to be filled, used in the case the conduction Cu PVD layer that forms according to the application's disclosed embodiment, and wherein can observe solid filler in whole via hole, there is good Cu core in confirmation thus.
Embodiment
Although describe the present invention with reference to the embodiment shown in figure, should be appreciated that the various alternative forms that the present invention can embodiment realize.In addition, can use element or the material of any suitable size, shape or type.
Wet processed is for reactant being sent to the feasible pattern of the inner surface of TSV structure, because transmit mainly via diffusion at the fluid of this characteristic dimension, therefore compared to PVD, seldom being subject to the restriction of high depth-width ratio geometry.In order to affect the wet processed to the TSV structure, be desirable to provide a kind of be used to making inner TSV structure moistening mode fully, in other words, a kind of mode is provided, replace barrier metals/air interface with barrier metals/fluid boundary, and the preferred embodiment of the method and equipment has been described, in this is contained in this specification with its full content by reference by Keigler in Application No. 61/151,385., can transmit via diffusion reactant is sent to these surfaces with after all elements on inner TSV surface contact fully at fluid.In addition, drive electromotive force by suitable electricity is provided, can form electrochemical reaction, and the reactant in fluid is transmitted in the metal deposition layer metal that enters on the TSV inner surface.But, as mentioned above, utilize conventional ECD mode that seed metal is deposited on and (for example be coated with the high impedance barrier metals, very large difficult point on the inner surface of the TSV feature of the substrate TiN with impedance of 10 to 100ohms/square) is, along with electric current flows to substrate center from substrate perimeter, larger diametral voltage can occur and fall in barrier metals.This larger voltage drop meeting causes producing between the margin and center zone of substrate the difference of undesirable available driving electromotive force.As described below, the disclosed embodiment of the application has overcome these defectives of conventional depositional mode, with the local electromotive force that abundance is provided on the TSV inner surface, to realize suitable metal electrodeposition, forms plating seed layer with the part.
As described below, for follow-up filling TSV structure, the seed that uses or the expected characteristics of conductive layer are, this layer quilt is attached to fully well the flat surfaces of substrate, the stress that is applied with the copper layer that bears relatively thick (1 to 5 micron) that forms in TSV fills processing procedure on flat surfaces, and it must bear the mechanical stress that the cmp that usually carries out brings after the TSV filling step.The tack of electrodeposit metals film depends critically upon cuclear density, and it depends on local deposits overvoltage and electroplating chemical characteristic.(for example be used for the conventional method of " direct on barrier " or " Seed Layer reparation " electro-deposition, U.S. Patent number 7,247, disclosed method in 223) need to be used for the expensive complex device of electro-deposition, to realize minimum overvoltage difference on whole substrate, and can need the annealing steps after the Seed Layer electro-deposition, to improve tack before filling step.As detailed below, compared to conventional method, exemplary embodiment provides a kind of method of economy, it provides the reliable attachment of Seed Layer, and do not rely on annealing steps, and better overvoltage uniformity is provided on whole substrate, has realized to repeat tack and kernel structure thus in whole TSV of substrate.
Exemplary embodiment as described below provides method, system and assembly, is used for forming metal seed layer by the inner surface in the lip-deep perforation silicon via feature of workpiece and processes one or more workpiece.Workpiece can be smooth or general planar, and can be thin or ultra-thin.Suitable workpiece includes but not limited to semiconductor wafer, silicon workpiece, interconnect substrate and printed circuit board (PCB).
At first, come formation microcosmic hole in workpiece by known etch processes, and suitable isolation and barrier film are applied to workpiece, both are on the inner surface of flat surfaces and microcosmic via hole, particularly, utilize chemical vapor deposition to apply thickness between tungsten, titanium nitride or the tantalum nitride barrier layer of 200 to 500 dusts, this barrier film make the surface have between 10 with the surface conductivity of 200ohms/square.Then, adhere to promotion rete (for example thickness is between the titanium of 200 to 500 dusts) by utilizing physical vapor deposition (PVD) to apply combination, with after-applied essence conduction tunic (for example thickness is between the copper (it can be called as thick-layer) of 1000 to 3000 dusts), the disclosed embodiment of the application provides the method that a plurality of microcosmic via feature is electrically connected to wafer perimeter.In the exemplary embodiment, PVD processes and may not deposit fully considerable seed metal in the microcosmic via feature.But PVD processes really to provide reliably between the flat surfaces of Ti/Cu layer and substrate and adheres to, and thus conductive layer is anchored into barrier layer and substrate surface.So well attached essence conduction Ti/Cu layer provides the electromotive force that electromotive force is applied to the inner surface of whole microcosmic via holes.
Utilization is guaranteed to eliminate fully in the microcosmic via hole air and interface, metal surface and is utilized fluid and with the interface, metal surface, its mode that substitutes (is for example passed through use as the Application No. 61/151 of Keigler, the 385 pre-infusion methods of disclosed vacuum, here by using, its full content is contained in this specification), the substrate with microcosmic via hole can be immersed and process fluid.Fluid can be deionization and the water that degass, and perhaps it can be the water that comprises the hydrofluoric acid of 0.5% weight.Can utilize the copper electroplating solution to remove and substitute and infiltrate fluid.Complete above step in can be in wafer being remained on basically the anaerobic environment.For example can infiltrate in advance pipe by utilizing oxygenless gas (for example nitrogen) that fluid is gone out vacuum, and by pumping nitrogen and recovering vacuum environment and replenish new fluid, realize above-mentioned purpose.At this moment, the microcosmic via hole comprises the copper electroplating solution.The top side part of the sidewall of microcosmic via hole can be via being connected to power supply and being roughly parallel to the PVD Ti/Cu conductive layer of the anode that wafer surface arranges and being electrically connected to wafer perimeter.Can apply a series of short negative voltage pulses in interior the company between microcosmic arrays of vias and anode.The copper ion that the duration of each pulse makes next-door neighbour wafer surface interface in the microcosmic via hole with the copper deposit electro-deposition on the metallic barrier surface and territory, smooth place, and with the copper deposit electro-deposition on PVD copper surface.Can provide the delay between pulse to spread from liquid solution with the permission copper ion, and substitute from the removed copper ion in neighbouring surface zone.For example, although can use other suitable disconnected/logical cycle ratio, the duration of having confirmed to break/lead to is that the ratio of approximately 2: 10 is comparatively preferred.By use can be called as relatively thick roughly evenly and the PVD copper layer of conduction and unconventional ultra-thin discontinuous PVD copper seed layer, the disclosed embodiment of the application has overcome the defective of conventional method.This roughly evenly and continuous conductive layer connect whole microcosmic via hole (particularly, the top side part of via sidewall) in can be roughly.Copper can be by Direct precipitation in the exemplary embodiment, be on the barrier metals that exposes on the wall of microcosmic via hole, by compensating thin PVD copper layer or directly copper being deposited on the barrier metals that covers whole wafer surface, eliminated the defective that usual manner runs into thus.The disclosed embodiment of the application has also eliminated the following puzzlement that usual manner (using ultra-thin Seed Layer) runs into, namely carry out electro-deposition on the high impedance substrate, need expensive ionization PVD depositing device, and eliminated the uncertainty that realizes that in whole via holes of substrate tight is filled.
With the system and method for the novelty of plating seed layer on the high impedance barrier layer inner surface of a plurality of microcosmic via holes on workpiece that describes that the disclosed embodiment of the application provides in detail.Particularly, the system and method for exemplary embodiment provides Seed Layer in high depth-width ratio connects silicon via hole (TSV), and utilizes copper to electroplate and filled TSV.The restriction that the disclosed embodiment of the application has avoided conventional method to deposit on the high impedance substrate, those methods or utilization directly deposit on the high impedance barrier layer, or utilize super thin metal Seed Layer on the top of high impedance barrier layer, therefore need to use the conventional electroplating unit that adopts a plurality of anodes.
Sketch U.S. Patent number 7,115 with reference to Figure 1A, 196 (its full content being comprised in this manual by using) disclosed method of the prior art, Figure 1A shows the cross section such as the microscopic feature of TSV.Etch a plurality of holes 150 in substrate 140, then can utilize the dielectric film (not shown) then to utilize high impedance barrier metals layer 152 that above-mentioned substrate and hole are coated with, can be by such as the vapor deposition process of plasma vapor deposition (PVD) or deposit this coating by chemical vapor deposition (CVD).The effect of conventional barrier metals layer be to prevent metallic atom (being generally copper atom) from the diffusion inside of TSV to substrate 140.Thus super thin metal Seed Layer 154 is deposited on the top of this barrier layer 152.Can utilize the chemical reaction such as electroless nickel deposition to carry out above-mentioned deposition, perhaps can utilize plasma vapor deposition (PVD) to carry out above-mentioned deposition at the uniform machinery that is used for the deposition barrier layer.At last, prior art is usually directed to use complicated electrodeposition apparatus (such as U.S. Patent number 7,115, the equipment of describing in 196 comprises its full content in this manual by reference) to improve the super thin metal Seed Layer.By using this equipment, prior art is attached to ultra-thin Seed Layer with more Seed Layer metal, makes it enough continuously to realize in follow-up electrodeposition process step filling the good electrical deposition of metal 158 (being generally copper).
Refer now to Figure 1B, it shows copper enchasing structure, and the microscopic feature 100 that wherein etches in substrate 102 has between the width of 500 to 2000 dusts or diameter 104 and between the degree of depth 106 of 5000 to 30000 dusts.For fear of existing larger potential difference to change, can corresponding to approximately 0.20 to 0.04ohms/square sheet impedance, apply the copper seed layer of the thickness (also can have the thickness up to 5000 dusts) that has at least about 1000 dusts on the silicon substrate of 300mm.As shown in Figure 1B, utilize PVD be deposited on 1000 dust Seed Layer 122 in the feature of 2000 dust width cause the hole before covered Seed Layer on the whole inner surface of microscopic feature by " extruding is closed ".Refer now to Fig. 1 C, for the application of these types, can deposit " ultra-thin " Seed Layer 102, it can only have the thickness of 100-250 dust.Be appreciated that this thin Seed Layer has the impedance of the scope of 4ohms/square.Application No. 11/050 as Vereecken, 899 (by reference its full content being comprised in this manual) are described, and as shown in the curve 300 in Fig. 2, this substrate resistance level can cause the superpotential very big difference of the deposition between wafer perimeter and center wafer, specifically successively decreases in the deposition overvoltage that can occur up to 100 times from periphery to the center.Fig. 7 is photo, shows the structure that the above-mentioned Cu that electroplates on covering TiN barrier wafer is carried out tape test.As shown in Figure 7, system is adjustable to the center or the edge tack that keep good.For example pass through the U.S. Patent number 6 of Woodruff, 497,801 and the U.S. Patent number 6 of Mayer, 773, describe in 571 (full content with both comprises in this manual by reference) such as the multianode part, or come to arrange the high impedance porous plate between anode and substrate by " EREX " system such as Ebara Corporation, also can change the geometry of plating tool so that the non-homogeneous electric field that applies to be provided, with the non-homogeneous overvoltage of compensation space.The deposition overvoltage has a strong impact on the tack of deposited film, and this is mainly because overvoltage is on depositing the impact of cuclear density.Although can realize uniform deposition for concrete sheet impedance wafer, when changing appears in the barrier impedance, maybe need it is readjusted.Fig. 6 shows the same treatment that is applied to two different barrier impedances.
With reference to figure 2, curve 302 shows the deposition overvoltage of the application's disclosed embodiment again, shows by the method that relatively thick conducting metal coating is applied to the flat surfaces of substrate being provided roughly overvoltage uniformly.Again with reference to figure 3, show the cross section of the disclosed embodiment of the application, wherein in the interior microscopic feature hole 200 of having made of substrate 201, its mesopore for example has diameter or the width 210 between approximately 1 to 10 micron (approximately 10000 to 100000 dusts), and between the degree of depth 212 of approximately 10 to 100 microns (approximately 100000 to 1000000 dusts), exemplary microscopic feature is circular, has the degree of depth of diameter and 50 to 75 microns (500000 to 750000 dusts) of 5 microns (50000 dusts).Be appreciated that microscopic feature shown in Figure 3 200 is representative, and can as required the feature that is similar to feature 200 be arranged arbitrarily on substrate 201.Substrate with microscopic feature can be coated with the dielectric film (not shown) by the processing mode that covering is set of roughly not considering micro-geometry, and can be coated with metallic barrier film 202, exemplary above-mentioned processing mode can be the chemical vapor deposition (CVD) of titanium nitride, tantalum nitride, ruthenium or tungsten, or the electrochemical deposition of nickel, above-mentioned barrier film for example has the approximately resistance of 1ohms/square to 200ohms/square, and the example process mode is approximately 5 to 50ohms/square.
Exemplary embodiment as described below is for example utilized the physical vapor deposition (PVD) of approximately 0.1 to 0.5 micron (1000 dust to 5000 dust) thick copper and has been deposited the coating 205 with well attached and conductivity.PVD copper layer can be deposited in the uniform machinery of deposition CVD barrier, can not cause barrier to generate oxide (its can make copper deteriorated to the tack of barrier) if this machine can move to pvd chamber from the CVD chamber with substrate and get final product.In alternate embodiment, PVD copper layer can deposit in the machine that separates, this machine removes oxide from barrier layer with known plasma precleaning etching method, and PVD sputter adhesion layer is set, thicker PVD sputter copper layer is set (for example subsequently, be the titanium of approximately 1000 dusts and the about copper of 2000 dusts in an embodiment), although in alternate embodiment, barrier and articulamentum can have other suitable thickness.As shown in Figure 3, PVD conductive layer 205 is for roughly evenly and continuously, and can not be coated with in fact the inner surface of the microscopic feature 200 with high depth-width ratio (for example, AR＞5) discernablely.In the exemplary embodiment, microscopic feature 200 can have between 5 to 15 the degree of depth and the depth-width ratio of diameter.Notice that conventional ionization PVD system can electroplate the inner surface that has higher than the microscopic feature of 10 depth-width ratio, still, these conventional systems move very expensive.On the contrary, exemplary embodiment can provide the economic alternative of ionization PVD method, and can effectively move to process the microscopic feature that has much larger than 10 depth-width ratio.
Refer now to Fig. 4, show flow chart, it has illustrated the method according to the disclosed exemplary embodiment of the application, and it affects adhering to the electro-deposition of Seed Layer 207 (referring to Fig. 3) by the conductive layer that realization is applied to the superpotential microscopic uniformity of deposition of each microscopic feature.Therefore, the feature 200 at substrate center place has been applied in the similar overvoltage of feature 200 with the substrate perimeter place.This can realize by the commercially available single anodization equipment such as " Stratus " of NEXX Systems Incorporated company.Fig. 5 is the schematic cross-sectional view of exemplary apparatus, and it is used for affecting at least a portion of the processing shown in Fig. 4.This embodiment for example can be used to process simultaneously two workpiece that for example kept by bilateral workpiece retainer 5018, although in alternate embodiment, equipment can be configured to only process single workpiece.Substantially, equipment can have main body 5200 ', and it comprises sidewall 5224 and end wall 5226, and shows agitation means 5204a and 5204b (for example septum), plate 5208 and the anode 5212 of positioned opposite.These elements and spacing and not drawn on scale.Although member 5204a and 5204b are illustrated as two isolating constructions, it can form single component.Described similar equipment in the Application No. 12/702,860 that is to submit on September 2nd, 2010, by reference its full content has been comprised in this manual.
In the illustrated embodiment, fluid by main body 5200 ' diapire at least one port 5228 enter main body 5200 '.In certain embodiments, port 5228 can be disposed in main body 5200 ' 5230 core.In one embodiment, port 5228 can be disposed in the bottom of sidewall 5224.Fluid is along the surperficial upper reaches of one or more workpiece.Fluid can at workpiece retainer 5018 and each member 5204, flow between 5204a or 5204b or between workpiece retainer 5018 and plate 5208.In different embodiment, fluid is by the top of main body, by the top of sidewall 5224, or by the top of end wall 5226 leave main body 5200 '.Arrow shows mobile roughly direction.
In the exemplary embodiment, anode 5212 can form the outer wall of main body 5200.In one embodiment, anode 5212 can be the parts of anode assemblies, and it has formed the outer wall of main body 5200.In different embodiment, main body 5200 has outer wall, and anode 5212 or anode assemblies be mounted to wall removedly, or separates with wall.
In the exemplary embodiment, anode 5212 can be the copper dish.In one embodiment, the exposed surface area of anode 5212 is about 300cm 2In one embodiment, anode 5212 is consumed during electro-deposition (or such as copper or solder deposition another fluid treatment).A feature of anode 5212 is, can easily it be removed or replace, and makes the manufacturing time of loss minimize.
Be appreciated that surface of the work plays negative electrode in the exemplary embodiment of using anode 5212.With reference to figure 4, be appreciated that in the exemplary embodiment again, the high sheet ratio of the etching hole (TSV) in workpiece 201 (referring to Fig. 3) as shown in the frame 401 of Fig. 4 can be outside being arranged in workpiece in electroplating device or before carry out.Similarly, above shown in the frame 402-403 of Fig. 4 can be outside being arranged in workpiece in electroplating device to the deposition of barrier layer 202 and thicker conductive layer 205 or before carry out.Also with reference to shown in Figure 3, the thicker conductive layer 205 that deposits on surface of the work is roughly even at the whole lip-deep thickness of the workpiece that deposits conductive layer 205 as mentioned above.Conductive layer 205 or roughly continuous at deposition position does not exist observable space or discontinuous (for example, not the existing the observable of depositing conducting layer 205 partly to be isolated from other parts of conductive layer) of cutting off conductive layer.As shown in Figure 3, in the exemplary embodiment, except one little (comparing coating self thickness) part of the hole inner wall surface that is positioned at the top opening part, hole wall surface keeps uncoated (not having observable conductive layer deposition) conductive layer.As shown in Fig. 4 center 404, can utilize electrodeposition apparatus shown in Figure 5 to realize above-mentioned to adhering to the electro-deposition of seed or overlay coating 207, it is covered with surface of the work fully, comprises the coating that lacks any Cu of can be observed PVD conductive layer or the surface of sedimental TSV inwall.As mentioned above, as shown in Fig. 4 center 404, seed or overlay coating 207 are applied directly on barrier layer 202 on the inwall of TSV.In the exemplary embodiment, can be in (deposition) step roughly (depositing from it the surface of Seed Layer) form the expectation final thickness that surface or Seed Layer 207 reach Seed Layer.As shown in Figure 3, overlay coating 207 is to carry out one deck that final surface is provided that the filling shown in the frame 405 of Fig. 4 is processed thereon.The equipment in exemplary embodiment shown in Figure 5 that is appreciated that also can comprise suitable controller (not shown), and it is connected to above-mentioned parts, and is suitable for operating equipment and affects shown in Figure 4 and at the corresponding part of processing described above.
As mentioned above, in the exemplary embodiment, eliminate the high-impedance behavior (can exist for " being located immediately on barrier " or " ultra-thin Seed Layer " type substrate) of substrate than thick copper layer, and provide roughly homogeneous conductivity to the whole microscopic features that spread all on workpiece.Therefore, can use to be called as the method that what is called " impacts (strike) " and processes, wherein use the chemical bath dilution to combine with using high electric overvoltage for ion, with the generation compact nucleus, provide thus adventitious deposit." impact " suitable examples of bathing open in the U.S. Patent number 3,684,666 of Shaw, by reference its full content is comprised in this manual.In the exemplary embodiment, impact processing and can use alkaline solution, its comprise every liter of about 96 gram citric acid, the CuCO of 20 every liter of gram 3Cu (OH) 2, wherein by increasing the NaOH operation, the pH value is adjusted to approximately 11.6 under the current density of 4 amperes every decimeter.With reference to figure 8a-8b, show the optical image of the cross section of the actual plated via that has and do not exist Cu PVD conductive layer again.Example is cut open to expose via hole to the Cu barrier interface of wafer.The image of left hand view 8 (a) shows the only similar processing on the TiN barrier, and the image of right part of flg 8 (b) has comprised according to above-mentioned exemplary embodiment and added Cu PVD conductive layer.As shown in the figure, plating Cu fails to arrive the via bottom in Fig. 8 (a) always.Utilize the tack test of drawstring method to show that the example in Fig. 8 (a) can be peeled off easily, there is not this problem in the example in Fig. 8 (b).
Compared to prior art (for example U.S. Patent number 7,115, and 196 disclosed Seed Layer are improved one's methods and equipment), the advantage of disclosed embodiment is very large, and this is to be convenient to because it provides the wider processing action pane that the business manufacturing is processed.With reference to figure 6, show the copper film that the conventional method direct plating on the high impedance substrate that utilizes the similar multizone anodization structure of describing with U.S. Patent number 7,115,196 has thicker profile.Although thickness evenness is not improved compared to using anode region to control, exist metal thickness to change, this also shows nuclear change, and the variation of the tack of copper film.As mentioned above, Fig. 7 shows the routine plating Cu wafer that directly is on barrier after testing tack through drawstring.As shown in the figure, in the conventional system that adopts anode region to control, be difficult to realize have the consistent plating of tack uniformly, cause thus at the center or fringe region realizes fully adhering to (other parts of illustrated substrate are deposited has relatively poor tack).Exemplary embodiment has solved this problem by being limited to the geometry yardstick that connects silicon via hole self to the required control of core and the tack of copper on barrier.In other words, disclosed embodiment has solved the problems referred to above by controlling electromotive force and control electromotive force on the 300mm surface of typical silicon substrate on the degree of depth of 0.1mm degree of depth microscopic feature, thus with problem reduction several orders of magnitude.
(for example be deposited into sufficient thickness in microscopic feature at layer of surface layer or Seed Layer 207, the about minimum thickness of 200 to 500 dusts) afterwards, substrate can be moved to routine " from bottom to top " type electroplating bath (frame 405 in Fig. 4), for example the DVF200 of Enthone Incorporated company.By the known method of industry, copper is filled in microscopic feature by electrochemistry.In the exemplary embodiment, can workpiece not annealed between seed layer deposition and follow-up filler deposition, this be because, apply the attachment characteristic of conductive layer due to known PVD, the disclosed embodiment of the application has advantageously guaranteed barrier on the flat surfaces of substrate and the reliable attachment between seed.For example the During Annealing after filling TSV can improve barrier on the TSV inner surface and the tack between Seed Layer.Because of the copper in the microscopic feature hole with respect to the thermal expansion of the expansion of substrate the compression that produces on the interface play improve the copper that applies in little impacting (microstrike) mode and the tack between barrier metals effect (for example, substrate can be silicon, and it has compared to the thermal coefficient of expansion of the copper of 18ppm/C is the about thermal coefficient of expansion of 4ppm/C).
In the exemplary embodiment, can affect kernel structure and the tack that impacts the seed layer deposition in microscopic feature during bath by apply deposition voltage with pulse mode.Particularly, positive voltage is applied to substrate or negative electrode, reaches the duration of 10 to 100 milliseconds, is not execute the alive disconnection period subsequently, is 20 to 1000 milliseconds.For example, disconnected/logical duration ratio can be approximately 2: 10, particularly, can use the duration ratio that breaks/lead to of 1: 4.In the exemplary embodiment, in case the Cu layer forms the bottom that arrives via hole continuously always, reduce electric current to optimize the kernel structure of Cu layer, to support the growth of the fine grained structure of electro-deposition Cu packing material in next step.
In one embodiment, provide the inner surface that is used for the microcosmic hole characteristic made in the general planar surface of workpiece to carry out electric plating method.the method comprises: workpiece is set to have barrier metals coating, its along the inner surface of the flat surfaces of workpiece and microcosmic hole characteristic both roughly continuously and evenly, wherein process (a substantially surface reaction limited process) by the restriction of surface reaction roughly and apply this barrier metals coating, workpiece is set to have the coating than thick metal layers on the flat surfaces of workpiece, it is anchored into barrier metals coating and is deposited to provide roughly electric conductivity uniformly to the microscopic feature that spreads all over workpiece, conductive coating setting to the workpiece periphery electrically contacts the path, workpiece is immersed chemical bath and make this chemical bath contact the inner surface of microcosmic hole characteristic fully, this chemical bath comprises the metal ion that is suitable for electro-deposition, and apply electromotive force with all surfaces substrates metal ion at the inner surface that comprises the microcosmic hole characteristic of workpiece at the periphery of workpiece, form thus predetermined surface coating in an electrodeposition step.In another embodiment, provide the semiconductor workpiece treatment facility that is used for making at workpiece microporous structure.Workpiece has the barrier film of the inner surface of the microporous structure that is applied to flat surfaces and workpiece, and metal level is deposited thereon and be anchored into barrier film.Equipment has the main body that defines for the chamber of workpiece.The chamber is configured and utilizes the processing fluid to infiltrate in advance workpiece, and this is processed fluid and form fluid and interface, metal surface between the inner surface of each microporous structure of processing fluid and flat surfaces and workpiece.Anode is disposed in the chamber with electroplating parts, anode is arranged to make to generate between workpiece and anode electroplates overvoltage, it is roughly even on workpiece, and impact is on the flat surfaces of workpiece and the metal electrodeposition that carries out on the inner surface of each microporous structure, makes the inner surface of each microporous structure have overlay coating for one deck coating.
Should be appreciated that above description is only to explanation of the present invention.Under the prerequisite that does not break away from spirit of the present invention, those skilled in the art can visualize various replacements and change.Therefore, the invention is intended to contain whole above-mentioned replacement, change and the variation that falls in the claims scope.

Claims (22)

1. method is used for the inner surface of the microcosmic hole characteristic made in the general planar surface of workpiece is carried out electric plating method, and described method comprises:
Workpiece is set having barrier metals coating, this barrier metals coating at the described inner surface of the described flat surfaces of workpiece and described microcosmic hole characteristic roughly continuously and is evenly wherein processed by surface reaction restriction roughly and is coated with described barrier metals coating;
Described workpiece is set to have the coating of thick metal layers on the described flat surfaces of described workpiece, this thick metal layers is anchored into described barrier metals coating, and is arranged such that the described microscopic feature that arranges on whole described workpiece has roughly conductivity uniformly;
Periphery at described workpiece is that the conductive coating setting electrically contacts the path;
Described workpiece is immersed chemical bath, and make described chemical bath contact the described inner surface of described microcosmic hole characteristic fully, described chemical bath comprises the metal ion that is suitable for electro-deposition; And
Described periphery at described workpiece applies voltage, so that the metal ion electro-deposition to all surfaces of described workpiece, is included in the described inner surface that forms the described microcosmic hole characteristic of predetermined surface coating in an electrodeposition step.
2. the method for claim 1, wherein be coated with described conductive coating by plasma vapor deposition (PVD).
3. the method for claim 1, wherein described conductive coating is applied to the described inner surface of described microscopic feature in ND mode.
4. the method for claim 1, wherein described conductive coating is thickness between the about copper layer of 2000 to 5000 dusts.
5. the method for claim 1, wherein described conductive coating is that thickness is the copper layer of approximately 5000 dusts.
6. the method for claim 1, wherein described conductive coating is that thickness is the copper layer of approximately 3000 dusts.
7. the method for claim 1, wherein described barrier metals coating is thickness between approximately titanium or the titanium tungsten adhesion layer of 500 to 2000 dusts.
8. the method for claim 1, wherein described barrier metals coating is that thickness is titanium or the titanium tungsten adhesion layer of approximately 1000 dusts.
9. the method for claim 1, wherein described microcosmic hole characteristic is the aperture between approximately 1 micron to 20 microns and the degree of depth between the about hole of 10 microns to 250 microns.
10. the method for claim 1, wherein described microcosmic hole characteristic is that diameter is that approximately 5 microns and the degree of depth are the about circular hole of 50 microns.
11. the method for claim 1, wherein described microcosmic hole characteristic is the aperture between approximately 1 micron to 20 microns and the degree of depth between the about non-circular hole of 10 microns to 250 microns.
12. the method for claim 1, wherein described barrier metals coating is titanium nitride, tantalum nitride, tungsten, nickel, titanium, tantalum, or the combination of these metals.
13. the method for claim 1, wherein deposit described barrier metals coating by vapor process.
14. the method for claim 1, wherein deposit described barrier metals coating by wet-chemical treatment.
15. the method for claim 1, wherein periodically apply described voltage in order to deposit, the duration that wherein applies described voltage is approximately 50 milliseconds, and the duration that does not apply described voltage is approximately 100 milliseconds.
16. semiconductor workpiece treatment facility, be used for making microporous structure at workpiece, described workpiece has the barrier film of the inner surface of the flat surfaces that is applied to described workpiece and microporous structure, and have the metal level that is deposited on described barrier film and is anchored into described barrier film, described equipment comprises:
Housing, define the process chamber for described workpiece, described chamber is configured to utilize to process fluid makes described workpiece wetting in advance, and described processing fluid forms fluid and the interface, metal surface between the inner surface of the described flat surfaces of described processing fluid and described workpiece and each microporous structure; And
Anode, it is arranged in be used in the described chamber of electroplating described workpiece, described anode is arranged and makes, on the inner surface of the described flat surfaces of described workpiece and each microporous structure, by the electro-deposition fluid, in the plating overvoltage that is created on described whole workpiece roughly uniformly, affects the electro-deposition of metal between described workpiece and described anode, make thus the described inner surface of each microporous structure have overlay coating as one deck coating.
17. equipment as claimed in claim 16, wherein, described barrier film is titanium nitride, tantalum nitride, tungsten, nickel, titanium, tantalum, or the combination of these metals.
18. equipment as claimed in claim 16, wherein, described metal level is to be formed on thick metal layers on described workpiece by physical vapor deposition.
19. equipment as claimed in claim 16, wherein, described wetting in advance be that vacuum is wetting in advance.
20. equipment as claimed in claim 16, wherein, described plating fluid comprises the copper electroplating solution.
21. equipment as claimed in claim 16 also comprises energy source, it can be connected to the described workpiece in described chamber, be used to described workpiece energy supply, and comprising controller, it is connected to described energy source, and is suitable for producing between described workpiece and described anode roughly overvoltage uniformly.
22. equipment as claimed in claim 16, wherein, the described workpiece almost parallel that keeps in described anode and described chamber.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109019504A (en) * 2018-06-22 2018-12-18 北京时代民芯科技有限公司 A kind of new producing method of the adjustable interconnection through silicon via of resistance

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130249047A1 (en) * 2012-03-26 2013-09-26 Nanya Technology Corporation Through silicon via structure and method for fabricating the same
US8791005B2 (en) * 2012-06-18 2014-07-29 International Business Machines Corporation Sidewalls of electroplated copper interconnects
US10157792B2 (en) * 2016-10-27 2018-12-18 Nxp Usa, Inc. Through substrate via (TSV) and method therefor
US10707151B2 (en) * 2018-11-20 2020-07-07 Nanya Technology Corporation Through silicon via structure and method for manufacturing the same
CN114921821B (en) * 2022-04-14 2023-05-16 电子科技大学 Electroplating device for filling holes of through holes and TGV/TCV hole metallization method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6136707A (en) * 1999-10-02 2000-10-24 Cohen; Uri Seed layers for interconnects and methods for fabricating such seed layers
US20060208272A1 (en) * 1998-02-04 2006-09-21 Semitool, Inc. Method for filling recessed micro-structures with metallization in the production of a microelectronic device
US20070072417A1 (en) * 2005-09-28 2007-03-29 Hiroki Nakamura Method for forming wiring structure, wiring structure, method for forming semiconductor device, and display device
US20080038918A1 (en) * 2001-10-16 2008-02-14 Canon Kabushiki Kaisha Semiconductor device and method for manufacturing the same

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3684666A (en) 1970-03-19 1972-08-15 Pfizer & Co C Copper electroplating in a citric acid bath
US5246565A (en) 1992-05-07 1993-09-21 The United States Of America As Represented By The United States Department Of Energy High adherence copper plating process
US5597412A (en) * 1995-02-15 1997-01-28 Fujitsu Limited Apparatus for forcing plating solution into via openings
TWI223678B (en) * 1998-03-20 2004-11-11 Semitool Inc Process for applying a metal structure to a workpiece, the treated workpiece and a solution for electroplating copper
US6197181B1 (en) 1998-03-20 2001-03-06 Semitool, Inc. Apparatus and method for electrolytically depositing a metal on a microelectronic workpiece
US6565729B2 (en) 1998-03-20 2003-05-20 Semitool, Inc. Method for electrochemically depositing metal on a semiconductor workpiece
US6497801B1 (en) 1998-07-10 2002-12-24 Semitool Inc Electroplating apparatus with segmented anode array
US6773571B1 (en) 2001-06-28 2004-08-10 Novellus Systems, Inc. Method and apparatus for uniform electroplating of thin metal seeded wafers using multiple segmented virtual anode sources
EP1029948A2 (en) * 1999-02-19 2000-08-23 Applied Materials, Inc. Using electroplated cu as cold layer for cold/hot deposition
KR20010015297A (en) * 1999-07-12 2001-02-26 조셉 제이. 스위니 Electrochemical deposition for high aspect ratio structures using electrical pulse modulation
US6413858B1 (en) 1999-08-27 2002-07-02 Micron Technology, Inc. Barrier and electroplating seed layer
US6610151B1 (en) * 1999-10-02 2003-08-26 Uri Cohen Seed layers for interconnects and methods and apparatus for their fabrication
WO2001031671A1 (en) 1999-10-26 2001-05-03 Stellar Display Corporation Method of fabricating a field emission device with a lateral thin-film edge emitter
US6660153B2 (en) 2000-10-20 2003-12-09 Shipley Company, L.L.C. Seed layer repair bath
US6881318B2 (en) * 2001-07-26 2005-04-19 Applied Materials, Inc. Dynamic pulse plating for high aspect ratio features
WO2003060959A2 (en) * 2002-01-10 2003-07-24 Semitool, Inc. Method for applying metal features onto barrier layers using electrochemical deposition
US6518184B1 (en) * 2002-01-18 2003-02-11 Intel Corporation Enhancement of an interconnect
US6861355B2 (en) * 2002-08-29 2005-03-01 Micron Technology, Inc. Metal plating using seed film
US6974531B2 (en) 2002-10-15 2005-12-13 International Business Machines Corporation Method for electroplating on resistive substrates
DE10314502B4 (en) * 2003-03-31 2008-06-12 Advanced Micro Devices, Inc., Sunnyvale Process for the electrolytic coating of a semiconductor structure
CN1920105B (en) 2003-10-22 2010-12-08 内克斯***公司 Method and apparatus for fluid processing a workpiece
US20060163055A1 (en) 2005-01-27 2006-07-27 International Business Machines Corporation Apparatus for direct plating on resistive liners
KR100675280B1 (en) * 2005-06-22 2007-01-29 삼성전자주식회사 Selective copper alloy interconnections in semiconductor devices and methods of forming the same
US20080111237A1 (en) 2006-11-14 2008-05-15 Texas Instruments Incorporated Semiconductor device manufactured using an electrochemical deposition process for copper interconnects
US20080149490A1 (en) * 2006-12-26 2008-06-26 Bonhote Christian R Electroplating on ultra-thin seed layers
US7928574B2 (en) * 2007-08-22 2011-04-19 Texas Instruments Incorporated Semiconductor package having buss-less substrate
US8425687B2 (en) * 2009-02-10 2013-04-23 Tel Nexx, Inc. Wetting a workpiece surface in a fluid-processing system
US20100206737A1 (en) * 2009-02-17 2010-08-19 Preisser Robert F Process for electrodeposition of copper chip to chip, chip to wafer and wafer to wafer interconnects in through-silicon vias (tsv)

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060208272A1 (en) * 1998-02-04 2006-09-21 Semitool, Inc. Method for filling recessed micro-structures with metallization in the production of a microelectronic device
US6136707A (en) * 1999-10-02 2000-10-24 Cohen; Uri Seed layers for interconnects and methods for fabricating such seed layers
US20080038918A1 (en) * 2001-10-16 2008-02-14 Canon Kabushiki Kaisha Semiconductor device and method for manufacturing the same
US20070072417A1 (en) * 2005-09-28 2007-03-29 Hiroki Nakamura Method for forming wiring structure, wiring structure, method for forming semiconductor device, and display device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109019504A (en) * 2018-06-22 2018-12-18 北京时代民芯科技有限公司 A kind of new producing method of the adjustable interconnection through silicon via of resistance
CN109019504B (en) * 2018-06-22 2020-02-21 北京时代民芯科技有限公司 Manufacturing method of interconnected silicon through hole with adjustable resistance

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