CN103094086B - CMOS formation method - Google Patents
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- CN103094086B CN103094086B CN201110338882.9A CN201110338882A CN103094086B CN 103094086 B CN103094086 B CN 103094086B CN 201110338882 A CN201110338882 A CN 201110338882A CN 103094086 B CN103094086 B CN 103094086B
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Abstract
A kind of CMOS formation method, comprising: the semiconductor substrate surface at described first area and second area forms gate dielectric layer; Gate dielectric layer surface in described first area forms the first polysilicon layer, form the second polysilicon layer, and described the first polysilicon layer thickness is thicker than described the second polysilicon layer thickness on the gate dielectric layer surface of described first area; Dielectric layer in described semiconductor substrate surface formation with described the second polysilicon layer flush; At described dielectric layer forming metal layer on surface, and described metal level covers described the first polysilicon layer and described the second polysilicon layer; Adopt annealing process to form the first metal silicide layer in described the first polysilicon layer, in described the second polysilicon layer, form the second metal silicide layer, and the metal molar percentage of the first metal silicide layer is less than the metal molar percentage of the second metal silicide layer. The properties of product that the present embodiment forms are good.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly a kind of CMOS formation method.
Background technology
CMOS (CMOS) transistor is the elementary cell in modem logic circuit,Wherein comprise PMOS and NMOS, and each PMOS (NMOS) transistor is positioned on dopant well,And all by the substrate of grid (Gate) both sides between p-type (N-shaped) utmost point/drain region and source area and drain regionPassage (Channel) form.
Along with the continuous progress of CMOS technology, metal gate electrode technology is applied to CMOS and manufactures to overcome and mixThe negative effect that assorted polysilicon produces, described negative effect comprises: the loss of gate electrode, high impedance, withAnd gate electrode and the dielectric incompatibility of high-K gate.
Because every kind of metal Ying Yu can have unique work function in MOS device, described work function is shadowRing the critical material parameter of device threshold voltage. Described work function refers to electronics in solid phase atom from FermiEnergy shift is to the required energy level of valence band. Ideally, in territory, nmos area, the fermi level value of metal gate existsNear the conduction band of silicon, and the fermi level value of metal gate in PMOS region is near the valence band of silicon. CauseThis, prior art is used the double-metal grid that contains different metal conventionally.
But double-metal grid need to adopt different metals to NMOS and PMOS, complex process, forThis, in the Chinese patent document that is CN10149654A, disclose a kind of fully silicided gate electrodes shape at publication numberOne-tenth method, the method adopts different silicide phases to control effective merit of PMOS and nmos pass transistorFunction, thus the threshold voltage that NMOS and PMOS are all applicable to obtained.
But above-mentioned fully silicided gate electrodes formation method complex process and the product yield of formation is low, productCan be low.
Summary of the invention
The problem that the present invention solves is to provide that a kind of to form method technique product yield simply assorted and that form highCMOS formation method.
For addressing the above problem, the invention provides a kind of CMOS formation method, comprising: semiconductor is providedSubstrate, described Semiconductor substrate comprises first area and the second area relative with first area; DescribedThe described semiconductor substrate surface of first area and second area forms gate dielectric layer; In described first areaGate dielectric layer surface form the first polysilicon layer, form the on the gate dielectric layer surface of described first areaTwo polysilicon layers, and described the first polysilicon layer thickness is thicker than described the second polysilicon layer thickness; DescribedSemiconductor substrate surface forms the dielectric layer with described the second polysilicon layer flush; At described dielectric layerForming metal layer on surface, and described metal level covers described the first polysilicon layer and described the second polysilicon layer;Adopt annealing process to form the first metal silicide layer in described the first polysilicon layer, described more than secondIn crystal silicon layer, form the second metal silicide layer, and the metal molar percentage of the first metal silicide layer is littleIn the metal molar percentage of the second metal silicide layer.
Optionally, Thickness Ratio and first metal silicide of described the first polysilicon layer and the second polysilicon layerLayer is corresponding with the ratio of the metal molar percentage of the second metal silicide layer.
Optionally, the thickness of described the first polysilicon layer is 1.5 to 3 times of thickness of the second polysilicon layer.
Optionally, the thickness of the first polysilicon layer is 80nm to 120nm.
Optionally, the thickness of the second polysilicon layer is 30nm to 60nm.
Optionally, described metal layer material is nickel, cobalt, titanium or platinum.
Optionally, the thickness of described metal level is 40nm to 80nm.
Optionally, the thickness of described the first polysilicon layer is 0.55 to 0.8 with described metal layer thickness ratio.
Optionally, the thickness of described the second polysilicon layer is 1.1 to 2.0 with described metal layer thickness ratio.
Optionally, the material of the first metal silicide layer is NiSi.
Optionally, the material of the second metal silicide layer is Ni2Si or Ni3Si。
Optionally, described annealing process is rapid thermal anneal process.
Optionally, the parameter of described annealing process is: adopt rapid thermal anneler, annealing temperature is 200DEG C to 350 DEG C.
Optionally, also comprise: remove unreacted metal level, and to the first metal silicide layer and secondMetal silicide layer annealing.
Optionally, to the technological parameter of the first metal silicide layer and the annealing of the second metal silicide layer be:Annealing temperature is 300 DEG C to 600 DEG C.
Compared with prior art, the present invention has the following advantages: the present embodiment adopts first area and theTwo regions form different the first polysilicon layer and described the second polysilicon layers of thickness, then form and cover instituteState the metal level of the first polysilicon and the second polysilicon, adopt a step annealing technique, simultaneously in first areaForm the different metal silicide layer of molar percentage with second area, saved processing step, and this realityExecuting example does not need multistep deposition and etching, has protected product not to be subject to too much damage, the properties of product of formationGood.
Brief description of the drawings
Fig. 1 is the schematic flow sheet of the CMOS formation method of the embodiment of the present invention;
Fig. 2 to Figure 10 is the process generalized section of the CMOS formation method of the embodiment of the present invention.
Detailed description of the invention
In prior art, adopt different silicide phases to control having of PMOS and nmos pass transistorEffect work function, the metal gates that replaces NMOS and PMOS adopts different metals; But, thisThe technique that bright inventor forms different silicide phases to prior art is studied, and finds: existingConventionally first in a certain region, (NMOS or PMOS) forms the first phase silicide to technology, then separatelyOne region (PMOS or NMOS) forms the second phase silicide, owing to forming different silicidesPhase need to be carried out deposition-etch technique repeatedly, such as form need to be to many when the first phase silicideThe first remaining phase silicide carries out etching removal, form the second phase silicide need to be to unnecessary theTwo phase silicides carry out etching removal, remove in technique more easily to product formation in above-mentioned multiple etchingEtching injury.
For this reason, the present inventor proposes a kind of CMOS formation method, please refer to Fig. 1, comprise asLower step:
Step S101, provides Semiconductor substrate, described Semiconductor substrate comprise first area and with the firstth districtThe second area that territory is relative;
Step S102, forms grid at the described semiconductor substrate surface of described first area and second area and is situated betweenMatter layer; Gate dielectric layer surface in described first area forms the first polysilicon layer, in described first areaGate dielectric layer surface form the second polysilicon layer, and described the first polysilicon layer thickness is thicker than described secondPolysilicon layer thickness;
Step S103, forms with described the second polysilicon layer flush at described semiconductor substrate surfaceDielectric layer;
Step S104, at described dielectric layer forming metal layer on surface, and described metal level covers described firstPolysilicon layer and described the second polysilicon layer;
Step S105, adopts annealing process to form the first metal silicide layer in described the first polysilicon layer,In described the second polysilicon layer, form the second metal silicide layer, and the metal of the first metal silicide layerMolar percentage is less than the metal molar percentage of the second metal silicide layer.
Step S106, removes unreacted metal level, and to the first metal silicide layer and the second metallic siliconCompound layer annealing.
Particularly, described first area is NMOS or PMOS region, and described second area is PMOSOr territory, nmos area, the adjacent or interval of described first area and second area.
The Thickness Ratio of described the first polysilicon layer and the second polysilicon layer and the first metal silicide layer and secondThe ratio correspondence of the metal molar percentage of metal silicide layer, the wherein metal molar of metal silicide layerPercentage is the molar percentage of metal and silicon in metal silicide.
Described metal layer material is nickel, cobalt, titanium or platinum.
Preferably, described the first metal silicide layer material is NiSi, described the second metal silicide layer materialMaterial is Ni2Si or Ni3Si。
The present embodiment adopts in first area and forms different the first polysilicon layer and the institutes of thickness with second areaState the second polysilicon layer, then form the metal level that covers described the first polysilicon and the second polysilicon, adoptBy a step annealing technique, form the different metallic silicon of molar percentage in first area with second area simultaneouslyCompound layer, has saved processing step, and the present embodiment do not need multistep deposition and etching, has protected productBe not subject to too much damage, the properties of product of formation are good.
Be territory, nmos area below taking first area, second area is that PMOS region is to enforcement of the present inventionExample is described in detail.
Please refer to Fig. 2, Semiconductor substrate 100 is provided, described Semiconductor substrate 100 comprises first area IWith the second area II relative with first area I.
Described Semiconductor substrate 100 is used to subsequent technique that platform is provided, and described Semiconductor substrate 100 canTo be selected from the substrates such as the silicon (SOI) on N-type silicon substrate, P type silicon substrate, insulating barrier. Described semiconductorSubstrate 100 is 300mm silicon chip or 450mm silicon chip;
Described Semiconductor substrate 100 comprises first area I and the second area II relative with first area I,In the present embodiment, described first area I is territory, nmos area, and second area is PMOS region; InstituteState between first area I and second area II and adopt isolation structure isolation, described isolation structure is LOCOSOr be fleet plough groove isolation structure (STI), in the present embodiment, described isolation structure is shallow trench isolation junctionStructure.
Correspondingly, the first area I of described Semiconductor substrate 100 has P type dopant well (not shown),The second area II of described Semiconductor substrate 100 has N-type dopant well (not shown).
Please also refer to Fig. 3-Fig. 6, in the described Semiconductor substrate of described first area I and second area II100 surfaces form gate dielectric layer 110; Gate dielectric layer 110 surfaces at described first area I form firstPolysilicon layer 121, forms the second polysilicon layer 122 on gate dielectric layer 110 surfaces of described second area II,And described the first polysilicon layer 121 thickness are thicker than described the second polysilicon layer 122 thickness.
Please refer to Fig. 3, form silicon oxide layer 111, described silica on described Semiconductor substrate 100 surfacesThe formation technique of layer is depositing operation or thermal oxidation technology.
Please refer to Fig. 4, form polysilicon layer 120 on described silicon oxide layer 111 surfaces, at first area IInterior polysilicon layer 120 surfaces form photoresist layers (not shown), taking described photoresist layer as mask, carveLose described polysilicon layer 120 until remove the polysilicon layer on the second area II surface of segment thickness, makePolysilicon layer thickness in the I of first area is thicker than the polysilicon layer thickness in second area II.
It should be noted that the Thickness Ratio of described the first polysilicon layer and the second polysilicon layer and follow-up formationThe first metal silicide layer corresponding with the ratio of the metal molar percentage of the second metal silicide layer, fromAnd the first metal silicide layer of formation and the metal molar percentage of the second metal silicide layer are metProduct demand.
More preferably, described polysilicon layer 120 thickness in the I of first area are many in second area II1.5 to 3 times of crystal silicon layer 120 thickness, above-mentioned thickness can make subsequent technique at first area I andSecond area II forms the metal silicide layer of coupling NMOS and PMOS.
Remove after photoresist layer, form hard mask layer 130, described hard mask on described polysilicon 120 surfacesLayer 130 material are silicon nitride.
Please refer to Fig. 5 and Fig. 6, form photoetching offset plate figure (not shown) on described hard mask layer 130 surfaces,Described photoetching offset plate figure is corresponding with the gate patterns of NMOS and PMOS, with described photoetching offset plate figure for coveringFilm, hard mask layer 130, polysilicon layer 120 and silicon oxide layer 111, lead until expose partly described in etchingBody substrate 100, forms on described Semiconductor substrate 100 surfaces of described first area I and second area IIGate dielectric layer 110; Gate dielectric layer 110 surfaces at described first area I form the first polysilicon layer 121,Gate dielectric layer 110 surfaces at described second area II form the second polysilicon layer 122, and described more than firstCrystal silicon layer 121 thickness are thicker than described the second polysilicon layer 122 thickness.
Concrete, the thickness of described the first polysilicon layer 121 is 80nm to 120nm, described the second polycrystallineThe thickness of silicon layer is 30nm to 60nm.
Please, still with reference to figure 6, forming gate dielectric layer 110, the first polysilicon layer 121 and the second polysiliconAfter layer 122, can also be on Semiconductor substrate 100 surfaces, more than second of the first polysilicon layer 121 both sidesSemiconductor substrate 100 surfaces of crystal silicon layer 122 both sides form side wall.
Can also in the Semiconductor substrate of the first polysilicon layer 121 both sides, form source area and drain region,And form source area and drain region in described the second polysilicon layer 122 semiconductor substrates on two sides, andIn source area and drain region, form metal silicide layer.
Please refer to Fig. 7 and Fig. 8, form and described the second polysilicon layer on described Semiconductor substrate 100 surfacesThe dielectric layer 140 of 122 flush.
Please refer to Fig. 6, remove described hard mask layer 130, the technique of described removal hard mask layer 130 is for wetMethod or dry removal processes, here repeat no more.
Adopt depositing operation at described Semiconductor substrate 100 surface deposition dielectric films 141, described medium is thinFilm 141 covers described the first polysilicon layer 121 and the second polysilicon layer 122.
Described depositing operation is chemical vapor deposition method, and the material of described dielectric film 141 is silicaOr low k dielectric materials.
Please refer to Fig. 7 and Fig. 8, adopt dielectric film 141 described in CMP process planarization, straightTo exposing described the first polysilicon layer 121, then photoresist is protected described the first polysilicon layer 121, adoptsWith dielectric film 141 described in time etching technics etching, until expose described the second polysilicon layer 122, shapeBecome dielectric layer 140.
Please refer to Fig. 8, at described dielectric layer 140 forming metal layer on surfaces 150, and described metal level 150Cover described the first polysilicon layer 121 and described the second polysilicon layer 122.
Described metal level 150 for described the first polysilicon layer 121 and described the second polysilicon layer 122Reaction forms metal silicide.
Described metal level 150 materials are nickel, cobalt, titanium or platinum, described metal layer thickness be 40nm extremely80nm。
The formation technique of described metal level 150 is physical vapour deposition (PVD) or chemical vapour deposition (CVD).
Also it should be noted that: because the formation technique of described metal level 150 is physical vapour deposition (PVD) or changeLearn vapour deposition, be formed on the metal of described the first polysilicon layer 121 and described the second polysilicon layer 122Layer 150 consistency of thickness, thus in subsequent step described first polysilicon layer 121 Hes different from thicknessDescribed the second polysilicon layer 122 forms the metal silicide layer of different mol ratio.
Please refer to Fig. 9 and Figure 10, adopt annealing process in the interior formation first of described the first polysilicon layer 121Metal silicide layer 151, at interior formation the second metal silicide layer 152 of described the second polysilicon layer 122,And the metal molar percentage of the first metal silicide layer 151 is less than the gold of the second metal silicide layer 152Belong to molar percentage.
Described annealing process is rapid thermal anneal process (RapidThermalAnnealing, RTA), concreteGround, described annealing process design parameter is: adopt rapid thermal anneler, annealing temperature be 200 DEG C to 350℃。
It should be noted that, thick owing to having formed described the first polysilicon layer 121 thickness in step beforeIn the metal level 150 of described the second polysilicon layer 122 thickness and thickness homogeneous, the polysilicon layer of different-thicknessWith the metal level 150 of same thickness, thereby form the different metal silicide layer of metal molar percentage.
In one embodiment, the thickness of described the first polysilicon layer 121 and described metal level 150 Thickness RatiosBe 0.55 to 0.8, the thickness of described the second polysilicon layer 122 and described metal level 150 Thickness Ratios are 1.1To 2.0 o'clock, can form the preferably different metal silicide layer of metal molar percentage.
In the present embodiment, because described the first polysilicon layer 121 thickness are thicker than described the second polysilicon layer122 thickness, the metal molar percentage of the first metal silicide layer 151 of formation is less than the second metal silicationThe metal molar percentage of thing layer 152.
In another embodiment, do exemplary illustrated taking described metal layer material as nickel, described in the firstth districtDescribed the first polysilicon layer 121 thickness in the I of territory are that the second polysilicon layer 122 in second area II is thickDegree 1.5 to 3 times, the thickness of described the first polysilicon layer 121 and described metal level 150 Thickness Ratios are0.55 to 0.8, the thickness of described the second polysilicon layer 122 and described metal level 150 Thickness Ratios be 1.1 to2.0 o'clock, after annealing process, first metallic silicon that can be NiSi in territory, nmos area forming componentCompound layer 151 is Ni in PMOS region forming component2Si or Ni3The second metal silicide layer 152 of Si,And the work function of NiSi meets the requirement of NMOS, Ni2Si or Ni3The work function of Si meets PMOS'sRequirement.
It should be noted that, the present embodiment adopt primary depositing and annealing process to form to meet NMOS andThe metal silicide layer of PMOS demand, saves processing step.
Please refer to Figure 10, remove unreacted metal level 150, and to the first metal silicide layer 151 HesThe second metal silicide layer 152 is annealed.
Described annealing process is high-temperature thermal annealing, for stablizing the first metal silicide layer 151 and the second gold medalBelong to silicide layer 152.
Described annealing process design parameter is: adopt rapid thermal anneler, annealing temperature be 300 DEG C to 600℃。
The present embodiment adopts in first area and forms different the first polysilicon layer and the institutes of thickness with second areaState the second polysilicon layer, then form the metal level that covers described the first polysilicon and the second polysilicon, adoptBy a step annealing technique, form the different metallic silicon of molar percentage in first area with second area simultaneouslyCompound layer, has saved processing step, and the present embodiment do not need multistep deposition and etching, has protected productBe not subject to too much damage, the properties of product of formation are good.
Although the present invention with preferred embodiment openly as above, it is not for limiting the present invention, Ren HebenThose skilled in the art without departing from the spirit and scope of the present invention, can utilize the method for above-mentioned announcementWith technology contents, technical solution of the present invention is made to possible variation and amendment, therefore, every the disengaging originallyThe content of invention technical scheme, that according to technical spirit of the present invention, above embodiment is done is any simpleAmendment, equivalent variations and modification, all belong to the protection domain of technical solution of the present invention.
Claims (15)
1. a CMOS formation method, is characterized in that, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate comprises first area and relative with first areaTwo regions;
Described semiconductor substrate surface at described first area and second area forms gate dielectric layer; InstituteThe gate dielectric layer surface of stating first area forms the first polysilicon layer, at the gate dielectric layer of described second areaSurface forms the second polysilicon layer, and described the first polysilicon layer thickness is thicker than described the second polysilicon bed thicknessDegree;
Form after described the first polysilicon layer and the second polysilicon layer, form at described semiconductor substrate surfaceDielectric layer with described the second polysilicon layer flush; The formation method of described dielectric layer comprises: adoptDepositing operation is at described semiconductor substrate surface deposition medium film, and described dielectric film covers described firstPolysilicon layer and the second polysilicon layer; Dielectric film described in the planarization of employing CMP process is straightTo exposing described the first polysilicon layer, then photoresist is protected described the first polysilicon layer, adopts back quarterDielectric film described in etching technique etching, until expose described the second polysilicon layer, forms described dielectric layer;At described dielectric layer forming metal layer on surface, and described metal level cover described the first polysilicon layer and described inThe second polysilicon layer;
Adopt a step annealing technique that described the first polysilicon layer is all metallized and form the first metal silicideLayer, all metallizes described the second polysilicon layer and forms the second metal silicide layer, and the first metallic siliconThe metal molar percentage of compound layer is less than the metal molar percentage of the second metal silicide layer.
2. CMOS formation method as claimed in claim 1, is characterized in that, described the first polysilicon layer withThe metal molar of the Thickness Ratio of the second polysilicon layer and the first metal silicide layer and the second metal silicide layerThe ratio correspondence of percentage.
3. CMOS formation method as claimed in claim 1, is characterized in that, described the first polysilicon layerThickness is 1.5 to 3 times of thickness of the second polysilicon layer.
4. CMOS formation method as claimed in claim 1, is characterized in that, the thickness of the first polysilicon layerFor 80nm to 120nm.
5. CMOS formation method as claimed in claim 1, is characterized in that, the thickness of the second polysilicon layerFor 30nm to 60nm.
6. CMOS formation method as claimed in claim 1, is characterized in that, described metal layer material be nickel,Cobalt, titanium or platinum.
7. CMOS formation method as claimed in claim 6, is characterized in that, the thickness of described metal level is40nm to 80nm.
8. CMOS formation method as claimed in claim 6, is characterized in that, described the first polysilicon layerThickness is 0.55 to 0.8 with described metal layer thickness ratio.
9. CMOS formation method as claimed in claim 6, is characterized in that, described the second polysilicon layerThickness is 1.1 to 2.0 with described metal layer thickness ratio.
10. CMOS formation method as claimed in claim 1, is characterized in that, the first metal silicide layerMaterial is NiSi.
11. CMOS formation methods as claimed in claim 1, is characterized in that, the second metal silicide layerMaterial is Ni2Si or Ni3Si。
12. CMOS formation methods as claimed in claim 1, is characterized in that, described annealing process is quickThermal anneal process.
13. CMOS formation methods as claimed in claim 12, is characterized in that the ginseng of described annealing processNumber is: adopt rapid thermal anneler, annealing temperature is 200 DEG C to 350 DEG C.
14. CMOS formation methods as claimed in claim 1, is characterized in that, also comprise: remove unreactedMetal level, and to the annealing of the first metal silicide layer and the second metal silicide layer.
15. CMOS formation methods as claimed in claim 14, is characterized in that, to the first metal silicideThe technological parameter of layer and the annealing of the second metal silicide layer is: annealing temperature is 300 DEG C to 600 DEG C.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101317272A (en) * | 2005-11-28 | 2008-12-03 | 日本电气株式会社 | Semiconductor device and method for manufacturing same |
| CN101496154A (en) * | 2006-07-28 | 2009-07-29 | 国际商业机器公司 | Fully silicided gate electrodes and method of making the same |
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| US7151023B1 (en) * | 2005-08-01 | 2006-12-19 | International Business Machines Corporation | Metal gate MOSFET by full semiconductor metal alloy conversion |
| JP2007081249A (en) * | 2005-09-15 | 2007-03-29 | Matsushita Electric Ind Co Ltd | Semiconductor device and method for manufacturing the same |
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| CN101317272A (en) * | 2005-11-28 | 2008-12-03 | 日本电气株式会社 | Semiconductor device and method for manufacturing same |
| CN101496154A (en) * | 2006-07-28 | 2009-07-29 | 国际商业机器公司 | Fully silicided gate electrodes and method of making the same |
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