CN103094086A - Formation method of complementary metal oxide semi-conductor transistor (CMOS) - Google Patents
Formation method of complementary metal oxide semi-conductor transistor (CMOS) Download PDFInfo
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Abstract
Disclosed is a formation method of a complementary metal oxide semi-conductor transistor (CMOS). The formation method of the CMOS comprises that a gate medium layer is formed on the surface of a semi-conductor substrate of a first sector and a second sector. A first polycrystalline silicon layer is formed on the surface of the gate medium layer in the first sector. A second polycrystalline silicon layer is formed on the surface of the gate medium layer in the second sector. The thickness of the first polycrystalline silicon layer is thicker than the thickness of the second polycrystalline silicon layer. A medium layer is formed on the surface of the semi-conductor substrate and is level with the surface of the second polycrystalline silicon layer. A metal layer is formed on the surface of the medium layer. The first polycrystalline silicon layer and the second polycrystalline silicon layer are covered by the metal layer. A first metal silicide layer is formed in the first polycrystalline silicon layer by using the annealing technology. A second metal silicide layer is formed in the second polycrystalline silicon layer. Mole percent of the metal of the first metal silicon layer is smaller than the mole percent of the metal of the second metal silicon layer. Performance of the formed product is good.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly a kind of CMOS formation method.
Background technology
CMOS (Complementary Metal Oxide Semiconductor) (CMOS) transistor is the elementary cell in the modem logic circuit, wherein comprise PMOS and NMOS, and each PMOS (NMOS) transistor is positioned on dopant well, and all is made of the passage (Channel) between p-type (N-shaped) utmost point/drain region and source area and drain region in the substrate of grid (Gate) both sides.
Along with the continuous progress of CMOS technology, the metal gate electrode technology is applied to CMOS and makes to overcome the negative effect that doped polycrystalline silicon produces, and described negative effect comprises: the dielectric incompatibility of the loss of gate electrode, high impedance and gate electrode and high-K gate.
Unique work function all can be arranged in the MOS device due to every kind of metal Ying Yu, and described work function is the critical material parameter that affects device threshold voltage.Described work function refers to electronics in the solid phase atom is moved to the required energy level of valence band from Fermi level.Ideally, in the nmos area territory near the conduction band of Fermi level value at silicon of metal gate, and near the valence band of Fermi level value at silicon of the metal gate in the PMOS zone.Therefore, prior art is used the double-metal grid that contains different metal usually.
But, double-metal grid need to adopt different metals with PMOS to NMOS, complex process, for this reason, be in the Chinese patent file of CN 10149654A at publication number, disclose a kind of fully silicided gate electrodes formation method, the method adopts different silicide phases controlling the effective work function of PMOS and nmos pass transistor, thereby obtains threshold voltage that NMOS and PMOS all are fit to.
But above-mentioned fully silicided gate electrodes formation method complex process and the product yield of formation is low, properties of product are low.
Summary of the invention
The problem that the present invention solves is to provide a kind of high CMOS formation method of product yield that method technique is simply assorted and form that forms.
For addressing the above problem, the invention provides a kind of CMOS formation method, comprising: Semiconductor substrate is provided, and described Semiconductor substrate comprises first area and the second area relative with the first area; Described semiconductor substrate surface at described first area and second area forms gate dielectric layer; Gate dielectric layer surface formation the first polysilicon layer in described first area, gate dielectric layer surface formation the second polysilicon layer in described first area, and described the first polysilicon layer thickness is thicker than described the second polysilicon layer thickness; At the dielectric layer of described semiconductor substrate surface formation with described the second polysilicon layer flush; At described dielectric layer forming metal layer on surface, and described metal level covers described the first polysilicon layer and described the second polysilicon layer; Adopt annealing process to form the first metal silicide layer in described the first polysilicon layer, form the second metal silicide layer in described the second polysilicon layer, and the metal molar percentage of the first metal silicide layer is less than the metal molar percentage of the second metal silicide layer.
Optionally, described the first polysilicon layer is corresponding with the ratio of the metal molar percentage of the second metal silicide layer with Thickness Ratio and first metal silicide layer of the second polysilicon layer.
Optionally, the thickness of described the first polysilicon layer is 1.5 to 3 times of thickness of the second polysilicon layer.
Optionally, the thickness of the first polysilicon layer is 80nm to 120nm.
Optionally, the thickness of the second polysilicon layer is 30nm to 60nm.
Optionally, described metal layer material is nickel, cobalt, titanium or platinum.
Optionally, the thickness of described metal level is 40nm to 80nm.
Optionally, the thickness of described the first polysilicon layer is 0.55 to 0.8 with described metal layer thickness ratio.
Optionally, the thickness of described the second polysilicon layer is 1.1 to 2.0 with described metal layer thickness ratio.
Optionally, the material of the first metal silicide layer is NiSi.
Optionally, the material of the second metal silicide layer is Ni
2Si or Ni
3Si.
Optionally, described annealing process is rapid thermal anneal process.
Optionally, the parameter of described annealing process is: adopt rapid thermal anneler, annealing temperature is 200 ℃ to 350 ℃.
Optionally, also comprise: remove unreacted metal level, and to the first metal silicide layer and the annealing of the second metal silicide layer.
Optionally, to the technological parameter of the first metal silicide layer and the annealing of the second metal silicide layer be: annealing temperature is 300 ℃ to 600 ℃.
Compared with prior art; the present invention has the following advantages: the present embodiment adopts in the first area and forms different the first polysilicon layer and described the second polysilicon layers of thickness with second area; then form the metal level that covers described the first polysilicon and the second polysilicon; adopt a step annealing technique; form the different metal silicide layer of molar percentage in the first area with second area simultaneously; saved processing step; and the present embodiment does not need multistep deposition and etching; protected product not to be subjected to too much damage, the properties of product of formation are good.
Description of drawings
Fig. 1 is the schematic flow sheet of the CMOS formation method of the embodiment of the present invention;
Fig. 2 to Figure 10 is the process generalized section of the CMOS formation method of the embodiment of the present invention.
Embodiment
in prior art, adopt different silicide phases to control the effective work function of PMOS and nmos pass transistor, the metal gates that replaces NMOS and PMOS adopts different metals, but, the present inventor studies the technique that prior art forms different silicide phases, find: first (NMOS or PMOS) forms the first phase silicide to prior art in a certain zone usually, then (PMOS or NMOS) forms the second phase silicide in another zone, due to the deposition-etch technique that need to carry out in the different silicide phase of formation repeatedly, remove such as need to carry out to the first unnecessary phase silicide etching when forming the first phase silicide, need to carry out to the second unnecessary phase silicide etching at formation the second phase silicide removes, remove in technique more easily to the product formation etching injury in above-mentioned multiple etching.
For this reason, the present inventor proposes a kind of CMOS formation method, please refer to Fig. 1, comprises the steps:
Step S101 provides Semiconductor substrate, and described Semiconductor substrate comprises first area and the second area relative with the first area;
Step S102 is at the described semiconductor substrate surface formation gate dielectric layer of described first area and second area; Gate dielectric layer surface formation the first polysilicon layer in described first area, gate dielectric layer surface formation the second polysilicon layer in described first area, and described the first polysilicon layer thickness is thicker than described the second polysilicon layer thickness;
Step S103 is at the dielectric layer of described semiconductor substrate surface formation with described the second polysilicon layer flush;
Step S104, at described dielectric layer forming metal layer on surface, and described metal level covers described the first polysilicon layer and described the second polysilicon layer;
Step S105, adopt annealing process to form the first metal silicide layer in described the first polysilicon layer, form the second metal silicide layer in described the second polysilicon layer, and the metal molar percentage of the first metal silicide layer is less than the metal molar percentage of the second metal silicide layer.
Step S106 removes unreacted metal level, and to the first metal silicide layer and the annealing of the second metal silicide layer.
Particularly, described first area is NMOS or PMOS zone, and described second area is PMOS or nmos area territory, described first area and second area adjacent or interval.
Described the first polysilicon layer is corresponding with the ratio of the metal molar percentage of the second metal silicide layer with Thickness Ratio and first metal silicide layer of the second polysilicon layer, and wherein the metal molar percentage of metal silicide layer is the molar percentage of metal and silicon in metal silicide.
Described metal layer material is nickel, cobalt, titanium or platinum.
Preferably, described the first metal silicide layer material is NiSi, and described the second metal silicide layer material is Ni
2Si or Ni
3Si.
The present embodiment adopts in the first area and forms different the first polysilicon layer and described the second polysilicon layers of thickness with second area; then form the metal level that covers described the first polysilicon and the second polysilicon; adopt a step annealing technique; form the different metal silicide layer of molar percentage in the first area with second area simultaneously; saved processing step; and the present embodiment does not need multistep deposition and etching, has protected product not to be subjected to too much damage, and the properties of product of formation are good.
The below take the first area as the nmos area territory, and second area is that the PMOS zone is described in detail embodiments of the invention.
Please refer to Fig. 2, Semiconductor substrate 100 is provided, described Semiconductor substrate 100 comprises first area I and the second area II relative with first area I.
Described Semiconductor substrate 100 is used to subsequent technique that platform is provided, and described Semiconductor substrate 100 can be selected from the substrates such as silicon (SOI) on N-type silicon substrate, P type silicon substrate, insulating barrier.Described Semiconductor substrate 100 is 300mm silicon chip or 450mm silicon chip;
Described Semiconductor substrate 100 comprises first area I and the second area II relative with first area I, and in the present embodiment, described first area I is the nmos area territory, and second area is the PMOS zone; Adopt the isolation structure isolation between described first area I and second area II, described isolation structure is LOCOS or is fleet plough groove isolation structure (STI), and in the present embodiment, described isolation structure is fleet plough groove isolation structure.
Correspondingly, the first area I of described Semiconductor substrate 100 has P type dopant well (not shown), and the second area II of described Semiconductor substrate 100 has N-type dopant well (not shown).
Please in the lump with reference to figure 3, Fig. 4 and Fig. 5, at the described Semiconductor substrate 100 surface formation gate dielectric layers 110 of described first area I and second area II; At gate dielectric layer 110 surface formation the first polysilicon layers 121 of described first area I, at gate dielectric layer 110 surface formation the second polysilicon layers 122 of described second area II, and described the first polysilicon layer 121 thickness are thicker than described the second polysilicon layer 122 thickness.
Please refer to Fig. 3, at described Semiconductor substrate 100 surface formation silicon oxide layers 111, the formation technique of described silicon oxide layer is depositing operation or thermal oxidation technology.
Please refer to Fig. 4, at described silicon oxide layer 111 surface formation polysilicon layers 120, polysilicon layer 120 surface formation photoresist layers (not shown) in the I of first area, take described photoresist layer as mask, the described polysilicon layer 120 of etching is until remove the polysilicon layer on the second area II surface of segment thickness, makes polysilicon layer thickness in the I of first area be thicker than polysilicon layer thickness in second area II.
Need to prove, the Thickness Ratio of described the first polysilicon layer and the second polysilicon layer and the first metal silicide layer of follow-up formation are corresponding with the ratio of the metal molar percentage of the second metal silicide layer, thereby make the first metal silicide layer of formation and the metal molar percentage of the second metal silicide layer meet product demand.
More preferably, described polysilicon layer 120 thickness in the I of first area are 1.5 to 3 times of polysilicon layer 120 thickness in second area II, and above-mentioned thickness can make subsequent technique form the metal silicide layer of coupling NMOS and PMOS at first area I and second area II.
After removing photoresist layer, at described polysilicon 120 surface formation hard mask layers 130, described hard mask layer 130 materials are silicon nitride.
Please refer to Fig. 5, at described hard mask layer 130 surface formation photoetching offset plate figures (not shown), described photoetching offset plate figure is corresponding with the gate patterns of NMOS and PMOS, take described photoetching offset plate figure as mask, the described hard mask layer 130 of etching, polysilicon layer 120 and silicon oxide layer 111, until expose Semiconductor substrate 100, at the described Semiconductor substrate 100 surface formation gate dielectric layers 110 of described first area I and second area II; At gate dielectric layer 110 surface formation the first polysilicon layers 121 of described first area I, at gate dielectric layer 110 surface formation the second polysilicon layers 122 of described second area II, and described the first polysilicon layer 121 thickness are thicker than described the second polysilicon layer 122 thickness.
Concrete, the thickness of described the first polysilicon layer 121 is 80nm to 120nm, the thickness of described the second polysilicon layer is 30nm to 60nm.
Please still with reference to figure 5, after forming gate dielectric layer 110, the first polysilicon layer 121 and the second polysilicon layer 122, can also be on Semiconductor substrate 100 surfaces of the first polysilicon layer 121 both sides, Semiconductor substrate 100 surfaces of the second polysilicon layer 122 both sides form side walls.
Can also form source area and drain region in the Semiconductor substrate of the first polysilicon layer 121 both sides, and form source area and drain region in described the second polysilicon layer 122 semiconductor substrates on two sides, and form metal silicide layer in source area and drain region.
Please refer to Fig. 6 and Fig. 7, at the dielectric layer 140 of described Semiconductor substrate 100 surface formation with described the second polysilicon layer 122 flush.
Please refer to Fig. 6, remove described hard mask layer 130, the technique of described removal hard mask layer 130 is wet method or dry removal processes, here repeats no more.
Adopt depositing operation at described Semiconductor substrate 100 surface deposition dielectric films 141, described dielectric film 141 covers described the first polysilicon layer 121 and the second polysilicon layer 122.
Described depositing operation is chemical vapor deposition method, and the material of described dielectric film 141 is silica or low k dielectric materials.
Please refer to Fig. 7; adopt the described dielectric film 141 of CMP (Chemical Mechanical Polishing) process planarization; until expose described the first polysilicon layer 121; then photoresist is protected described the first polysilicon layer 121; adopt back the described dielectric film 141 of etching technics etching; until expose described the second polysilicon layer 122, form dielectric layer 140.
Please refer to Fig. 8, at described dielectric layer 140 forming metal layer on surfaces 150, and described metal level 150 covers described the first polysilicon layer 121 and described the second polysilicon layer 122.
Described metal level 150 is used for forming metal silicide with described the first polysilicon layer 121 and described the second polysilicon layer 122 reactions.
Described metal level 150 materials are nickel, cobalt, titanium or platinum, and described metal layer thickness is 40nm to 80nm.
The formation technique of described metal level 150 is physical vapour deposition (PVD) or chemical vapour deposition (CVD).
Also need to prove: because the formation technique of described metal level 150 is physical vapour deposition (PVD) or chemical vapour deposition (CVD), be formed on metal level 150 consistency of thickness of described the first polysilicon layer 121 and described the second polysilicon layer 122, thereby described first polysilicon layer 121 different from thickness and described the second polysilicon layer 122 form the metal silicide layer of different mol ratio in subsequent step.
Please refer to Fig. 9, adopt annealing process at described the first interior formation the first metal silicide layer 151 of polysilicon layer 121, at described the second interior formation the second metal silicide layer 152 of polysilicon layer 122, and the metal molar percentage of the first metal silicide layer 151 is less than the metal molar percentage of the second metal silicide layer 152.
Described annealing process is rapid thermal anneal process (Rapid Thermal Annealing, RTA), and particularly, described annealing process design parameter is: adopt rapid thermal anneler, annealing temperature is 200 ℃ to 350 ℃.
Need to prove, owing to having formed the metal level 150 that described the first polysilicon layer 121 thickness are thicker than described the second polysilicon layer 122 thickness and thickness homogeneous in step before, the polysilicon layer of different-thickness and the metal level of same thickness 150, thus the different metal silicide layer of metal molar percentage formed.
In one embodiment, the thickness of described the first polysilicon layer 121 and described metal level 150 Thickness Ratios are 0.55 to 0.8, the thickness of described the second polysilicon layer 122 and described metal level 150 Thickness Ratios are 1.1 to 2.0 o'clock, can form the more excellent different metal silicide layer of metal molar percentage.
In the present embodiment, because described the first polysilicon layer 121 thickness are thicker than described the second polysilicon layer 122 thickness, the metal molar percentage of the first metal silicide layer 151 of formation is less than the metal molar percentage of the second metal silicide layer 152.
In another embodiment, do exemplary illustrated take described metal layer material as nickel, described described the first polysilicon layer 121 thickness in the I of first area are 1.5 to 3 times of the second polysilicon layer 122 thickness in second area II, the thickness of described the first polysilicon layer 121 and described metal level 150 Thickness Ratios are 0.55 to 0.8, the thickness of described the second polysilicon layer 122 and described metal level 150 Thickness Ratios are 1.1 to 2.0 o'clock, after annealing process, can be the first metal silicide layer 151 of NiSi in nmos area territory forming component, be Ni in PMOS zone forming component
2Si or Ni
3The second metal silicide layer 152 of Si, and the work function of NiSi meets the requirement of NMOS, Ni
2Si or Ni
3The work function of Si meets the requirement of PMOS.
Need to prove, the present embodiment adopts primary depositing and annealing process to form the metal silicide layer that meets NMOS and PMOS demand, saves processing step.
Please refer to Figure 10, remove unreacted metal level 150, and to the first metal silicide layer 151 and the second metal silicide layer 152 annealing.
Described annealing process is high-temperature thermal annealing, is used for stablizing the first metal silicide layer 151 and the second metal silicide layer 152.
Described annealing process design parameter is: adopt rapid thermal anneler, annealing temperature is 300 ℃ to 600 ℃.
The present embodiment adopts in the first area and forms different the first polysilicon layer and described the second polysilicon layers of thickness with second area; then form the metal level that covers described the first polysilicon and the second polysilicon; adopt a step annealing technique; form the different metal silicide layer of molar percentage in the first area with second area simultaneously; saved processing step; and the present embodiment does not need multistep deposition and etching, has protected product not to be subjected to too much damage, and the properties of product of formation are good.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (15)
1. a CMOS formation method, is characterized in that, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate comprises first area and the second area relative with the first area;
Described semiconductor substrate surface at described first area and second area forms gate dielectric layer; Gate dielectric layer surface formation the first polysilicon layer in described first area, gate dielectric layer surface formation the second polysilicon layer in described first area, and described the first polysilicon layer thickness is thicker than described the second polysilicon layer thickness;
At the dielectric layer of described semiconductor substrate surface formation with described the second polysilicon layer flush;
At described dielectric layer forming metal layer on surface, and described metal level covers described the first polysilicon layer and described the second polysilicon layer;
Adopt annealing process to form the first metal silicide layer in described the first polysilicon layer, form the second metal silicide layer in described the second polysilicon layer, and the metal molar percentage of the first metal silicide layer is less than the metal molar percentage of the second metal silicide layer.
2. CMOS formation method as claimed in claim 1, is characterized in that, described the first polysilicon layer is corresponding with the ratio of the metal molar percentage of the second metal silicide layer with Thickness Ratio and first metal silicide layer of the second polysilicon layer.
3. CMOS formation method as claimed in claim 1, is characterized in that, the thickness of described the first polysilicon layer is 1.5 to 3 times of thickness of the second polysilicon layer.
4. CMOS formation method as claimed in claim 1, is characterized in that, the thickness of the first polysilicon layer is 80nm to 120nm.
5. CMOS formation method as claimed in claim 1, is characterized in that, the thickness of the second polysilicon layer is 30nm to 60nm.
6. CMOS formation method as claimed in claim 1, is characterized in that, described metal layer material is nickel, cobalt, titanium or platinum.
7. CMOS formation method as claimed in claim 6, is characterized in that, the thickness of described metal level is 40nm to 80nm.
8. CMOS formation method as claimed in claim 6, is characterized in that, the thickness of described the first polysilicon layer is 0.55 to 0.8 with described metal layer thickness ratio.
9. CMOS formation method as claimed in claim 6, is characterized in that, the thickness of described the second polysilicon layer is 1.1 to 2.0 with described metal layer thickness ratio.
10. CMOS formation method as claimed in claim 1, is characterized in that, the material of the first metal silicide layer is NiSi.
11. CMOS formation method as claimed in claim 1 is characterized in that, the material of the second metal silicide layer is Ni
2Si or Ni
3Si.
12. CMOS formation method as claimed in claim 1 is characterized in that, described annealing process is rapid thermal anneal process.
13. CMOS formation method as claimed in claim 12 is characterized in that, the parameter of described annealing process is: adopt rapid thermal anneler, annealing temperature is 200 ℃ to 350 ℃.
14. CMOS formation method as claimed in claim 1 is characterized in that, also comprises: remove unreacted metal level, and to the first metal silicide layer and the annealing of the second metal silicide layer.
15. CMOS formation method as claimed in claim 14 is characterized in that, to the technological parameter of the first metal silicide layer and the second metal silicide layer annealing be: annealing temperature is 300 ℃ to 600 ℃.
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| US20070034967A1 (en) * | 2005-08-01 | 2007-02-15 | International Business Machines Corporation | Metal gate mosfet by full semiconductor metal alloy conversion |
| CN1933158A (en) * | 2005-09-15 | 2007-03-21 | 松下电器产业株式会社 | Semiconductor device and method for fabricating the same |
| CN101317272A (en) * | 2005-11-28 | 2008-12-03 | 日本电气株式会社 | Semiconductor device and method for manufacturing same |
| CN101496154A (en) * | 2006-07-28 | 2009-07-29 | 国际商业机器公司 | Fully silicided gate electrodes and method of making the same |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070034967A1 (en) * | 2005-08-01 | 2007-02-15 | International Business Machines Corporation | Metal gate mosfet by full semiconductor metal alloy conversion |
| CN1933158A (en) * | 2005-09-15 | 2007-03-21 | 松下电器产业株式会社 | Semiconductor device and method for fabricating the same |
| CN101317272A (en) * | 2005-11-28 | 2008-12-03 | 日本电气株式会社 | Semiconductor device and method for manufacturing same |
| CN101496154A (en) * | 2006-07-28 | 2009-07-29 | 国际商业机器公司 | Fully silicided gate electrodes and method of making the same |
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