CN103077144A - Serial peripheral interface (SPI) communication interface for ensuring data integrity, and communication method thereof - Google Patents
Serial peripheral interface (SPI) communication interface for ensuring data integrity, and communication method thereof Download PDFInfo
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- CN103077144A CN103077144A CN2012105806975A CN201210580697A CN103077144A CN 103077144 A CN103077144 A CN 103077144A CN 2012105806975 A CN2012105806975 A CN 2012105806975A CN 201210580697 A CN201210580697 A CN 201210580697A CN 103077144 A CN103077144 A CN 103077144A
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Abstract
The invention belongs to the technical field of a distributed control system, and relates to a serial peripheral interface (SPI) communication interface for ensuring data integrity, and a communication method thereof. The SPI communication interface comprises a host computer for SPI communication, at least one slave, an SPI bus master output/slave output (MISO) line, an SPI bus master output/slave input (MOSI) line, an SCK line and a CS line. The SPI communication interface is characterized in that each slave comprises a Ready line to be connected with the host computer for ensuring the data integrality of SPI communication. By using the SPI communication interface, the data integrity of SPI communication is ensured by providing two communication methods. The Ready line is added between the host computer for SPI communication and the slave, so that the breaking effect on a current operation when the slave passively receives a communication instruction in the existing SPI communication is eliminated, and the data integrity of the SPI communication is ensured.
Description
Technical field
The invention belongs to the DCS(scattered control system) technical field, be specifically related to a kind ofly be applied between fastener inside and the fastener chip SPI communication interface and guarantee the method that the SPI communication data is complete.
Background technology
Scattered control system (DCS) is widely used in the industry-by-industries such as electric power, metallurgy, petrochemical complex.Along with the development of DCS, the situation of single module double mcu even multiple single chip microcomputer is more and more, or single module has a plurality of programmable chips.The SPI communications protocol is flexible, degree of controllability is high, and a lot of SPI communication of tenaculum DMA of cpu chip, makes the SPI communication become more simple and convenient, and the time that takies CPU still less, so the communication mode of SPI agreement is all adopted in the communication of a lot of chip chambers.
The both sides of SPI communication are divided into main frame and one or more from equipment, 4 lines of normal operation: the slave of serial time clock line (SCK), main frame input/slave output data line MISO, main frame output/slave input data line MOSI and Low level effective is selected line CS.
During general SPI communication, the status that main frame has the initiative and dominates, slave can only passive receive.But the chip as slave generally also needs to carry out other orders and task, and the communication command of accepting passively main frame inevitably will interrupt and affect the task of current execution, if especially both sides' Content of communciation is the data of constantly updating, slave is accepted passively the SPI communication command and may be interrupted current data acquisition or interrupt the data field assignment, the problems such as the unreliable and data dislocation of the data that cause slave to collect, even might cause very serious fault.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of SPI communication interface and utilizes it to guarantee the means of communication of the data integrity of the SPI communication between single-chip microcomputer or between other programmable chips, the current task of avoiding being in the SPI communication programmable chip of slave status is interrupted, also avoid the data of communication transfer that the problems such as dislocation occur, improved the operation efficiency of transfer efficiency and processor.
For achieving the above object, the technical scheme that adopts is: a kind of SPI communication interface of guaranteeing data integrity, main frame and at least one slave, MISO line, MOSI line, SCK line and CS line of comprising the SPI communication, it is characterized in that: every described slave has a Ready line to be connected with described main frame, is used for guaranteeing the data integrity of SPI communication.
Use above-mentioned SPI communication interface, the first is guaranteed the means of communication of data integrity, it is characterized in that, may further comprise the steps:
(1) the slave data acquisition is complete and data are put into SPI send the buff district, when being ready for the SPI communication, drags down the Ready line;
When (2) Host Detection is low to certain slave Ready line, drag down CS line corresponding to this slave;
(3) main frame and this slave carry out the SPI communication;
(4) communication is complete, and main frame is drawn high the CS line, and slave is drawn high the Ready line.
Use above-mentioned SPI communication interface, the second is guaranteed the means of communication of data integrity, it is characterized in that, may further comprise the steps:
(1) the slave data acquisition is complete and data are put into SPI send the buff district, when being ready for the SPI communication, drags down the Ready line;
When (2) Host Detection is low to certain slave Ready line, drag down CS line corresponding to this slave;
(3) this slave and main frame begin the SPI communication, transmit a byte;
(4) judge whether data transmission is complete, end of transmission then goes to step (7), the not complete step (5) that then goes to;
(5) slave is put into the SPI data register with next byte, and the level of the Ready line that overturns;
(6) main frame judges according to the byte number that transmits whether Ready line level is correct, correctly then goes to step (3), the incorrect step (7) that then goes to;
(7) main frame is drawn high the CS line, and slave is drawn high the Ready line, and communication finishes.
Good effect of the present invention is: by set up a Ready line between the main frame of SPI communication and every slave, make slave have initiative to communication, interrupted the impact of current operation when having eliminated slave passive receive communication instruction in the existing SPI communication.Simultaneously because the existence of CS line, the main frame of SPI communication is not lost the control to communication yet, main frame and slave can not interrupt other tasks of oneself because of the passive communication command of accepting, thereby the quality of SPI communication is significantly improved, guarantee the data integrity of SPI communication, also improved the work efficiency of the CPU of the main frame of SPI communication and slave.
Description of drawings
Fig. 1 is the hardware principle block diagram of existing SPI communication;
Fig. 2 is the hardware principle block diagram of SPI communication of the present invention;
Fig. 3 is the byte sequential chart of the SPI means of communication of the present invention;
Sequential chart when Fig. 4 is the first means of communication multibyte communication of the present invention;
Sequential chart when Fig. 5 is the second means of communication multibyte communication of the present invention;
The process flow diagram of slave when Fig. 6 is the first means of communication multibyte communication of the present invention;
The process flow diagram of main frame when Fig. 7 is the first means of communication multibyte communication of the present invention;
The process flow diagram of slave when Fig. 8 is the second means of communication multibyte communication of the present invention;
The process flow diagram of main frame when Fig. 9 is the second means of communication multibyte communication of the present invention.
Embodiment
A kind of SPI communication interface of guaranteeing data integrity, main frame and at least one slave, MISO line, MOSI line, SCK line and CS line of comprising the SPI communication, it is characterized in that: every described slave has a Ready line to be connected with described main frame, is used for guaranteeing the data integrity of SPI communication.
Use above-mentioned SPI communication interface, the first is guaranteed the means of communication of data integrity, it is characterized in that may further comprise the steps:
(1) the slave data acquisition is complete and data are put into SPI send the buff district, when being ready for the SPI communication, drags down the Ready line;
When (2) Host Detection is low to certain slave Ready line, drag down CS line corresponding to this slave;
(3) main frame and this slave carry out the SPI communication;
(4) communication is complete, and main frame is drawn high the CS line, and slave is drawn high the Ready line.
Use above-mentioned SPI communication interface, the second is guaranteed the means of communication of data integrity, it is characterized in that, may further comprise the steps:
(1) the slave data acquisition is complete and data are put into SPI send the buff district, when being ready for the SPI communication, drags down the Ready line;
When (2) Host Detection is low to certain slave Ready line, drag down CS line corresponding to this slave;
(3) this slave and main frame begin the SPI communication, transmit a byte;
(4) judge whether data transmission is complete, end of transmission then goes to step (7), the not complete step (5) that then goes to;
(5) slave is put into the SPI data register with next byte, and the level of the Ready line that overturns;
(6) main frame judges according to the byte number that transmits whether Ready line level is correct, correctly then goes to step (3), the incorrect step (7) that then goes to;
(7) main frame is drawn high the CS line, and slave is drawn high the Ready line, and communication finishes.
Fig. 1 is the hardware principle block diagram of existing SPI communication, Fig. 2 is the hardware principle block diagram of SPI communication of the present invention, comparison diagram 1 and Fig. 2 are as seen, SPI communication of the present invention has been Duoed a Ready line than existing SPI communication at hardware, the signal of this line is exported by slave, be input to main frame, that slave is to the control line of whole SPI communication, this line makes main frame in whole SPI communication initiative arranged, therefore, the SPI communication command that no longer sent by main frame such as the task of the current execution of slave such as data collection interrupts.
Fig. 3 is the byte sequential chart of the SPI means of communication of the present invention, by finding out in the sequential chart, only the CS line just can drag down after the Ready line drags down, and only in the situation that Ready and CS line all be low CLK just can be effective, thereby data just can be effective, the just existence of Ready line and CS line, just make main frame and the slave both sides of SPI communication that ownership has been arranged, main frame and slave can not interrupt other tasks of oneself because of the passive communication command of accepting, thereby can guarantee data and other data integrities and the true and accurate of SPI communication.
Sequential chart when the present invention has two kinds of communication mode: Fig. 4 to be the first means of communication multibyte communication of the present invention, the sequential chart when Fig. 5 is the second means of communication multibyte communication of the present invention.The something in common of two kinds of communication modes is, slave has the Ready control line, all communication is had control; Difference is that the first pattern Ready line only overturns once, and beginning drags down before the communication, and communication is complete draws high, and is applicable to the demanding situation of communication speed, and main frame, slave can be with rapid data transmission means such as DMA; And the second pattern is overturn once at each byte end of transmission Ready line, in this case, main frame needed to judge the level of Ready line before each the byte transmission except first byte, thereby more can guarantee the correctness of communication, but the defective of this pattern is, main frame all needs to judge the state of Ready line at every turn because each slave all will overturn the Ready line, thereby has reduced the communication speed of SPI, and can not use the high speed means of communication such as DMA.So can come choice for use the first pattern or the second pattern according to actual conditions in use.
The process flow diagram of slave when Fig. 6 is the first means of communication multibyte communication of the present invention, the process flow diagram of main frame when Fig. 7 is the first means of communication multibyte communication of the present invention.As shown in the figure, when the slave DSR, drag down the Ready line; When Host Detection is low to certain slave Ready line, drag down CS line corresponding to this slave; Main frame and this slave carry out the SPI communication; Communication is complete, and main frame is drawn high the CS line, and slave is drawn high the Ready line.
The process flow diagram of slave when Fig. 8 is the second means of communication multibyte communication of the present invention, the process flow diagram of main frame when Fig. 9 is the second means of communication multibyte communication of the present invention.As shown in the figure:
(1) the slave data acquisition is complete and data are put into SPI send the buff district, when being ready for the SPI communication, drags down the Ready line;
When (2) Host Detection is low to certain slave Ready line, drag down CS line corresponding to this slave;
(3) this slave and main frame begin the SPI communication, transmit a byte;
(4) judge whether data transmission is complete, end of transmission then goes to step (7), the not complete step (5) that then goes to;
(5) slave is put into the SPI data register with next byte, and the level of the Ready line that overturns;
(6) main frame judges according to the byte number that transmits whether Ready line level is correct, correctly then goes to step (3), the incorrect step (7) that then goes to;
(7) main frame is drawn high the CS line, and slave is drawn high the Ready line, and communication finishes.
Process flow diagram by above-mentioned two kinds of communication modes can be found out, before each communication begins, all to operate the Ready line, this is that slave can select when to begin communication, and main frame is because the existence of CS line, do not lose the control to communication yet, like this slave can data acquisition or other tasks finish control afterwards Ready line notice main frame can communication, finish and control afterwards the CS line and begin communication and main frame also can be chosen in other tasks, the control that all has of main frame and slave makes the communication controllability that becomes very strong like this, other operations of main frame and slave can not interrupted, guaranteed the data integrity that is designed into of other operations.
Experimental verification:
Test for performance of the present invention, compare with existing SPI communication modes, both hardware circuits are identical, all adopting main frame is that LPC2136, two slaves are STM32F103, main frame carries out multiple communication simultaneously, and slave carries out the meter of pulsed quantity simultaneously to be measured frequently, and measurement range is 1-10000Hz.
Experimental results show that, when adopting traditional SPI means of communication, slave is because the passive communication command of accepting, when pulsed frequency is higher or pulsed frequency lower the time, the frequently operation meeting of the meter of slave is interrupted by the SPI communication, thereby causes result of calculation to follow the signal source of input inconsistent.When adopting the SPI means of communication of the present invention, slave is chosen in to calculate and drags down the Ready line after complete and begin communication, and through observing for a long time, the result of calculation of slave is consistent with the signal of input, and in measurement range, error is ± 1Hz.
By experimental result as can be known, the present invention can guarantee the correctness of other operations of SPI communication two party, can guarantee that the SPI communication two party carries out the complete of the data that relate to when other calculate.
Claims (3)
1. SPI communication interface of guaranteeing data integrity, main frame and at least one slave, MISO line, MOSI line, SCK line and CS line of comprising the SPI communication, it is characterized in that: every described slave has a Ready line to be connected with described main frame, is used for guaranteeing the data integrity of SPI communication.
2. use a kind of SPI communication interface as claimed in claim 1 to guarantee the means of communication of data integrity, it is characterized in that, may further comprise the steps:
(1) the slave data acquisition is complete and data are put into SPI send the buff district, when being ready for the SPI communication, drags down the Ready line;
When (2) Host Detection is low to certain slave Ready line, drag down CS line corresponding to this slave;
(3) main frame and this slave carry out the SPI communication;
(4) communication is complete, and main frame is drawn high the CS line, and slave is drawn high the Ready line.
3. use a kind of SPI communication interface as claimed in claim 1 to guarantee the means of communication of data integrity, it is characterized in that, may further comprise the steps:
(1) the slave data acquisition is complete and data are put into SPI send the buff district, when being ready for the SPI communication, drags down the Ready line;
When (2) Host Detection is low to certain slave Ready line, drag down CS line corresponding to this slave;
(3) this slave and main frame begin the SPI communication, transmit a byte;
(4) judge whether data transmission is complete, end of transmission then goes to step (7), the not complete step (5) that then goes to;
(5) slave is put into the SPI data register with next byte, and the level of the Ready line that overturns;
(6) main frame judges according to the byte number that transmits whether Ready line level is correct, correctly then goes to step (3), the incorrect step (7) that then goes to;
(7) main frame is drawn high the CS line, and slave is drawn high the Ready line, and communication finishes.
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Cited By (6)
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| CN103838700A (en) * | 2014-02-20 | 2014-06-04 | 江苏理工学院 | level multiplexing control serial communication device and communication method thereof |
| CN104735053A (en) * | 2015-01-28 | 2015-06-24 | 上海兰宝传感科技股份有限公司 | Multi-CPU control system based on SPI bus and MODBUS communication protocol |
| CN105024900A (en) * | 2015-08-03 | 2015-11-04 | 艾德克斯电子（南京）有限公司 | Multi-machine synchronous communication system and method |
| CN107346294A (en) * | 2016-05-04 | 2017-11-14 | 上海商米科技有限公司 | Data-flow-control system and method based on SPI protocol |
| CN112214440A (en) * | 2020-10-10 | 2021-01-12 | 北京寓乐世界教育科技有限公司 | Communication method based on SPI communication |
| CN114528235A (en) * | 2022-01-21 | 2022-05-24 | 厦门亿联网络技术股份有限公司 | SPI (Serial peripheral interface) -based communication method, slave equipment and system |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103838700A (en) * | 2014-02-20 | 2014-06-04 | 江苏理工学院 | level multiplexing control serial communication device and communication method thereof |
| CN104735053A (en) * | 2015-01-28 | 2015-06-24 | 上海兰宝传感科技股份有限公司 | Multi-CPU control system based on SPI bus and MODBUS communication protocol |
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| CN107346294A (en) * | 2016-05-04 | 2017-11-14 | 上海商米科技有限公司 | Data-flow-control system and method based on SPI protocol |
| CN112214440A (en) * | 2020-10-10 | 2021-01-12 | 北京寓乐世界教育科技有限公司 | Communication method based on SPI communication |
| CN114528235A (en) * | 2022-01-21 | 2022-05-24 | 厦门亿联网络技术股份有限公司 | SPI (Serial peripheral interface) -based communication method, slave equipment and system |
| CN114528235B (en) * | 2022-01-21 | 2024-05-31 | 厦门亿联网络技术股份有限公司 | SPI-based communication method, slave device and system |
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Owner name: SHANGHAI AUTOMATION INSTRUMENTATION CO., LTD. Free format text: FORMER OWNER: SHANGHAI AUTOMATIC INDUSTRUMENT AND METER CO LTD Effective date: 20150612 |
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