CN103067148A - Hardware synchronization method of cascading instrument - Google Patents
Hardware synchronization method of cascading instrument Download PDFInfo
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- CN103067148A CN103067148A CN2012102649313A CN201210264931A CN103067148A CN 103067148 A CN103067148 A CN 103067148A CN 2012102649313 A CN2012102649313 A CN 2012102649313A CN 201210264931 A CN201210264931 A CN 201210264931A CN 103067148 A CN103067148 A CN 103067148A
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Abstract
The invention discloses a hardware synchronization method of a cascading instrument. The hardware synchronization method of the cascading instrument includes that main control modules of a plurality of instruments conduct information interaction through Ethernet, distribute addresses according to position order of a series link which is formed by connecting synchronous modules, and confirm an instrument which is located in a first position in the link. When synchronization needs to be conducted, the main control module of the first position instrument sends synchronous configuration requirements to the main control modules of other position instruments through the Ethernet and sends synchronous instructions to the synchronous modules of the instrument. The other instrument main control modules receive the synchronous configuration requirements through the Ethernet, finish synchronous configuration of the instrument, and meanwhile the synchronous modules of the instrument receive synchronous input signals and clock input signals through an input signal wire. After the synchronous input signals and the clock input signals are processed by the synchronous modules in the instrument, one path sends out the synchronous input signals and the clock input signals through the output signal wire and the other path is led to other function circuits of the instrument to conduct synchronization operation, so synchronization of all instruments in a system can be finally achieved.
Description
Technical field:
The present invention relates to control, technical field of measurement and test, but relate in particular to a kind of control of cascade in large-scale control, the test macro, method for synchronous between the tester of being applied to.
Background technology:
In control, technical field of measurement and test are used, the especially extraction of some complex state information, analog computation, it not only needs the signals collecting number of links huge, also need the multiplexed signal sampling link carry out strict synchronously.Traditional separate unit instrument obviously is that impossible to satisfy it fully be the application requirements that day by day increases, and for this reason, takes many instrument cascades or distributed connection to become inevitable trend, and the synchronous processing of signals collecting link also becomes inevitable factor between multiple instruments.
At present, between multiple instruments synchronously, no matter be cascade or distributed, mainly contain two kinds of technical schemes: the one, adopt main control module that synchronization point is set, each instrument by count alone with arrange under synchronization point compare, thereby realize that many instruments are synchronous; The one, main control module the set time section send to the time signal, instrument by with to the time signal calibration time difference, thereby realize that many instruments are synchronous.
Two kinds of above-mentioned technical schemes can realize in larger time tolerance synchronously, but need in the situation of precise time in actual applications, accomplish it is very difficult synchronously.This is because the precision of external crystal-controlled oscillation that is used for producing precise time of each instrument is different.The crystal oscillator precision that general instrument uses be ± 50ppm about, when two instruments used respectively the crystal oscillator of 5/1000000ths precision to produce precise time, if do not revise, it was in 1 second time, the maximum deviation of generation is 50uS each other.In other words, if the signal of two instrument collections is 20KHz, then in 1 second, the phase shift of one-period can appear.Therefore, guarantee synchronously accurate consistency, just need within the extremely short time, revise that in actual applications, this correction frequently certainly will be caused the resource overhead of multiple instruments system, thereby lowers efficiency.In addition, crystal oscillator itself is a temperature sensor, and temperature effect can be aggravated above-mentioned phenomenon, so above-mentioned phenomenon is prior art scheme defective technically.
In sum, there is following defective in existing technical scheme:
One, if the employing of the instrument in system crystal oscillator separately then needs frequently simultaneous operation producing the precise time realization synchronously, affect efficient;
Two, synchronous frequently as not carrying out, then certainly will reduce synchronous time precision, affect consistency.
Summary of the invention:
In view of above-mentioned technical problem, but the invention provides the method for the hardware synchronization between a kind of cascade instrument.The method mainly is that to solve in the prior art in the system each instrument simultaneous operation precision not high, is subjected to each instrument crystal oscillator individual difference to affect large problem, can realize that the simultaneous operation precision is high, and not affected by instrument crystal oscillator individual difference.Secondly, can also solve in the prior art after system synchronization for eliminate accumulated error that crystal oscillator difference causes needs frequent to the time problem so that only need a simultaneous operation, can realize long-term stable maintenance synchronous regime.Moreover, can also solve prior art loaded down with trivial details to the time, the Synchronization Control flow process, accomplish simple for structure, simple, the high efficiency of control flow.
Concrete technical scheme of the present invention is as follows:
But the method for the hardware synchronization between a kind of cascade instrument, the concrete steps of the method are as follows:
A. the main control module of many instruments carries out information interaction by Ethernet, distributes the address according to the sequence of positions of the link in tandem that connects into via synchronization module, confirms to be in the link instrument of primary importance;
B. in case need to carry out synchronously, the main control module of primary importance instrument sends synchronous configuration requirement by Ethernet to the main control module of other position instruments, and the synchronization module in this instrument sends synch command; After synchronization module in described this instrument makes an explanation to this synch command, outwards send synchronization output signal, clock output signal by output signal line;
C. other instrument main control modules receive synchronous configuration requirement by Ethernet, finish the synchronous configuration of instrument, and the synchronization module in this instrument receives synchronous input signal, clock input signal by input signal cable simultaneously; After synchronization module in this instrument of described process was processed, it was leaded up to output signal line and outwards sends synchronization output signal, clock output signal; Another road is incorporated into other functional circuits of instrument and carries out simultaneous operation, thus finally realize all appts in the system synchronously.
In the such scheme, the synchronization module in the described instrument is a FPGA (Field Programmable Gate Array) treatment circuit, and this FPGA (Field Programmable Gate Array) treatment circuit receives via synchronous configuration or the synch command of interface circuit to main control module, and makes corresponding explanation; The synchronous input signal, the clock input signal that comprehensively receive via synchronous input interface simultaneously, process by DCM, then send synchronization output signal, clock output signal by synchronous delivery outlet, by interface circuit synchronizing information is incorporated into other functional circuits of instrument simultaneously.
In the such scheme, described method is carried out waveform correction, phase-locked processing, strict guarantee synchronous input signal and synchronization output signal, clock input signal and clock output signal same-phase by the DCM of FPGA (Field Programmable Gate Array) treatment circuit in the synchronization module.Be that synchronous input/output signal is identical with the poor Δ t of the relative time of clock input/output signal all the time.
In the such scheme, in the described method after synchronous event sends from the synchronous signal line of First instrument, other instrument is after receiving synchronous event, then come the triggering synchronous operation with the same clock edge behind the synchronous event, because the FPGA (Field Programmable Gate Array) treatment circuit is hardware trigger, its time-delay can be ignored fully, thereby can realize the precise synchronization of all appts in the system.
In the such scheme, described method is in synchronizing process, synchronously the trigger point is chosen is with respect to the relative point in time of synchronizing signal on the same clock signal, so that the precise time that triggers synchronously can be got rid of the factor of clock signal, because synchronizing signal is level signal, it is very little and fixing the survey at intrasystem transmission delay, so realize exact time synchronization on the basis of system's precise synchronization.
Compared with prior art, the present invention has following advantage:
1. the synchronous clock of each instrument is to be sent by the primary importance instrument, rather than instrument is quoted the internal clocking of controlling oneself, so do not have individual difference impact and the accumulated error of each instrument crystal oscillator, and then the responsive to temperature problem of clock devices also can obtain good control and solution.Thereby stable, a long-term system synchronization state keeps after the assurance simultaneous operation.
2. process strict guarantee instrument synchronous input signal and synchronization output signal, clock input signal and clock output signal same-phase by DCM such as waveform correction, phase-locked processing; Adopt simultaneously same clock behind the synchronous event along coming hardware trigger simultaneous operation, can fully guarantee the high-precise synchronization between each instrument relatively.
3. it is very little and fixingly survey, trigger fast characteristic to take full advantage of the hardware transmission delay, realizes exact time synchronization on the basis of system's precise synchronization.
4. take full advantage of the distributed structure that combines with cascade, carry out the control of synchronous flow process by distributed frame, cascade structure carries out the transmission of hardware synchronization information, has greatly simplified control flow and structure, thereby realizes high efficiency simultaneous operation.
Description of drawings:
Further specify the present invention below in conjunction with the drawings and specific embodiments.
Fig. 1 is the system architecture diagram of the method for the invention when concrete the application.
Fig. 2 is the structured flowchart of the synchronization module of the instrument in the system shown in Figure 1.
Fig. 3 is the schematic diagram of input signal cable involved in the present invention.
Fig. 4 is the schematic diagram of output signal line involved in the present invention.
Fig. 5 is the synchronous schematic diagram of clock signal and synchronizing signal in the inventive method.
Embodiment:
For technological means, creation characteristic that the present invention is realized, reach purpose and effect is easy to understand, below in conjunction with concrete diagram, further set forth the present invention.
As shown in Figure 1, this figure is the composition of the hardware system structure of method of the present invention in specific implementation process.It comprises many instruments 100 that have main control module 101, synchronization module 102, and the input signal cable and the output signal line that are used for connecting synchronization module 102 in the instrument 100; Main control module 101 and the synchronization module 102 of instrument 100 carry out connecting communication by the PXI bus of instrument internal; The main control module 101 of instrument 100 is by the distributed connecting communication between Ethernet realization instrument; Synchronization module 102 in the instrument 100 also connects other functional circuits 103
In the whole system, the input signal cable of an instrument synchronization module links to each other with the output signal line of last instrument synchronization module, the output signal line of synchronization module links to each other with the input signal cable of a rear instrument synchronization module, thereby makes many instruments connect into a link in tandem via synchronization module.
As shown in Figure 2, this figure is the structured flowchart of synchronization module in the instrument.Wherein, the FPGA (Field Programmable Gate Array) treatment circuit receives via synchronous configuration or the synch command of interface circuit to main control module, and makes corresponding explanation; The synchronous input signal, the clock input signal that comprehensively receive via synchronous input interface simultaneously, process by DCM, then send synchronization output signal, clock output signal by synchronous delivery outlet, by interface circuit synchronizing information is incorporated into other functional circuits of instrument simultaneously.
In addition, synchronous input interface, synchronous output interface all adopt the EXG1B connector of 7 core Lemo; FPGA (Field Programmable Gate Array) treatment circuit and jointly adopt the SPART 3 Series FPGA chips of a slice XILINX company to realize with other functional circuit interface circuits; Adopt high density (2mm spacing) the impedance matching cellular type connector that meets PXI bus protocol regulation and PCI9054 type pci data communication bus and the local data bus conversion chip of PLX company to realize with the interface circuit of main control module.
In addition, as shown in Figure 3, the synchronous input signal line adopts the cable that comprises two pairs of twisted-pair feeders of band shielding.A pair of twisted-pair feeder in the cable is with differential pair mode transfer clock input signal; Another to twisted-pair feeder with differential pair mode transmitting synchronous input signal.As shown in Figure 4, the synchronization output signal line adopts the cable that comprises two pairs of twisted-pair feeders of band shielding.A pair of twisted-pair feeder in the cable is with differential pair mode transfer clock output signal; Another to twisted-pair feeder with differential pair mode transmitting synchronous output signal.
The key step of the inventive method is: the main control module of many instruments at first carries out information interaction by Ethernet, distributes the address according to the sequence of positions of the link in tandem that connects into via synchronization module, confirms to be in the link instrument of primary importance.In case need to carry out synchronously, the main control module of primary importance instrument sends synchronous configuration requirement by Ethernet to the main control module of other position instruments, and the synchronization module in the instrument sends synch command simultaneously.After synchronization module in the instrument makes an explanation to this order, outwards send synchronization output signal, clock output signal by output signal line.Other instrument main control modules receive synchronous configuration requirement by Ethernet, finish the synchronous configuration of instrument, and receive synchronous input signal, clock input signal by synchronization module by input signal cable, after processing through synchronization module, it is leaded up to output signal line and outwards sends synchronization output signal, clock output signal; One the tunnel is incorporated into other functional circuits of instrument carries out simultaneous operation, thus finally realize all appts in the system synchronously.
As shown in Figure 5, the clock signal in the scheme comprises clock input signal, clock output signal; Synchronizing signal comprises synchronous input signal, synchronization output signal.DCM by FPGA (Field Programmable Gate Array) treatment circuit in the synchronization module carries out waveform correction, phase-locked processing, strict guarantee synchronous input signal and synchronization output signal, clock input signal and clock output signal same-phase, namely input/output signal is identical with the poor Δ t of the relative time of clock input/output signal all the time synchronously.After synchronous event sends from the synchronous signal line of First instrument, other instrument is after receiving synchronous event, then come the triggering synchronous operation with the same clock edge behind the synchronous event, because the FPGA (Field Programmable Gate Array) treatment circuit is hardware trigger, its time-delay can be ignored fully, thereby can realize the precise synchronization of all appts in the system.In addition because synchronously the trigger point is not the absolute time point of choosing on the clock signal, but on the same clock signal of choosing with respect to the relative point in time of synchronizing signal, so the precise time that triggers synchronously can be got rid of the factor of clock signal; And synchronizing signal is owing to be level signal, and it is very little and fixing the survey at intrasystem transmission delay, so realize exact time synchronization on the basis of system's precise synchronization.
More than show and described basic principle of the present invention and principal character and advantage of the present invention.The technical staff of the industry should understand; the present invention is not restricted to the described embodiments; that describes in above-described embodiment and the specification just illustrates principle of the present invention; without departing from the spirit and scope of the present invention; the present invention also has various changes and modifications, and these changes and improvements all fall in the claimed scope of the invention.The claimed scope of the present invention is defined by appending claims and equivalent thereof.
Claims (5)
1. but the method for the hardware synchronization between a cascade instrument is characterized in that the concrete steps of the method are as follows:
A. the main control module of many instruments carries out information interaction by Ethernet, distributes the address according to the sequence of positions of the link in tandem that connects into via synchronization module, confirms to be in the link instrument of primary importance;
B. in case need to carry out synchronously, the main control module of primary importance instrument sends synchronous configuration requirement by Ethernet to the main control module of other position instruments, and the synchronization module in this instrument sends synch command; After synchronization module in described this instrument makes an explanation to this synch command, outwards send synchronization output signal, clock output signal by output signal line;
C. other instrument main control modules receive synchronous configuration requirement by Ethernet, finish the synchronous configuration of instrument, and the synchronization module in this instrument receives synchronous input signal, clock input signal by input signal cable simultaneously; After synchronization module in this instrument of described process was processed, it was leaded up to output signal line and outwards sends synchronization output signal, clock output signal; Another road is incorporated into other functional circuits of instrument and carries out simultaneous operation, thus finally realize all appts in the system synchronously.
2. but the method for the hardware synchronization between according to claim 1 cascade instrument, it is characterized in that, synchronization module in the described instrument is a FPGA (Field Programmable Gate Array) treatment circuit, this FPGA (Field Programmable Gate Array) treatment circuit receives via synchronous configuration or the synch command of interface circuit to main control module, and makes corresponding explanation; The synchronous input signal, the clock input signal that comprehensively receive via synchronous input interface simultaneously, process by DCM, then send synchronization output signal, clock output signal by synchronous delivery outlet, by interface circuit synchronizing information is incorporated into other functional circuits of instrument simultaneously.
3. but the method for the hardware synchronization between according to claim 1 cascade instrument, it is characterized in that, described method is carried out waveform correction, phase-locked processing, strict guarantee synchronous input signal and synchronization output signal, clock input signal and clock output signal same-phase by the DCM of FPGA (Field Programmable Gate Array) treatment circuit in the synchronization module.
4. but the method for the hardware synchronization between according to claim 1 cascade instrument, it is characterized in that, in the described method after synchronous event sends from the synchronous signal line of First instrument, other instrument is after receiving synchronous event, then come the triggering synchronous operation with the same clock edge behind the synchronous event, because the FPGA (Field Programmable Gate Array) treatment circuit is hardware trigger, its time-delay can be ignored fully, thereby can realize the precise synchronization of all appts in the system.
5. but the method for the hardware synchronization between according to claim 1 cascade instrument, it is characterized in that, described method is in synchronizing process, synchronously the trigger point is chosen is with respect to the relative point in time of synchronizing signal on the same clock signal, so that the precise time that triggers synchronously can be got rid of the factor of clock signal, because synchronizing signal is level signal, it is very little and fixing the survey at intrasystem transmission delay, so realize exact time synchronization on the basis of system's precise synchronization.
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| CN106850176A (en) * | 2016-11-23 | 2017-06-13 | 西安昆仑工业（集团）有限责任公司 | Cannon distributed data Master-slave parallel harvester and method |
| CN110808804A (en) * | 2019-10-30 | 2020-02-18 | 中电科仪器仪表有限公司 | Structure and method for realizing receiving synchronization of multipath RapidIO test board cards and test equipment |
| CN112306146A (en) * | 2020-10-30 | 2021-02-02 | 济南浪潮高新科技投资发展有限公司 | Device and method for synchronizing output waveforms of AWG board card in multi-PXIE chassis |
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| CN112306146A (en) * | 2020-10-30 | 2021-02-02 | 济南浪潮高新科技投资发展有限公司 | Device and method for synchronizing output waveforms of AWG board card in multi-PXIE chassis |
| CN112306146B (en) * | 2020-10-30 | 2023-07-21 | 山东浪潮科学研究院有限公司 | Device and method for synchronizing output waveforms of AWG board cards in multi-PXIE chassis |
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