CN103036577A - Low-complexity code circuit structure of low density parity check (LDPC) code - Google Patents

Abstract

The invention discloses a low-complexity code circuit structure of a low density parity check (LDPC) code. The code circuit structure of the LDPC code comprise a multiplication circuit, an add operation circuit and a control circuit. The code circuit structure and the check matrix of the LDPC code carry out row operation through an original input uncoded information sequence, and finally the row operation is achieved by gaining a check sequence. The code circuit structure aims at a quasi-cyclic LDPC code with a code rate greater than 0.5 and a similar lower triangular form, adopts a mode that operation is carried out according to the rows of the check matrix of the LDPC, reduces hardware resources, adopts an operate mode of being partially parallel, guarantees the data handling capacity of a code circuit, and achieves the low-complexity encoding of the quasi-cyclic LDPC code with the similar lower triangular form.

Description

A kind of low-density checksum LDPC code coding circuit structure of low complex degree

Technical field

The invention belongs to digital signal and system field, relate to the realization of the LDPC code error correcting code circuitry in the transfer of data error correcting technique.Be specifically related to the realization for the coding circuit of the LDPC code of the quasi-cyclic with near lower triangular form, be a kind of coding circuit structure of LDPC code of low complex degree.

Background technology

The purpose of communication is that the ignorant message of the other side in time is sent to the other side reliably, improves reliability and the validity of communication, is the target that communication work is pursued all the time.Chnnel coding is for the transmission reliability that guarantees communication system, overcomes Noise and Interference in the channel and the jamproof technology of a custom-designed class and method.It is according to certain rule artificial some necessary verification code elements of adding in information code element to be sent, at receiving terminal, utilizes law discoveries of these check code elements and information code element and corrects mistake, the reliability of transmitting to improve information code element.Code element information to be sent is information code element, and the unnecessary code element of artificial adding is the verification code element.The purpose of chnnel coding is to attempt to exchange for minimum verification code element the raising of maximum reliability.

In communication system, error correction coding is used to improve reliability and the power utilization of transmission, and LDPC (Low-density Parity-check, low-density checksum) code is a kind of error correction coding of better performances.The LDPC code is proposed by Gallager at first, but do not cause enough attention, until after the Turbo code proposition, people are when the iterative decoding of research Turbo code, find that the two has identical characteristic, namely retrain the characteristic of random code set and iterative decoding, started subsequently the research climax of LDPC code.

But the LDPC code approaches the performance of shannon limit and the characteristics that complete parallel is realized iterative decoding with it, performance is better than other channel coding/decodings under many occasions, become just gradually the focus of channel error correction encoding research in the wireless sense network, the many choice for use LDPC of system codes have been arranged at present, such as satellite digital video broadcast standard DVB-S2 and next generation mobile communication system.

Be different from other linear block codess, the LDPC code is represented by its H matrix.The characteristic of H matrix directly has influence on the encoder complexity of LDPC code.The subject matter that the LDPC code faces is its higher encoder complexity and encoding time delay.If adopt common coded system, the LDPC code coder has the encoder complexity that becomes quadratic power with code length, and this is difficult to accept when code length is longer.Therefore, in the time of practical application, main consideration has the LDPC code of the check matrix of ad hoc structure.

The LDPC code is a kind of linear error correction code with sparse check matrix.The element of its check matrix is 1 except sub-fraction, and other overwhelming majority are zero.Be different from other linear block codess, the LDPC code is represented that by its check matrix H general coded system also is generator matrix G to be converted to check matrix H finish coding.The common encryption algorithm of LDPC code has: G matrix implementation method, RU decomposition algorithm, LU predecomposition algorithm etc.Wherein the RU decomposition algorithm is the most frequently used encryption algorithm of structurized LDPC code.

Summary of the invention

The problem to be solved in the present invention is: adopt the coded system by the row part parallel to have great advantage at code check in greater than 0.5 LDPC code coding circuit, and present LDPC code coding circuit adopts full compute mode parallel or that press the row part parallel, for code check greater than 0.5 LDPC code, by the row coding than needing more barrel shifter and accumulator element by the row coding.

Technical scheme of the present invention is: a kind of low-density checksum LDPC code coding circuit structure of low complex degree is characterized in that:

Using the input message from information source that this circuit structure encodes is: information sequence s and the verification sequence p of input are divided into k by the z position _b=n _b-m _bIndividual group, then Therefore whole code word can be expressed as: $c=\left[\begin{array}{cc}s& p\end{array}\right]=[{\mathrm{<figure-callout\; id="0"\; label="s"\; filenames="HDA00002676706900012.png"\; state="\{\{state\}\}">s</figure-callout>}}_0,{\mathrm{<figure-callout\; id="1"\; label="s"\; filenames="HDA00002676706900012.png,HDA00002676706900021.png"\; state="\{\{state\}\}">s</figure-callout>}}_1,....,s_{k_b-1},{\mathrm{<figure-callout\; id="0"\; label="p"\; filenames="HDA00002676706900012.png"\; state="\{\{state\}\}">p</figure-callout>}}_0,{\mathrm{<figure-callout\; id="1"\; label="p"\; filenames="HDA00002676706900012.png,HDA00002676706900021.png"\; state="\{\{state\}\}">p</figure-callout>}}_1,....,p_{m_b-1}]$

If check matrix H is expressed as: H=[H ₁H ₂], H ₁Corresponding to information sequence part, H ₂Corresponding to check code word part, h _{I, j}Be the matrix in block form in the check matrix H, a minute block size is z;

According to Hc ^T=0 and H ₁And H ₂Feature obtain

Definition

I=0,1 ..., m _b-1, top equation can be expressed as,

According to p ₀Try to achieve: p ₁=λ ₀+ ∏ ₁p ₀

$p_{m_b-1}={\mathrm{\&lambda;}}_{m_b-1}+{\mathrm{\&Pi;}}_1{\mathrm{<figure-callout\; id="0"\; label="p"\; filenames="HDA00002676706900012.png"\; state="\{\{state\}\}">p</figure-callout>}}_0$

p _x+1＝λ _x+p ₀+p _x

p _i+1=λ _i+p _i?i≠0,x,m _b-1

Wherein x is corresponding verification sequence part H in the check matrix H ₂In the first row value of classifying 0 element place as;

Wherein parameter declaration is as follows:

Z is minute class value of low density parity check code;

k _bThe group number that divides into groups according to the z position for inputting information sequence to be encoded;

n _bThe group number that divides into groups according to the z position for the sequence after encoded;

m _bThe group number that divides into groups according to the z position for check code word;

S is information sequence, by obtaining after the grouping of z position:

P is check code word, by obtaining after the grouping of z position:

p _iI the grouping after the z position grouping of pressing for check code word p;

C is encoded whole codeword sequence afterwards;

H is check matrix, H ₁Corresponding to information sequence part, H ₂Corresponding to the check code word part;

X is corresponding verification sequence part H in the check matrix H ₂In first matrix in block form be the line number at the capable place of " 0 ".

According to the computational methods of top check code word, the information sequence of input is according to the grouping input of z position;

This circuit structure comprises check matrix memory 801, barrel shifter group 802, accumulator group 803, first-in first-out buffer memory 804, the first data selector 805, check code word computing module 806, the second data selector 807, address counter 808, control circuit 809 and input control module 810;

Described barrel shifter group 802 comprises m _bIndividual identical barrel shifter group; Accumulator group 803 comprises m _bIndividual identical accumulator; m _bValue identical with the line number of the check matrix of LDPC code; The corresponding accumulator of each barrel shifter group;

The information sequence of input is according to the grouping input of z position, each group information sequence of input through barrel shifter group 802 be stored in check matrix memory 801 in the check matrix of LDPC code by going corresponding multiplying; This multiplying is finished by barrel shifter, and the operation result of barrel shifter is h _{I, j}S _j

The operation of input control circuit 810 controls is: one group of information sequence of every input, finish multiplication operation, and the address of check matrix memory 801 adds 1 simultaneously, provides the value of check matrix next column;

Each group information sequence is through result's process accumulator group 803 of multiplying, and is cumulative by corresponding row;

After the input of all information sequence is complete, namely finished the multiplying each other and accumulating operation by the row grouping of the corresponding position with check matrix of information sequence of input, be λ by going the result who adds up _i

Control circuit 809, the first data selector 805 and check code word computing module 806 are by cumulative, displacement and register circuit, the as a result λ cumulative to piecemeal _iCumulative after again selectively adding up or being shifted, piecemeal calculates check code word p thus; Namely finish the process of whole coding;

At last, the information sequence of input passes through the second data selector 807 continuous wave outputs through first-in first-out buffer memory 804 with check code word, obtains having the code word of fault-tolerant ability.

Description of drawings

Fig. 1 is the position of LDPC code in communication system;

Fig. 2 is a kind of check matrix of LDPC code of the near lower triangular form with quasi-cyclic;

Fig. 3 is the coding circuit structure of the LDPC code of low complex degree;

Fig. 4 is the implementation of the matrix multiplication operation of LDPC code.

Embodiment

In order to understand better the present invention, make a more detailed description below in conjunction with embodiment and place system.

Technical scheme of the present invention is a kind of error correcting code circuitry structure that is applied to the low density parity check code of communication system, this circuit structure is according to the LDPC code check matrix, divide row operation, then ask for the check code word of input message sequence, realization has the low encoding complexity of the quasi-cyclic LDPC code of near lower triangular form; Specific as follows:

This coding circuit structure is the quasi-cyclic LDPC code of near lower triangular form for check matrix; Check matrix H with LDPC code of this characteristic generally adopts the form of piecemeal to represent, each matrix-block behind the piecemeal wherein, and the overwhelming majority is null matrix, and other matrix is the result after the unit matrix cyclic shift of z position, and z is the size of the partitioning of matrix;

In the process of coding, the information sequence of input is also according to the grouping input of z position, and each group information sequence of input carries out by the corresponding multiplying of row through barrel shifter group and the check matrix of LDPC code, and this multiplying is finished by each barrel shifter.The quantity of barrel shifter is identical with the line number of the check matrix of LDPC code in the barrel shifter group.

Input control circuit is controlled one group of information sequence of every input, finishes multiplication operation, and the address of check matrix memory adds 1 simultaneously, provides the value of check matrix next column.Each group information sequence is through the result of multiplying, and is cumulative by corresponding row through the accumulator group, after all information sequence inputs are complete, namely finished input the corresponding position with check matrix of information sequence divide into groups to multiply each other and accumulating operation by going.

Control circuit is controlled the 1st data selector, and check code word calculates module, and by circuit such as cumulative, displacement and registers, to the cumulative result of front face dividing rear the adding up of again add up selectively or be shifted, piecemeal calculates check code word thus.At last, the information sequence of input passes through the 2nd data selector continuous wave output through the first-in first-out buffer memory with the check code word that calculates, and finally obtains information sequence has fault-tolerant ability afterwards through the check matrix coding of this LDPC code code word.

Fig. 1 is the telecommunication system transceiver structure chart, and LDPC is coded in after the information source of transmitter, before the modulation, be used for to improve the reliability of transfer of data, receiver section corresponding the LDPC decoding circuit arranged.

Fig. 2 (a) and (b) be a kind of check matrix of LDPC code of the near lower triangular form with quasi-cyclic, having provided a kind of code check among Fig. 2 (a) is 2/3, code length is the check matrix H of 576 LDPC code, this check matrix adopts the form of the partitioning of matrix to represent, the unit matrix of each data representation length z=24 of form carries out ring shift right result afterwards by the numerical value in the form among Fig. 2 (a) figure, for example the data of the first row first row are carried out ring shift right result afterwards among Fig. 2 (a), are the matrix shown in Fig. 2 (b).Can see that from Fig. 2 (a) the most elements in the form are zero, the sparse property of the check matrix of LDPC code also has been described.

Fig. 3 is the coding circuit structure of the LDPC code with low complex degree that provides, in the process of coding, the information sequence of input is also according to the grouping input of z position, each group information sequence of input carries out by the corresponding multiplying of row through barrel shifter group 802 and the check matrix 801 of LDPC code, and this multiplying is finished by barrel shifter.The quantity of barrel shifter is identical with the line number of the check matrix of LDPC code in the barrel shifter group 802.

Input control circuit 810 is controlled one group of information sequence of every input, finishes multiplication operation, and the address of check matrix memory adds 1 simultaneously, provides the value of check matrix next column.Each group information sequence is through the result of multiplying, and is cumulative by corresponding row through 803 accumulator groups, after all information sequence inputs are complete, namely finished input the corresponding position with check matrix of information sequence divide into groups to multiply each other and accumulating operation by going.

Control circuit 809, the first data selectors 805, and check code word computing module 806, by cumulative, the circuit such as displacement and register, it is rear cumulative that the cumulative result of front face dividing is again selectively added up or is shifted, and piecemeal calculates check code word thus.At last, the information sequence of input passes through the second data selector 807 continuous wave outputs through the first-in first-out buffer memory with the check code word that calculates, and finally obtains information sequence has fault-tolerant ability afterwards through the check matrix coding of this LDPC code code word.

Fig. 4 is the barrel shifter that carries out matrix multiplication operation, and the barrel shift structure that above-mentioned matrix multiplication operation provides in can employing figure realizes.The figure place of the barrel shifter that provides among the figure is z=8, and input data a0-a7, barrel shifter be by the situation of input data s0-s2 control displacement, finally obtains the data d0 that is shifted-d7, and the mux among the figure is the data selector of alternative.

Claims (1)

1. the low-density checksum LDPC code coding circuit structure of a low complex degree is characterized in that:

Use this circuit structure, information sequence s and the verification sequence p of input are divided into k by the z position _b=n _b-m _bIndividual group, then $S=[S_0,S_1,....,S_{k_b-1}],$ $p=[p_0,p_1,....,p_{k_b-1}],$ Therefore whole code word can be expressed as:

$c=\left[\begin{array}{cc}s& p\end{array}\right]=[s_0,s_1,....,s_{k_b-1},p_0,p_1,....,p_{m_b-1}];$

If check matrix H is expressed as: H=[H1 H2], H1 is corresponding to the information sequence part, and H2 is corresponding to the check code word part, and hi, j are the matrix in block form in the check matrix H, i=0,1 ..., m _b-1, j=0,1 ..., k _b-1, a minute block size is z, and i represents line number, and j represents row number, according to Hc ^T=0 and H ₁And H ₂Feature obtain

Definition

I=0,1 ..., m _b-1, top equation can be expressed as,

According to p ₀Try to achieve: p ₁=λ ₀+ ∏ ₁p ₀

$p_{m_b-1}={\mathrm{\&lambda;}}_{m_b-1}+{\mathrm{\&Pi;}}_1{p}_0$

p _x+1=λ _x+p ₀+p _x

p _i+1=λ _i+p _i?i≠0,x,m _b-1

Wherein parameter declaration is as follows:

Z is minute class value of low density parity check code;

k _bThe group number that divides into groups according to the z position for inputting information sequence to be encoded;

n _bThe group number that divides into groups according to the z position for the sequence after encoded;

m _bThe group number that divides into groups according to the z position for check code word;

S is information sequence, by obtaining after the grouping of z position:

P is check code word, by obtaining after the grouping of z position:

p _iI the grouping after the z position grouping of pressing for check code word p;

C is encoded whole codeword sequence afterwards;

H is check matrix, H ₁Corresponding to information sequence part, H ₂Corresponding to the check code word part;

X is corresponding verification sequence part H in the check matrix H ₂In first matrix in block form be the line number at the capable place of " 0 ";

According to the computational methods of top check code word, the information sequence of input is according to the grouping input of z position;

This circuit structure comprises check matrix memory 801, barrel shifter group 802, accumulator group 803, first-in first-out buffer memory 804, the first data selector 805, check code word computing module 806, the second data selector 807, address counter 808, control circuit 809 and input control module 810;

Described barrel shifter group 802 comprises m _bIndividual identical barrel shifter group; Accumulator group 803 comprises m _bIndividual identical accumulator; m _bValue identical with the line number of the check matrix of LDPC code; The corresponding accumulator of each barrel shifter group;

The information sequence of input is according to the grouping input of z position, each group information sequence of input through barrel shifter group 802 be stored in check matrix memory 801 in the check matrix of LDPC code by going corresponding multiplying; This multiplying is finished by barrel shifter, and the operation result of barrel shifter is h _{I, j}S _j

The operation of input control circuit 810 controls is: one group of information sequence of every input, finish multiplication operation, and the address of check matrix memory 801 adds 1 simultaneously, provides the value of check matrix next column;

Each group information sequence is through result's process accumulator group 803 of multiplying, and is cumulative by corresponding row;

After the input of all information sequence is complete, namely finished the multiplying each other and accumulating operation by the row grouping of the corresponding position with check matrix of information sequence of input, be λ by going the result who adds up _i

Control circuit 809, the first data selector 805 and check code word computing module 806 are by cumulative, displacement and register circuit, the as a result λ cumulative to piecemeal _iCumulative after again adding up or being shifted, piecemeal calculates check code word;

At last, the information sequence of input passes through the second data selector 807 continuous wave outputs through first-in first-out buffer memory 804 with check code word, obtains having the code word of fault-tolerant ability.

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