CN117828247B - Fast Fourier transform processing method, integrated circuit and electronic equipment - Google Patents

Fast Fourier transform processing method, integrated circuit and electronic equipment Download PDF

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CN117828247B
CN117828247B CN202410252073.3A CN202410252073A CN117828247B CN 117828247 B CN117828247 B CN 117828247B CN 202410252073 A CN202410252073 A CN 202410252073A CN 117828247 B CN117828247 B CN 117828247B
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butterfly operation
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CN117828247A (en
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段建峰
彭吉生
黄强
许宇卫
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Beijing Thinking Semiconductor Technology Co ltd
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Abstract

The disclosure relates to a fast fourier transform processing method, an integrated circuit and an electronic device, and relates to the technical field of digital processing. A method of processing a fast fourier transform comprising: and operating all data in all physical addresses corresponding to the memory through multistage fast Fourier transform butterfly operation, wherein each stage of fast Fourier transform butterfly operation comprises the following steps: reading initial data from a physical address group corresponding to the memory in parallel through a first sequence, wherein the physical address group comprises part of physical addresses of the memory; and performing butterfly operation on the initial data to obtain target data, and writing the target data into the physical address group in parallel through a second sequence.

Description

Fast Fourier transform processing method, integrated circuit and electronic equipment
Technical Field
The disclosure relates to the technical field of digital processing, in particular to a fast fourier transform processing method, an integrated circuit and electronic equipment.
Background
FFT (Fast Fourier Transform ) is the basis of digital signal processing methods in the field of digital processing. In the FFT in-situ operation process, the hardware area and the power consumption are required to be reduced by compressing the working time of the hardware, so that the area and the power consumption of the hardware are optimized.
Disclosure of Invention
In order to solve the defects in the prior art, the disclosure provides a fast Fourier transform processing method, an integrated circuit and electronic equipment.
In a first aspect, the present disclosure provides a method for processing a fast fourier transform, the method comprising:
And operating all data in all physical addresses corresponding to the memory through multistage fast Fourier transform butterfly operation, wherein each stage of fast Fourier transform butterfly operation comprises the following steps:
Reading initial data from a physical address group corresponding to the memory in parallel through a first sequence, wherein the physical address group comprises part of physical addresses of the memory;
and performing butterfly operation on the initial data to obtain target data, and writing the target data into the physical address group in parallel through a second sequence, wherein the physical address group is different when each stage of the fast Fourier transform butterfly operation is performed, the first sequence and the second sequence are determined according to the base number of the current stage participating in the fast Fourier transform butterfly operation, and the first sequence is different from the second sequence.
In a second aspect, the present disclosure provides an integrated circuit that performs operations on all data in all physical addresses corresponding to a memory through a multi-stage fft butterfly operation, where the integrated circuit includes a data readout module and an execution module, for each stage of fft butterfly operation:
the data reading module is configured to read initial data from a physical address group corresponding to the memory in parallel through a first sequence, wherein the physical address group comprises part of physical addresses of the memory;
The execution module is configured to perform butterfly operation on the initial data to obtain target data, and write the target data into the physical address group in parallel through a second sequence, wherein the physical address group is different when each stage of the fast Fourier transform butterfly operation is performed, the first sequence and the second sequence are determined according to the base number of the current stage participating in the fast Fourier transform butterfly operation, and the first sequence is different from the second sequence.
In a third aspect, the present disclosure provides a non-transitory computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the fast fourier transform processing method of the first aspect.
In a fourth aspect, the present disclosure provides an electronic device comprising:
A memory having a computer program stored thereon;
A processor for executing the computer program in the memory to implement the fast fourier transform processing method of the first aspect.
Through the technical scheme, all data in all physical addresses corresponding to the memory are operated through multistage fast Fourier transform butterfly operation, and each stage of fast Fourier transform butterfly operation comprises: reading initial data from a physical address group corresponding to the memory in parallel through a first sequence; and performing butterfly operation on the initial data to obtain target data, and writing the target data into the physical address group in parallel through a second sequence. In each stage of the fast fourier transform butterfly operation, data reading is performed through a first sequence and data writing is performed through a second sequence, so that the physical address groups of each stage of the fast fourier transform butterfly operation are different. And the multistage fast Fourier transform butterfly operation can read data from a plurality of physical address groups simultaneously, so that parallel reading and parallel writing of the data in the physical addresses are realized, the time of each stage of fast Fourier transform butterfly operation is shortened, the working time of a memory is shortened, and the area and the power consumption required by the memory in the multistage fast Fourier transform butterfly operation process are reduced.
Additional features and advantages of the present disclosure will be set forth in the detailed description which follows.
Drawings
The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification, illustrate the disclosure and together with the description serve to explain, but do not limit the disclosure. In the drawings:
Fig. 1 is a schematic diagram of a first portion of logical addresses and a second portion of logical addresses corresponding to each stage of FFT butterfly operation, according to an exemplary embodiment of the present disclosure.
Fig. 2 is a schematic diagram illustrating a mapping relationship of a physical address group and a logical address group according to an exemplary embodiment of the present disclosure.
Fig. 3 is a schematic diagram of a first portion of logical addresses and a second portion of logical addresses corresponding to each stage-based 2FFT butterfly operation, according to an exemplary embodiment of the present disclosure.
Fig. 4 is a schematic diagram of a mapping relationship of a physical address group to a logical address group of a radix-2 FFT butterfly operation, according to an exemplary embodiment of the present disclosure.
Fig. 5 is a schematic diagram of a third stage radix-2 FFT butterfly operation shown in accordance with an exemplary embodiment of the present disclosure.
Fig. 6 is a schematic diagram of a first portion of logical addresses and a second portion of logical addresses corresponding to each stage-based 4FFT butterfly operation, according to an exemplary embodiment of the present disclosure.
Fig. 7 is a schematic diagram of a mapping relationship of a physical address group to a logical address group of a radix-4 FFT butterfly operation, according to an exemplary embodiment of the disclosure.
Fig. 8 is a schematic diagram of a third stage radix-4 FFT butterfly operation shown in accordance with an exemplary embodiment of the disclosure.
Fig. 9 is an addressing flow diagram of a destination register address, shown according to an exemplary embodiment of the present disclosure.
FIG. 10 is an addressing block diagram of a destination register address, shown according to an exemplary embodiment of the present disclosure.
Fig. 11 is a sequence of high and low groups in a mixed base, shown according to an exemplary embodiment of the present disclosure.
Fig. 12 is a logical address schematic of a pure base shown according to an exemplary embodiment of the present disclosure.
Fig. 13 is a schematic diagram of logical addresses of a hybrid base shown according to an exemplary embodiment of the present disclosure.
FIG. 14 is a schematic diagram of a memory order and write pipeline in registers of a base 4/base 2 mixed base transition stage, shown according to an exemplary embodiment of the present disclosure.
Fig. 15 is a block diagram of an integrated circuit shown in accordance with an exemplary embodiment of the present disclosure.
Fig. 16 is a block diagram of an electronic device, shown in accordance with an exemplary embodiment of the present disclosure.
Detailed Description
Specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the disclosure, are not intended to limit the disclosure.
It should be noted that, all actions for acquiring signals, information or data in the present disclosure are performed under the condition of conforming to the corresponding data protection rule policy of the country of the location and obtaining the authorization given by the owner of the corresponding device.
As described in the background art, in the FFT in-situ operation process, the area and power consumption of the hardware need to be reduced by compressing the working time of the hardware.
In the related art, the chinese patent application No. 201410095193.3 discloses a fast fourier transform accelerator. Comprising the following steps: the processing is performed for a subset of the input points by a plurality of constant geometry butterflies, each constant geometry butterfly comprising a device of data. When the plurality of constant geometry butterflies has completed, the input points return to the original or "natural" order. One or more in-situ operations are performed as needed to combine multiple sets of points. For example, a 1024-point time-decimated FFT may use five stages of radix-4 butterfly. The first three phases can be calculated by using a constant geometry run on 16 64 point subsets of 1024 points, and the last two phases can be calculated using an in-situ FFT method.
The inventors found that although the FFT in-situ operation can be realized in the related art, when the patent is applied to actual hardware, in order to compress the operating time of the hardware, data of each butterfly operation needs to be read out in parallel and written in parallel. For example, a radix-2 FFT butterfly operation requires reading in 2-way data from memory in parallel and writing out the 2-way output of the butterfly operation to memory in parallel. Based on 4FFT butterfly operation, 4 paths of data need to be read in from a memory in parallel, and 4 paths of output of the butterfly operation need to be written out to the memory in parallel. That is, the related art does not solve the problem of how to implement parallel reading and parallel writing of data in an ASIC (Application SPECIFIC INTEGRATED Circuit) during FFT butterfly operation and in-situ operation.
In view of this, the embodiments of the present disclosure disclose a fast fourier transform processing method, an integrated circuit, and an electronic device, which can read and write data in a memory in parallel, thereby shortening the time of each stage of FFT butterfly operation.
The embodiment of the disclosure provides a fast fourier transform processing method, which may include:
and performing operation on all data in all physical addresses corresponding to the memory through multistage fast Fourier transform butterfly operation, wherein each stage of fast Fourier transform butterfly operation can comprise:
Reading initial data from a physical address group corresponding to the memory in parallel through a first sequence, wherein the physical address group comprises part of physical addresses of the memory;
And performing butterfly operation on the initial data to obtain target data, and writing the target data into a physical address group in parallel through a second sequence, wherein the physical address group is different when the fast Fourier transform butterfly operation is performed on each stage, the first sequence and the second sequence are determined according to the base number of the current stage participating in the fast Fourier transform butterfly operation, and the first sequence and the second sequence are different.
It should be noted that, because the read-write address rules of each stage of FFT butterfly operation in the memory are different, in order to ensure parallel read-write of each stage of FFT butterfly operation, in the embodiment of the disclosure, the read-write address of each stage of FFT butterfly operation in the memory is designed, and the result of each stage of FFT butterfly operation is transposed through different read-write sequences. The multistage fast Fourier transform butterfly operation can read data from a plurality of different physical address groups simultaneously, and parallel reading and writing of data in physical addresses by the FFT butterfly operation in the in-situ operation are realized.
It should be understood that, because the same memory can only read data once in the same clock, in order to realize parallel reading and writing of data in the memory by each stage of FFT butterfly operation, the memory is segmented in advance to obtain a plurality of sub-memories, so that each stage of FFT butterfly operation can read data from different sub-memories at the same time, and parallel reading and writing of data in the memory are realized.
It is worth to be noted that, the physical address group of each stage of FFT butterfly operation may be determined in advance according to the logical address and the mapping relationship between the logical address and the physical address before performing the multi-stage FFT butterfly operation; the method can also be determined according to the mapping relation between the logical address and the physical address in the process of multistage FFT butterfly operation, for example, the physical address group of the next stage FFT butterfly operation is determined after the present stage FFT butterfly operation is finished.
In each stage of the fft butterfly operation in the embodiment of the present disclosure, data read is performed through a first order and data write is performed through a second order, so that a result of the fft butterfly operation is transposed, thereby switching a physical address group corresponding to each stage of fft butterfly operation. The multi-stage fast Fourier transform butterfly operation can read data from a plurality of physical address groups simultaneously, so that parallel reading and parallel writing of the data in the physical addresses are realized, the area of a memory participating in the butterfly operation is reduced, the time of each stage of fast Fourier transform butterfly operation is shortened, the working time of the memory is shortened, and the power consumption of the memory is reduced.
In order to facilitate a better understanding of the fast fourier transform processing method provided by the embodiments of the present disclosure, the steps of the method are illustrated in detail below.
In a possible embodiment, the set of physical addresses may be obtained by:
determining a logic address group corresponding to each stage of fast Fourier transform butterfly operation in a logic address addressing mode;
dividing the logical addresses into a first part of logical addresses and a second part of logical addresses according to the logical address group, the number of points of the fast Fourier transform butterfly operation and the cardinal number of the current stage of the fast Fourier transform butterfly operation, wherein the first part of logical addresses are used for determining data of the fast Fourier transform butterfly operation, and the second part of logical addresses are used for recording the calculation times of the fast Fourier transform butterfly operation in the current stage in the fast Fourier transform butterfly operation process;
And determining a physical address group corresponding to the first part of logical addresses from the physical addresses according to the mapping relation between the logical addresses and the physical addresses.
Specifically, the first part of logical address is used for selecting the input data of the present-stage FFT butterfly operation. After each time of FFT butterfly operation is completed, the second part of logical addresses adds 1 to the calculated times (index) of the FFT butterfly operation, and counts and accumulates, so that the index of the FFT butterfly operation is recorded. The accumulation order in the second partial logical address may be any order except for the first partial logical address of the next stage. In the second part of logical addresses, the first part of logical addresses of the next stage are accumulated in a preferential manner. Therefore, the second part of logic addresses needs to be adjusted in sequence when accumulating, the first part of logic addresses of the next stage are partially adjusted to the lowest bits of the second part of logic addresses, and the adjusted second part of logic addresses are called second part of logic accumulated addresses. In the embodiment of the disclosure, the accumulation sequence is from the low order address group to the high order address group in the second part of logic accumulation addresses, so as to avoid missing the FFT butterfly operation of a certain stage.
It should be understood that accumulation in the presently disclosed embodiments refers to accumulating the low order bits in the binary number. If the binary number in the second part of the logic accumulation address is 0010, the second part of the logic accumulation address performs one-time counting accumulation to obtain a binary number 0011, the second part of the logic accumulation address performs two-time counting accumulation to obtain a binary number 0100, the second part of the logic accumulation address performs three-time counting accumulation to obtain a binary number 0101, and so on.
It should be noted that, the physical address is an address corresponding to the memory, and the arrangement sequence of each address group in the physical address varies with the current stage of the FFT. The logical address may be a calculated address corresponding to a memory in the FFT in-situ operation algorithm, and the arrangement order of each address group in the logical address is fixed.
Wherein each register stores one of a plurality of data output by a butterfly operation. The number of registers in the FFT butterfly operation process is determined according to the cardinality of the current stage. For example, the radix-2 FFT corresponds to 2×2=4 registers; the radix-4 FFT butterfly operation corresponds to 4x4 = 16 registers; the base 4/base 2 hybrid FFT has 16 registers for the base 4 stage and 4 registers for the base 2 stage.
It should be understood that, as shown in fig. 1, when each stage of FFT butterfly operation is performed, the division of the first part of logical address and the second part of logical address is different, and the logical addresses need to be divided again according to the logical address group, the number of points of the FFT butterfly operation and the cardinality of the current stage of the FFT butterfly operation. As shown in fig. 2, the mapping relationship between the logical address and the physical address of each stage of FFT butterfly operation is different.
It should be noted that, the logical addresses and the physical addresses are grouped, and the number of address groups corresponding to the logical addresses after grouping is the same as the number of address groups corresponding to the physical addresses. The logical address addressing may be from a lower address group to an upper address group of the logical address.
Illustratively, when 1 bit is included in each address group, in the process of addressing from the lower address group to the higher address group, bit0 is included in the first address group, bit1 is included in the second address group, bits 2, … are included in the third address group, and bitm is included in the m-th address group. When each address group comprises x bits and x is more than or equal to 2, as shown in fig. 2, in the process of addressing from a low-order address group to a high-order address group, the first address group comprises bits 0-bitn, the second address group comprises bits (n+1) -bits (n+x), the third address group comprises bits (n+x+1) -bits (n+2x), …, and the m-th address group comprises bits [ n+ (m-2) x+1] bits [ n+ (m-1) x ], m is more than or equal to 2, and n=x-1.
In the embodiment of the disclosure, a logical address is divided into a first part of logical address and a second part of logical address according to a logical address group, the number of points of FFT butterfly operation and the base number of the current stage of FFT butterfly operation, and a physical address group corresponding to the first part of logical address is determined according to the mapping relation between the logical address and the physical address. According to the mapping between the logical address and the physical address, the physical address group of each stage of FFT butterfly operation is determined, and the physical address group comprises addresses of a plurality of sub-memories obtained by partitioning the memory, so that the multistage FFT butterfly operation reads data from the plurality of physical address groups simultaneously, and the parallel reading and the parallel writing of the data in the memory are realized, thereby realizing the parallel processing of the FFT butterfly operation in the in-situ operation.
In a possible implementation, dividing the logical address into the first partial logical address and the second partial logical address according to the logical address group, the number of points of the butterfly operation of the fast fourier transform, and the radix of the current stage of the fast fourier transform may include:
grouping the logic addresses according to the number of points of the butterfly operation of the fast Fourier transform and the cardinality of the current stage of the fast Fourier transform to obtain a first target number of address groups;
determining location information of the logical address group in a first target number of address groups;
And dividing the logical address group in the logical addresses into a first partial logical address according to the position information, and taking the rest address group in the logical addresses as a second partial logical address.
It should be noted that, the first target number may be determined according to the number of times that the number of points of the FFT butterfly operation is the radix of the FFT butterfly operation. For example, a 32-point radix 2FFT butterfly operation, 5 =32, the first target number is 5. 1024-point basis 2FFT butterfly operation, 2 10 =1024, the first target number is 10. The 64-point radix-4 FFT butterfly operation, 4 3 =64, the first target number is 3. 1024-point basis 4FFT butterfly operation, 4 5 =1024, the first target number is 5.
For example, referring to fig. 3, for a 32-point radix 2FFT butterfly operation, the 32-point logical addresses are grouped to obtain 5 address groups, the 5 address groups are arranged in a row from a low-order address group to a high-order address group, each address group has 1 bit, and the 5 address groups are respectively a 5-order address group bit4, a 4-order address group bit3, a 3-order address group bit2, a 2-order address group bit1, and a 1-order address group bit0, and each stage needs to perform 16 FFT butterfly operations. During the first-stage FFT butterfly operation, a logical address group is determined to be a No. 1 address group bit0 in a logical address addressing mode, the No. 1 address group bit0 is divided into a first part of logical addresses, and a No. 5 address group bit4, a No. 4 address group bit3, a No. 3 address group bit2 and a No. 2 address group bit1 are used as a second part of logical addresses. Similarly, during the second-stage FFT butterfly operation, dividing the address group bit1 into a first part of logic addresses, and taking the address group bit4, the address group bit3, the address group bit2 and the address group bit0 as a second part of logic addresses; in the third-stage FFT butterfly operation, dividing an address group bit2 into a first part of logical addresses, and taking an address group bit4, an address group bit3, an address group bit1 and an address group bit0 as a second part of logical addresses; in the fourth-stage FFT butterfly operation, dividing an address group bit3 into a first part of logical addresses, and taking an address group bit4, an address group bit2, an address group bit1 and an address group bit0 as a second part of logical addresses; and in the fifth-stage FFT butterfly operation, dividing the address group bit4 into a first part of logical addresses, and taking the address group bit3, the address group bit2, the address group bit1 and the address group bit0 as a second part of logical addresses.
For example, referring to fig. 6, for 1024-point based 4FFT butterfly operation, 1024-point logical addresses are grouped to obtain 5 address groups, the 5 address groups are arranged in a row from a lower address group to an upper address group, each address group has 2 bits, the 5 address groups are respectively 5 # address groups bit9 and bit8, 4 # address groups bit7 and bit6, 3 # address groups bit5 and bit4, 2 # address groups bit3 and bit2, and 1 # address groups bit1 and bit0, and 256 FFT butterfly operations are required to be performed at each stage. If the 32-point base 2FFT butterfly operation is obtained in the same way, in the first stage FFT butterfly operation, dividing the address groups bit1 and bit0 into a first part of logical addresses, and taking the address groups bit9 and bit8, the address groups bit7 and bit6, the address groups bit5 and bit4, and the address groups bit3 and bit2 as second part of logical addresses; during the second-stage FFT butterfly operation, dividing the address groups bit3 and bit2 into first partial logic addresses, and taking the address groups bit9 and bit8, the address groups bit7 and bit6, the address groups bit5 and bit4 and the address groups bit1 and bit0 as second partial logic addresses; during the third-stage FFT butterfly operation, dividing the address groups bit5 and bit4 into first partial logic addresses, and taking the address groups bit9 and bit8, the address groups bit7 and bit6, the address groups bit3 and bit2 and the address groups bit1 and bit0 as second partial logic addresses; in the fourth-stage FFT butterfly operation, dividing a 4-number address group bit7 and a bit6 into a first part of logic addresses, and taking a 5-number address group bit9 and a bit8, a 3-number address group bit5 and a bit4, a 2-number address group bit3, a bit2 and a 1-number address group bit1 and a bit0 as a second part of logic addresses; and during the fifth-stage FFT butterfly operation, dividing the address groups bit9 and bit8 into first partial logic addresses, and taking the address groups bit7 and bit6, the address groups bit5 and bit4, the address groups bit3 and bit2 and the address groups bit1 and bit0 as second partial logic addresses.
In the embodiment of the disclosure, the logical addresses are grouped according to the number of the FFT butterfly operation points and the base number of the current stage of the FFT butterfly operation, the logical addresses are divided into a first part of logical addresses and a second part of logical addresses according to the position information of the logical address groups in the grouped address groups, the physical address groups are determined through the first part of logical addresses, so that the data input by the current stage of the FFT butterfly operation is selected, and the count of the FFT butterfly operation is recorded through the second part of logical addresses, so that the FFT butterfly operation of a certain stage is prevented from being missed.
In a possible implementation, the physical address group of the data parallel read and data parallel write of each stage of the fft butterfly operation is a high-order physical address group of the physical address.
It should be appreciated that during the FFT butterfly operation, the logical addresses for reading and writing data between the two stages of FFT butterfly operations are the same. In order to realize multi-path parallel reading and writing of data in a memory, physical addresses for reading and writing of data are different between two adjacent stages of FFT butterfly operations.
With reference to fig. 1 and fig. 2, in each stage of FFT butterfly operation, the position of the first partial logical address is not changed, so that the logical addresses for reading and writing data between two adjacent stages of FFT butterfly operation processes are ensured to be the same. In each stage of FFT butterfly operation, the first part of physical addresses in the physical addresses are moved to the position of the high-order addresses, namely, the low-order address group in the physical addresses is moved to the high-order address group, so that the physical addresses for reading and writing data between two adjacent stages of FFT butterfly operation processes are different. Because the lower order address group in the physical address is shifted to the higher order address group in each stage of FFT butterfly operation, the mapping relationship between the logical address and the physical address of each stage of FFT butterfly operation is different.
In a possible embodiment, the first order and the second order may be determined by:
Determining a target register address according to the base number of the current stage of the fast Fourier transform butterfly operation, wherein the target register address can be a matrix constructed by taking the base number as a dimension;
The address order in the first partial logical address of the current stage is taken as a first order, and the column order in the target register address is taken as a second order.
It should be noted that the radix of the FFT butterfly operation is different, and the corresponding register addresses are different. For example, referring to fig. 5, the radix 2FFT butterfly operation, the corresponding radix 2 stage destination register address may be a 2x2 matrix of 4 registers; referring to fig. 8, the radix-4 FFT butterfly operation, the corresponding destination register address may form a 4x4 matrix for 16 registers; referring to fig. 12, a radix-4/radix-2 hybrid FFT butterfly operation, the corresponding radix-4 target register address may be a 4x4 matrix of 16 registers, and the radix-2 target register address may be a 2x2 matrix of 4 registers.
It should be appreciated that the radix of the FFT butterfly may determine the number of results per FFT butterfly. If the radix-2 FFT butterfly operation obtains 2 operation results in each FFT butterfly operation; the radix-4 FFT butterfly operation obtains 4 operation results for each FFT butterfly operation.
It should be understood that, in various FFT butterfly operations such as the radix-2 FFT butterfly operation and the radix-4 FFT butterfly operation, the first order may be the address fetching order in the corresponding first partial logical address, and the second order may be the column order of the corresponding target register address. The first order may be an order in which the butterfly result is written to the target register address, and the second order may be an order in which the butterfly result is read from the target register address. Because each register in the target register address stores one data, the data in each register in the target register address can be read out and written in parallel through different sequences, so that the FFT butterfly operation result of each stage is transposed, and then the physical reading address and the physical writing address of each stage are determined according to the mapping relation of the logical address and the physical address, so that all the data in the memory are refreshed through the multi-stage FFT butterfly operation. The write physical address of the FFT butterfly operation of the present stage in the FFT butterfly operation process is the read physical address of the next stage of FFT butterfly operation.
In a possible implementation, referring to fig. 9, the addressing mode of the destination register address may include:
In step S91, a supplemental address of the current stage is determined from the first partial logical address of the current stage and the first partial logical address of the next stage of the fft butterfly operation.
It should be noted that the complementary address of the current stage may be selected from the second partial logical address of the next stage. The length of the supplementary address bit of the current stage is the difference between the lengths of the two first part logical addresses, such as the difference obtained by subtracting the length of the first part logical address of the next stage from the length of the first part logical address of the current stage. The first partial logical address of the current stage causes the result of each butterfly to be written into the register set in parallel at the same clock. For pure bases, no supplemental address is included in the register address.
In step S92, the arrangement order of the destination register addresses is determined based on the first partial logical address of the current stage, the first partial logical address of the next stage, and the complementary address of the current stage.
As shown in fig. 10, the order of the target register addresses may be the order of the first partial logical address of the next stage, the first partial logical address of the current stage, and the supplementary address of the current stage.
In step S93, the address length of the destination register address is determined from the high radix of the current stage of the fft butterfly operation.
It should be noted that, as shown in fig. 11, the high-radix stage is arranged in front of the low-radix stage in the FFT stage operation, and the register set is responsible for the transposition of data, and the low-radix stage operation is generally put to the last stage. Because of the in-situ operation, only one group of parallel memory and registers is provided, the sequence is adjusted in the second part of logic addresses during accumulation, the first part of logic addresses of the next stage are partially adjusted to the lowest order of the second part of logic addresses, and the adjusted second part of logic addresses are called second part of logic accumulation addresses. And inputting the current butterfly operation result into a register group in parallel, and writing each register in the register group into a memory in parallel according to columns.
It should be noted that, when the FFT butterfly operation is a non-transition stage of a pure base or a mixed base, the square value of the base is determined, and the square value is determined to be the power of a2, then the address length of the target register address is a. Illustratively, as shown in fig. 12, the address length of the target register address of the base 2FFT is log2 (2 2) =2 bits, and then the addressing of the target register address is n0, c0. The address length of the target register address of the radix-4 FFT butterfly operation is log2 (4 2) =4 bits, and the addressing of the target register address is n1, n0, c1, c0.
It should be noted that, when the FFT butterfly operation is a transition stage of the mixed base, the square of the high base of the current base of the FFT butterfly operation is determined, a square value is obtained, and if the square value is determined to be the power of a of 2, the address length of the target register address is a. Illustratively, as shown in fig. 13, the target register address of the radix-4/radix-2 mixed-radix FFT butterfly operation has an address length of log2 (4 2) =4 bits. The first partial logical address of the current stage is c1, c0, and the first partial logical address of the next stage is n0. The complementary address bit length is 1 and p0, and the addressing of the target register addresses is n0, c1, c0 and p0. The target register address of the radix 8/radix 4 mixed radix FFT butterfly operation has an address length of log2 (8 2) =6 bits. The first part of logic addresses of the current stage are c2, c1 and c0, and the first part of logic addresses of the next stage are n1 and n0. The complementary address bit length is 1 and p0, and the addressing of the target register addresses is n1, n0, c2, c1, c0 and p0.
It should be noted that, whether the FFT butterfly operation adopts a pure basis or a mixed basis needs to be determined according to the number of points, if the FFT butterfly operation is calculated only by the radix 2FFT butterfly operation when the number of points is large, the FFT butterfly operation requires a long time, which results in low FFT butterfly operation efficiency, so that the FFT butterfly operation is calculated by the mixed radix butterfly operation when the number of points is large.
Illustratively, the radix-2 FFT butterfly is 2 i points, such as 32 points; the radix-4 FFT butterfly is (2 2）i, e.g., 1024; the radix-8 FFT butterfly is (2 3）i, e.g., 4096; the radix-4/radix-2 FFT butterfly is 2 i; not (2 2）i, e.g., 512).
It should be appreciated that in a2 i point radix 2FFT butterfly operation, the 2 i point logical addresses are aligned with i bits. Each stage of FFT butterfly operation needs to divide i bit addresses into two parts again, wherein i-1 bit is responsible for the increment of the butterfly operation number, and 1 bit is responsible for the selection of two paths of data during butterfly operation. Each butterfly operation, the data of two addresses is determined by 1 bit. There are 2 （i-1） butterfly operations in each stage, and 2 （i-1） butterfly operations are counted by the remaining (i-1) bits. (2 2）i Point based 4FFT butterfly, 2 2i Point logical addresses are in a group of two bits, 2i bits are arranged in a row, each stage of FFT butterfly needs to divide the 2i bits address into two parts again, wherein 2 i-2=2 (i-1) bits are responsible for the increment of the butterfly operand number, 2 bits are responsible for the selection of four paths of data when the butterfly is operated, each butterfly operation, the data of four parallel addresses are determined by 2 bits, there are (2 2）（i-1） butterfly operations in each stage, the 2 2）（i-1） butterfly operations are counted by the remaining 2 (i-1) bits, in the hybrid FFT butterfly operation, each stage of FFT butterfly operation is calculated by the corresponding pure based butterfly operation.
In a possible implementation, in case the fft butterfly is pure or the fft is hybrid and the current stage is a non-transitional stage, the data of the fft butterfly may be stored in the target register address in the first order by:
and storing the data of the fast Fourier transform butterfly operation according to the sequence of the preceding sequence and the following sequence of the target register address.
For example, referring to fig. 5, the target register address corresponding to the radix-2 FFT butterfly operation is a 2x2 matrix formed by 4 registers, each butterfly operation of the present stage FFT butterfly operation obtains two results, and the first part of logic of the next stage FFT butterfly operation in the second part of logic address is accumulated to obtain 2x2 = 4 results. For these 4 results, the order of the first row 0,1 and the second row 2, 3 is written in parallel into the four registers. Similarly, referring to fig. 8, the target register address corresponding to the radix-4 FFT butterfly operation is a 4x4 matrix formed by 16 registers, four results of each butterfly operation of the present stage FFT butterfly operation are accumulated on the first partial logical address of the next stage FFT butterfly operation in the second partial logical address, so as to obtain 4x 4=16 results. For these 16 results, the first behavior 0,1, 2, 3, the second behavior 4, 5, 6, 7, the third behavior 8, 9, 10, 11, the fourth behavior 12, 13, 14, 15 are written in parallel into sixteen registers in the order of the first behavior 0,1, 2, 3.
In a possible embodiment, in case the current stage of the fft butterfly is a mixed-base transition stage, the data of the fft butterfly may be stored in the destination register address in the first order by:
the destination register address is divided into two intervals.
For the same interval, determining target registers of two adjacent rows and one column in the interval, and storing data of the fast Fourier transform butterfly operation according to the Z-shaped sequence;
and storing the data of the fast Fourier transform butterfly operation according to the sequence of the different sections in the target register address from top to bottom according to the different sections.
It should be noted that, in the case where the FFT butterfly operation is a mixed base, the transition stage cannot implement transposition by using the target register address corresponding to the pure base, and the data reading amount of the FFT butterfly operation performed during the high base operation is larger than the data reading amount of the FFT butterfly operation performed during the low base operation, which may result in that the working time of the memory cannot be reduced to an ideal state, for example, the data reading amount of the base 4FFT butterfly operation is larger than the data reading amount of the base 2FFT butterfly operation, so that a special target register address is provided for the transition stage of the mixed base in the embodiment of the disclosure.
For example, referring to fig. 14, the target register address corresponding to the base 4/base 2 hybrid FFT butterfly operation transition stage is a 4x4 matrix formed by 16 registers, four results of each butterfly operation of the present stage FFT butterfly operation are respectively accumulated on the first part of logical addresses of the next stage FFT butterfly operation in the second part of logical addresses, so as to obtain 4x 4=16 results. For these 16 results, the first actions 0, 4, 1, 5, the second actions 2, 6, 3, 7 are written in the section a in the order of the section a, the section B, and the second actions 10, 14, 11, 15 are written in the order of the first actions 8, 12, 9, 13 in the section B in parallel in the 16 registers.
The following describes a processing method of the FFT butterfly operation provided in the present disclosure, taking a 32-point radix 2FFT butterfly operation, a 1024-point radix 4FFT butterfly operation, and a 512-point radix 4/radix 2 hybrid FFT butterfly operation as examples.
1. 32-Point radix 2FFT butterfly:
As shown in fig. 3, the 32-point logical addresses are aligned in 5 bits. Each stage of FFT butterfly operation needs to divide the 5 bit address into two parts again, wherein 4 bits are responsible for the increment of the number of butterfly operations, and 1 bit is responsible for the selection of two paths of data during butterfly operation. Each butterfly operation, the data of two addresses is determined by 1 bit. There are 16 butterfly operations in each stage, and the 16 butterfly operations are counted by the remaining 4 bits. If the first level FFT butterfly operation is performed, dividing bit0 into a first part of logical addresses, and taking bit4, bit3, bit2 and bit1 as a second part of logical addresses; dividing bit1 into a first part of logical addresses and taking bit4, bit3, bit2 and bit0 as a second part of logical addresses during the second-stage FFT butterfly operation; dividing bit2 into a first part of logical addresses and taking bit4, bit3, bit1 and bit0 as a second part of logical addresses during the third-stage FFT butterfly operation; dividing bit3 into a first part of logical addresses and taking bit4, bit2, bit1 and bit0 as a second part of logical addresses during fourth-stage FFT butterfly operation; during the fifth-stage FFT butterfly operation, bit4 is divided into a first part of logical addresses, and bit3, bit2, bit1 and bit0 are used as a second part of logical addresses.
As shown in fig. 4, the mapping relationship between the logical address and the physical address of each stage of FFT butterfly operation may be: aiming at the first-stage FFT butterfly operation, logical addresses are bit4, bit3, bit2, bit1 and bit0 in sequence from high order to low order, physical addresses are bit0, bit4, bit3, bit2 and bit1 in sequence from high order to low order, and the logical address group bit0 corresponds to the physical address group bit0; aiming at the second-stage FFT butterfly operation, the logical addresses are bit4, bit3, bit2, bit1 and bit0 in sequence from high order to low order, the physical addresses are bit1, bit4, bit3, bit2 and bit0 in sequence from high order to low order, and the logical address group bit1 corresponds to the physical address group bit1; aiming at the butterfly operation of the third-stage FFT, the logical addresses are bit4, bit3, bit2, bit1 and bit0 in sequence from high order to low order, the physical addresses are bit2, bit4, bit3, bit1 and bit0 in sequence from high order to low order, and the logical address group bit2 corresponds to the physical address group bit2; aiming at fourth-level FFT butterfly operation, logical addresses are bit4, bit3, bit2, bit1 and bit0 in sequence from high order to low order, physical addresses are bit3, bit4, bit2, bit1 and bit0 in sequence from high order to low order, and logical address group bit3 corresponds to physical address group bit3; for the fifth-stage FFT butterfly operation, the logical addresses are bit4, bit3, bit2, bit1 and bit0 in sequence from high order to low order, the physical addresses are bit4, bit3, bit2, bit1 and bit0 in sequence from high order to low order, and the logical address group bit4 corresponds to the physical address group bit4.
The process of each stage of FFT butterfly operation is completely the same, taking the third stage of FFT butterfly operation as an example, as shown in FIG. 5, according to the division mode of the logical address and the mapping relation between the logical address and the physical address of the third stage of FFT butterfly operation, the physical addresses of bit2, bit4, bit3, bit1 and bit0 can be determined, and the physical addresses of bit3, bit4, bit2, bit1 and bit0 can be written. bit2 may indicate the memory read and bit3 may indicate where in the memory the data was read. The pipelined processing between the third stage FFT butterfly and the fourth stage FFT butterfly may include: bit3 in 4 bits in the logic address is accumulated, bit3 corresponding to the reading physical address is also accumulated, so that a 2x2 matrix constructed by 4 registers is formed, and then the matrix is written into the 4 registers in parallel according to rows for caching, and is read out and written into the physical address according to columns. Since the butterfly operation can only be performed once per clock, the process of actually writing the physical address is pipelined.
2. 1024 Point radix 4FFT butterfly operation:
as shown in fig. 6, 1024-point logical addresses are grouped into two bits, 10 bits being aligned. Each stage of FFT butterfly operation needs to divide 10 bit addresses into two parts again, wherein 8 bits are responsible for the increment of the number of butterfly operations, and 2 bits are responsible for the selection of four paths of data during butterfly operation. Each butterfly operation, the data of four parallel addresses is determined by 2 bits. There are 256 butterfly operations in each stage, and 256 butterfly operations are counted by the remaining 8 bits. If the first level FFT butterfly operation is performed, dividing bit0 and bit1 into a first part of logic addresses, and taking bit9 and bit8, bit7 and bit6, bit5 and bit4, bit3 and bit2 as a second part of logic addresses; during the second-stage FFT butterfly operation, bit3 and bit2 are divided into a first part of logic addresses, and bit9 and bit8, bit7 and bit6, bit5 and bit4, bit1 and bit0 are used as a second part of logic addresses; during the third-stage FFT butterfly operation, bit5 and bit4 are divided into a first part of logic addresses, and bit9 and bit8, bit7 and bit6, bit3, bit2, bit1 and bit0 are used as a second part of logic addresses; in the fourth-stage FFT butterfly operation, bit7 and bit6 are divided into a first part of logic addresses, and bit9 and bit8, bit5 and bit4, bit3, bit2, bit1 and bit0 are used as a second part of logic addresses; during the fifth-stage FFT butterfly operation, bit9 and bit8 are divided into first partial logic addresses, and bit7 and bit6, bit5 and bit4, bit3, bit2, bit1 and bit0 are used as second partial logic addresses.
As shown in fig. 7, the mapping relationship between the logical address and the physical address of each stage of FFT butterfly operation may be: aiming at the first-stage FFT butterfly operation, logical addresses are bit9 and bit8, bit7 and bit6, bit5 and bit4, bit3 and bit2, bit1 and bit0 in sequence from high order to low order, physical addresses are bit1 and bit0, bit9 and bit8, bit7 and bit6, bit5 and bit4, bit3 and bit2 in sequence from high order to low order, and logical address groups bit1 and bit0 correspond to physical address groups bit1 and bit0; aiming at the second-stage FFT butterfly operation, logical addresses are bit9 and bit8, bit7 and bit6, bit5 and bit4, bit3 and bit2, bit1 and bit0 in sequence from high order to low order, physical addresses are bit3 and bit2, bit9 and bit8, bit7 and bit6, bit5 and bit4, bit1 and bit0 in sequence from high order to low order, and logical address groups bit3 and bit2 correspond to physical address groups bit3 and bit2; aiming at the butterfly operation of the third-stage FFT, the logical addresses are bit9 and bit8, bit7 and bit6, bit5 and bit4, bit3 and bit2, bit1 and bit0 in sequence from high to low, the physical addresses are bit5 and bit4, bit9 and bit8, bit7 and bit6, bit3 and bit2, bit1 and bit0 in sequence from high to low, and the logical address groups bit5 and bit4 correspond to the physical address groups bit5 and bit4; aiming at fourth-level FFT butterfly operation, logical addresses are bit9 and bit8, bit7 and bit6, bit5 and bit4, bit3 and bit2, bit1 and bit0 in sequence from high order to low order, physical addresses are bit7 and bit6, bit9 and bit8, bit5 and bit4, bit3 and bit2, bit1 and bit0, and logical address groups bit7 and bit6 correspond to physical address groups bit7 and bit6 in sequence from high order to low order; for the fifth level FFT butterfly operation, the logical addresses are bit9 and bit8, bit7 and bit6, bit5 and bit4, bit3 and bit2, bit1 and bit0 in sequence from high order to low order, the physical addresses are bit9 and bit8, bit7 and bit6, bit5 and bit4, bit3 and bit2, bit1 and bit0 in sequence from high order to low order, and the logical address groups bit9 and bit8 correspond to the physical address groups bit9 and bit8.
The process of each stage of FFT butterfly operation is completely the same, taking the third stage of FFT butterfly operation as an example, as shown in FIG. 8, according to the division mode of the logical address and the mapping relation between the logical address and the physical address of the third stage of FFT butterfly operation, the physical addresses of bit5 and bit4, bit9 and bit8, bit7 and bit6, bit3 and bit2, bit1 and bit0, and the physical addresses of bit7 and bit6, bit9 and bit8, bit5 and bit4, bit3 and bit2, bit1 and bit0 can be determined. bits 5 and 4 may indicate the memory being read and bits 7 and 6 may indicate where in the memory the data is being read. The pipelined processing between the third stage FFT butterfly and the fourth stage FFT butterfly may include: and accumulating bit7 and bit6 in 4 bit groups in the logical address, accumulating bit7 and bit6 corresponding to the read physical address, forming a 4x4 matrix constructed by 16 registers, writing the matrix into the 16 registers in parallel according to rows, caching, and reading and writing the matrix into the physical address according to columns. Since the butterfly operation can only be performed once per clock, the process of actually writing the physical address is pipelined.
3. 512-Point radix-4-radix-2 hybrid FFT butterfly:
The first four stages in the 512-point radix 4/radix 2 mixed FFT butterfly operation are 128 radix 4FFT butterfly operations, the last stage is 256 radix 2FFT butterfly operations, the calculation process of the first four stages of radix 4FFT butterfly operations is identical to the calculation process of the pure radix 4FFT butterfly operation, and the calculation process of the last stage of radix 2FFT butterfly operation is identical to the calculation process of the pure radix 2FFT butterfly operation. Only the data is buffered differently in the registers corresponding to the transition radix 4 stage of the radix-4 FFT butterfly and the radix-2 FFT butterfly.
The output numbers of the 1 st butterfly operation in the group are 0, 1, 2 and 3; the output numbers of the 2 nd butterfly operation in the group are 4, 5, 6 and 7; the 3 rd butterfly operation in the group outputs numbers of 8, 9, 10 and 11; the 4 th butterfly operation in the group outputs numbers 12, 13, 14 and 15. According to the sequence shown in fig. 14, the data are written into 16 registers for temporary storage, and then written into four sub-memories in parallel from left to right according to columns, so that the pipelined read-write of the 512-point base 4/base 2 hybrid FFT butterfly operation is ensured, and the operation efficiency of the memory is improved.
In summary, according to the fast fourier transform butterfly operation in the embodiment of the disclosure, according to the mapping relation between the logical address and the physical address, the in-situ operation of the fast fourier transform butterfly operation can read and write data in parallel, and the conversion from the base 4 level to the base 2 level of temporary registers is realized by designing the target transposition mode of the base 4/base 2 hybrid base, so that the parallel read and write operation of the ASIC hardware in the in-situ operation process of the FFT butterfly operation is realized, the space saving of the FFT butterfly operation on the memory in the in-situ operation process is ensured, and the parallel operation of the ASIC hardware is realized.
In a possible embodiment, as shown in fig. 15, the disclosure provides an integrated circuit that performs operations on all data in all physical addresses corresponding to a memory through a multi-stage fft butterfly operation, where the integrated circuit includes a data readout module 1001 and an execution module 1002, for each stage of fft butterfly operation:
A data readout module 1001 configured to read out initial data in parallel from a physical address group corresponding to a memory, the physical address group including a partial physical address of the memory, by a first order;
the execution module 1002 is configured to perform butterfly operation on the initial data to obtain target data, and write the target data into the physical address group in parallel through a second order, where the physical address group is different when each stage of the fast fourier transform butterfly operation, and the first order and the second order are determined according to the radix of the current stage participating in the fast fourier transform butterfly operation, and the first order is different from the second order.
In each stage of the fft butterfly operation in the embodiment of the present disclosure, data read is performed through a first order and data write is performed through a second order, so that a result of the fft butterfly operation is transposed, thereby switching a physical address group corresponding to each stage of fft butterfly operation. And the reading and writing of the data are parallel, so that the area of a memory participating in butterfly operation is reduced, the time of each stage of fast Fourier transform butterfly operation is shortened, the working time of the memory is shortened, and the power consumption of the memory is reduced.
In a possible implementation manner, the execution module 1002 is configured to determine, by using a logical address addressing manner, a logical address group corresponding to each stage of the fft butterfly operation;
Dividing the logical addresses into a first part of logical addresses and a second part of logical addresses according to the logical address group, the number of points of the fast Fourier transform butterfly operation and the cardinal number of the current stage of the fast Fourier transform butterfly operation, wherein the first part of logical addresses are used for determining data of the fast Fourier transform butterfly operation, and the second part of logical addresses are used for recording the calculation times of the current stage of the fast Fourier transform butterfly operation in the fast Fourier transform butterfly operation process;
And determining a physical address group corresponding to the first part of logical addresses from the physical addresses according to the mapping relation between the logical addresses and the physical addresses.
In a possible implementation manner, the execution module 1002 is configured to group the logical addresses according to the number of points of the fft butterfly operation and the cardinality of the current stage of the fft butterfly operation, to obtain a first target number of address groups;
Determining location information of a logical address group in the first target number of address groups;
And dividing the logical address group in the logical addresses into a first partial logical address according to the position information, and taking the rest address group in the logical addresses as a second partial logical address.
In a possible embodiment, the first order and the second order may be determined by:
Determining a target register address according to the base number of the current stage of the fast Fourier transform butterfly operation, wherein the target register address is a matrix constructed by taking the base number as a dimension;
The address order in the first partial logical address of the current stage is taken as a first order, and the column order in the target register address is taken as a second order.
In a possible implementation, the execution module 1002 is configured to determine the supplemental address of the current stage according to the first partial logical address of the current stage and the first partial logical address of the next stage of the fft butterfly operation;
Determining the arrangement sequence of the target register addresses according to the first partial logic address of the current stage, the first partial logic address of the next stage and the supplementary address of the current stage;
And determining the address length of the target register address according to the high radix of the current stage of the fast Fourier transform butterfly operation.
In a possible implementation, for the case that the current stage of the fft butterfly is a mixed-base transition stage, the execution module 1002 is configured to divide the destination register address into two intervals;
For the same interval, determining target registers of two adjacent rows and one column in the interval, and storing data of the fast Fourier transform butterfly operation according to the Z-shaped sequence;
and storing the data of the fast Fourier transform butterfly operation according to the sequence of the different sections in the target register address from top to bottom according to the different sections.
In a possible implementation, for the case where the current stage of the fft butterfly is a pure basis or the fft butterfly is a mixed basis and the current stage is a non-transitional stage, the execution module 1002 is configured to store the fft butterfly data in the order of the preceding and following target register addresses.
In a possible implementation, the physical address group of the parallel data read and parallel data write of the fast fourier transform butterfly operation of each stage is a high-order physical address group of the physical address.
The specific manner in which the various modules perform the operations in the integrated circuits of the embodiments described above have been described in detail in connection with embodiments of the method and will not be described in detail herein.
In one possible embodiment, the present disclosure provides an electronic device comprising:
A memory having a computer program stored thereon;
and a processor for executing the computer program in the memory to implement the fast fourier transform processing method.
In each stage of the fft butterfly operation in the embodiment of the present disclosure, data read is performed through a first order and data write is performed through a second order, so that a result of the fft butterfly operation is transposed, thereby switching a physical address group corresponding to each stage of fft butterfly operation. And the reading and writing of the data are parallel, so that the area of a memory for parameter butterfly operation is reduced, the time of each stage of fast Fourier transform butterfly operation is shortened, the working time of the memory is shortened, and the power consumption of the memory is reduced.
Fig. 16 is a block diagram of an electronic device 1100, according to an example embodiment. As shown in fig. 16, the electronic device 1100 may include: processor 1101, memory 1102. The electronic device 1100 can also include one or more of a multimedia component 1103, an input/output (I/O) interface 1104, and a communication component 1105.
The processor 1101 is configured to control the overall operation of the electronic device 1100 to perform all or part of the steps in the fast fourier transform processing method described above. The memory 1102 is used to store various types of data to support operation on the electronic device 1100, which may include, for example, instructions for any application or method operating on the electronic device 1100, as well as application-related data, such as contact data, transceived messages, pictures, audio, video, and the like. The Memory 1102 may be implemented by any type or combination of volatile or non-volatile Memory devices, such as static random access Memory (Static Random Access Memory, SRAM for short), electrically erasable programmable Read-Only Memory (ELECTRICALLY ERASABLE PROGRAMMABLE READ-Only Memory, EEPROM for short), erasable programmable Read-Only Memory (Erasable Programmable Read-Only Memory, EPROM for short), programmable Read-Only Memory (Programmable Read-Only Memory, PROM for short), read-Only Memory (ROM for short), magnetic Memory, flash Memory, magnetic disk, or optical disk. The multimedia component 1103 may include a screen and an audio component. Wherein the screen may be, for example, a touch screen, the audio component being for outputting and/or inputting audio signals. For example, the audio component may include a microphone for receiving external audio signals. The received audio signals may be further stored in memory 1102 or transmitted through communications component 1105. The audio assembly further comprises at least one speaker for outputting audio signals. The I/O interface 1104 provides an interface between the processor 1101 and other interface modules, which may be a keyboard, mouse, buttons, etc. These buttons may be virtual buttons or physical buttons. The communication component 1105 is used for wired or wireless communication between the electronic device 1100 and other devices. Wireless Communication, such as Wi-Fi, bluetooth, near Field Communication (NFC) for short, 2G, 3G, 4G, NB-IOT, eMTC, or other 5G, etc., or one or a combination of more of them, is not limited herein. The corresponding communication component 1105 may thus comprise: wi-Fi module, bluetooth module, NFC module, etc.
In an exemplary embodiment, the electronic device 1100 may be implemented by one or more Application-specific integrated circuits (ASICs), digital signal processors (DIGITAL SIGNAL processors, DSPs), digital signal processing devices (DIGITAL SIGNAL Processing Device, DSPDs), programmable logic devices (Programmable Logic Device, PLDs), field programmable gate arrays (Field Programmable GATE ARRAY, FPGAs), controllers, microcontrollers, microprocessors, or other electronic components for performing the above-described processing methods of fast fourier transforms.
In another exemplary embodiment, a computer readable storage medium is also provided, comprising program instructions which, when executed by a processor, implement the steps of the fast fourier transform processing method described above. For example, the computer readable storage medium may be the memory 1102 including program instructions described above, which are executable by the processor 1101 of the electronic device 1100 to perform the processing method of the fast fourier transform described above.
In another exemplary embodiment, a computer program product is also provided, which comprises a computer program executable by a programmable apparatus, the computer program having code portions for performing the above-mentioned processing method of fast fourier transformation when being executed by the programmable apparatus.
The preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings, but the present disclosure is not limited to the specific details of the embodiments described above, and various simple modifications may be made to the technical solutions of the present disclosure within the scope of the technical concept of the present disclosure, and all the simple modifications belong to the protection scope of the present disclosure.
In addition, the specific features described in the above embodiments may be combined in any suitable manner without contradiction. The various possible combinations are not described further in this disclosure in order to avoid unnecessary repetition.
Moreover, any combination between the various embodiments of the present disclosure is possible as long as it does not depart from the spirit of the present disclosure, which should also be construed as the disclosure of the present disclosure.

Claims (7)

1. A method of processing a fast fourier transform, the method comprising:
And operating all data in all physical addresses corresponding to the memory through multistage fast Fourier transform butterfly operation, wherein each stage of fast Fourier transform butterfly operation comprises the following steps:
Reading initial data from a physical address group corresponding to the memory in parallel through a first sequence, wherein the physical address group comprises part of physical addresses of the memory;
Performing butterfly operation on the initial data to obtain target data, and writing the target data into the physical address group in parallel through a second sequence, wherein the physical address group is different when each stage of the fast Fourier transform butterfly operation is performed, the first sequence and the second sequence are determined according to the base number of the current stage participating in the fast Fourier transform butterfly operation, and the first sequence and the second sequence are different;
The set of physical addresses is obtained by:
determining a logical address group corresponding to the fast Fourier transform butterfly operation of each stage in a logical address addressing mode;
dividing the logical address into a first part of logical address and a second part of logical address according to the logical address group, the number of points of the fast Fourier transform butterfly operation and the cardinality of the current stage of the fast Fourier transform butterfly operation, wherein the first part of logical address is used for determining data of the fast Fourier transform butterfly operation, and the second part of logical address is used for recording the calculation times of the fast Fourier transform butterfly operation in the current stage in the fast Fourier transform butterfly operation process;
Determining a physical address group corresponding to the first part of logical addresses from physical addresses according to the mapping relation between the logical addresses and the physical addresses;
The dividing the logical address into a first part of logical address and a second part of logical address according to the logical address group, the number of points of the fast fourier transform butterfly operation and the cardinality of the current stage of the fast fourier transform butterfly operation includes:
grouping the logical addresses according to the number of points of the fast Fourier transform butterfly operation and the cardinality of the current stage of the fast Fourier transform butterfly operation to obtain a first target number of address groups;
Determining location information of the logical address group in the first target number of the address groups;
Dividing the logical address group in the logical addresses into a first partial logical address according to the position information, and taking the rest address group in the logical addresses as a second partial logical address;
the first order and the second order are determined by:
determining a target register address according to the base number of the current stage of the fast Fourier transform butterfly operation, wherein the target register address is a matrix constructed by taking the base number as a dimension;
taking the address taking sequence in the first part of logic addresses of the current stage as the first sequence, and taking the column sequence in the register addresses as the second sequence.
2. The method of claim 1, wherein the addressing of the destination register address comprises:
determining a supplementary address of the current stage according to the first partial logic address of the current stage and the first partial logic address of the next stage of the fast Fourier transform butterfly operation;
determining the arrangement sequence of the target register addresses according to the first partial logic address of the current stage, the first partial logic address of the next stage and the supplementary address of the current stage;
And determining the address length of the target register address according to the high radix of the current stage of the fast Fourier transform butterfly operation.
3. The method of claim 1, wherein, in the case where the current stage of the fft butterfly is a mixed-base transition stage, the data of the fft butterfly is stored in the destination register address in the first order by:
dividing the target register address into two sections;
For the same interval, determining target registers of two adjacent rows and one column in the interval, and storing the data of the fast Fourier transform butterfly operation according to the Z-shaped sequence;
And storing the data of the fast Fourier transform butterfly operation according to the sequence of the different intervals in the target register address from top to bottom aiming at the different intervals.
4. The method of claim 1, wherein, in the case where the current stage of the fft butterfly is pure, or where the fft butterfly is mixed and the current stage is a non-transitional stage, the fft butterfly data is stored in the destination register address by:
and storing the data of the fast Fourier transform butterfly operation according to the sequence of the preceding sequence and the following sequence of the register address.
5. The method of claim 1, wherein the set of physical addresses for data parallel reads and data parallel writes of the fast fourier transform butterfly operation of each stage is a set of high order physical addresses of the physical addresses.
6. An integrated circuit, wherein the integrated circuit performs operations on all data in all physical addresses corresponding to a memory through a multi-stage fft butterfly operation, and wherein the integrated circuit includes a data readout module and an execution module, for each stage of fft butterfly operation:
the data reading module is configured to read initial data from a physical address group corresponding to the memory in parallel through a first sequence, wherein the physical address group comprises part of physical addresses of the memory;
The execution module is configured to perform butterfly operation on the initial data to obtain target data, and write the target data into the physical address group in parallel through a second sequence, wherein the physical address group is different when each stage of the fast Fourier transform butterfly operation is performed, the first sequence and the second sequence are determined according to the base number of the current stage participating in the fast Fourier transform butterfly operation, and the first sequence is different from the second sequence;
the execution module is configured to determine a logical address group corresponding to the fast Fourier transform butterfly operation of each stage in a logical address addressing mode;
dividing the logical address into a first part of logical address and a second part of logical address according to the logical address group, the number of points of the fast Fourier transform butterfly operation and the cardinality of the current stage of the fast Fourier transform butterfly operation, wherein the first part of logical address is used for determining data of the fast Fourier transform butterfly operation, and the second part of logical address is used for recording the calculation times of the fast Fourier transform butterfly operation in the current stage in the fast Fourier transform butterfly operation process;
Determining a physical address group corresponding to the first part of logical addresses from physical addresses according to the mapping relation between the logical addresses and the physical addresses;
The execution module is configured to group the logical addresses according to the number of points of the fast Fourier transform butterfly operation and the cardinality of the current stage of the fast Fourier transform butterfly operation to obtain a first target number of address groups;
Determining location information of the logical address group in the first target number of the address groups;
Dividing the logical address group in the logical addresses into a first partial logical address according to the position information, and taking the rest address group in the logical addresses as a second partial logical address;
wherein the first order and the second order are determined by:
determining a target register address according to the base number of the current stage of the fast Fourier transform butterfly operation, wherein the target register address is a matrix constructed by taking the base number as a dimension;
taking the address taking sequence in the first part of logic addresses of the current stage as the first sequence, and taking the column sequence in the register addresses as the second sequence.
7. An electronic device, comprising:
A memory having a computer program stored thereon;
a processor for executing the computer program in the memory to implement the method of any one of claims 1-5.
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