CN103021955B - The formation method for integrated semiconductor device of polysilicon resistance structure and correspondence - Google Patents
The formation method for integrated semiconductor device of polysilicon resistance structure and correspondence Download PDFInfo
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- CN103021955B CN103021955B CN201210564445.3A CN201210564445A CN103021955B CN 103021955 B CN103021955 B CN 103021955B CN 201210564445 A CN201210564445 A CN 201210564445A CN 103021955 B CN103021955 B CN 103021955B
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- 239000000463 material Substances 0.000 claims abstract description 164
- 229910052751 metal Inorganic materials 0.000 claims description 113
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- 229910021332 silicide Inorganic materials 0.000 claims description 105
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 105
- 239000012774 insulation material Substances 0.000 claims description 66
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- 238000004519 manufacturing process Methods 0.000 abstract description 13
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 28
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 239000000377 silicon dioxide Substances 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- 238000002955 isolation Methods 0.000 description 8
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- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
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Abstract
The formation method for integrated semiconductor device of a kind of polysilicon resistance structure and correspondence, described formation method for integrated semiconductor device is formation control gate material layer on first area and second area, and the control gate material layer of described first area and second area is synchronously etched, the control gate of gate-division type flash memory is formed in first area, the second polysilicon resistance is formed at second area, and the first polysilicon resistance is formed at second area while the wordline forming gate-division type flash memory, do not need to increase any extra technique, shorten process cycle, and save the consumption of the raw material of deposit spathic silicon, save production technology cost.
Description
Technical field
The present invention relates to semiconductor technology, particularly the formation method for integrated semiconductor device of a kind of polysilicon resistance structure and correspondence.
Background technology
Along with the characteristic size (CD of semiconductor device, CriticalDimension) become more and more less, the integrated level of semiconductor chip is more and more higher, unit are needs the number of devices of formation and type also get more and more, thus also more and more higher to the requirement of semiconductor technology.How the various different components of reasonable arrangement position and utilize the common ground of each device manufacture to save the focus that semiconductor process step and material become research now.
In semiconductor device manufactures, polysilicon is a kind of electric conducting material be in daily use, and usually may be used for the floating boom, control gate etc. of the gate electrode of making MOS transistor, high value polysilicon resistance, flash memory.
Publication number is that the Chinese patent literature of CN101465161A discloses a kind of gate-division type flash memory, specifically please refer to Fig. 1, comprise: Semiconductor substrate 10, be positioned at two storage bit unit 50 of described Semiconductor substrate 10 spaced surface arrangement, groove between described two storage bit unit 50, be positioned at the sidewall of described groove and the tunnel oxide 70 of lower surface, be positioned at tunnel oxide 70 surface and the polysilicon word line 40 of the full described groove of filling, be positioned at the conductive plunger 20 on described Semiconductor substrate 10 surface, described conductive plunger 20 is positioned at the both sides of described storage bit unit 50.Wherein, described storage bit unit 50 comprises the ground floor silicon oxide layer 51 being positioned at described Semiconductor substrate 10 surface, be positioned at first multi-crystal silicon floating bar 52 on described ground floor silicon oxide layer 51 surface, be positioned at the second layer silicon oxide layer 53 on described first multi-crystal silicon floating bar 52 surface, be positioned at first polysilicon control grid 54 on described second layer silicon oxide layer 53 surface, cover the monox lateral wall 55 of described ground floor silicon oxide layer 51, first multi-crystal silicon floating bar 52, second layer silicon oxide layer 53, first polysilicon control grid 54.
At present, described gate-division type flash memory and polysilicon resistance separate to manufacture, and after namely first forming gate-division type flash memory in appointed area, then forms mask layer on described gate-division type flash memory surface, then form polysilicon resistance in other regions.But the integrated level of described formation process is lower, and processing step is more.
Summary of the invention
The problem that the present invention solves is to provide the formation method for integrated semiconductor device of a kind of polysilicon resistance structure and correspondence, utilizes while forming gate-division type flash memory and forms polysilicon resistance structure, greatly saved process costs, shortened process cycle.
For solving the problem, technical solution of the present invention provides a kind of formation method for integrated semiconductor device, comprise: Semiconductor substrate is provided, described Semiconductor substrate has first area and the second area relative with first area, the semiconductor substrate surface of described first area is formed with the first insulation material layer, described first insulation material layer surface is formed with floating gate material layer, described floating gate material layer surface is formed with the second insulation material layer, the semiconductor substrate surface of described second area is formed with separator, second insulation material layer surface of described first area and the insulation surface of second area are formed with control gate material layer, form the mask layer with opening in described control gate material surface, wherein, the opening being positioned at first area is the first opening, and the opening being positioned at second area is the second opening, form the first side wall at the sidewall of described first opening, form the second side wall at the sidewall of described second opening, the control gate material layer that the control gate material layer, the second insulation material layer, floating gate material layer, the first insulation material layer and the second opening that come out to described first opening come out etches, until expose the Semiconductor substrate of first area and the separator of second area, the first oxide layer is formed in described first opening, the second open bottom and sidewall surfaces, and in described first opening, the second opening, fill full polysilicon, polysilicon wherein in the first opening forms wordline, and the polysilicon in the second opening forms the first polysilicon resistance, the part control gate material layer removed described mask layer and covered by mask layer, be positioned at the control gate material layer formation control grid below the first side wall, the control gate material layer be positioned at below the second side wall forms the second polysilicon resistance, and exposes two end surfaces of described control gate, polysilicon resistance, etch described the second insulation material layer, floating gate material layer, the first insulation material layer that are covered by mask layer, until expose the Semiconductor substrate of first area, form gate-division type flash memory in first area, two end surfaces exposed at described first polysilicon resistance and the second polysilicon resistance form metal silicide and conductive plunger, form metal interconnecting layer on described conductive plunger surface, and by metal silicide, conductive plunger and metal interconnecting layer the first polysilicon resistance is connected with the second polysilicon resistance and forms polysilicon resistance structure.
Optionally, also comprise: after forming gate-division type flash memory, the 3rd insulating barrier is formed on described first polysilicon resistance surface, described 3rd insulating layer exposing goes out two end surfaces of the first polysilicon resistance, form metal silicide at described the first polysilicon resistance two end surfaces of exposing and wordline surface, form conductive plunger on described metal silicide surface.
Optionally, also comprise: after forming gate-division type flash memory, form the 4th insulating barrier on the semiconductor substrate, the second polysilicon material layer is formed at described 4th surface of insulating layer, second polysilicon material layer of described first area and part second area, the 4th insulating barrier are etched, expose the two ends of described first polysilicon resistance and the two ends of the second polysilicon resistance, form metal silicide at described the first polysilicon resistance two end surfaces of exposing and the second polysilicon resistance two end surfaces, form conductive plunger on described metal silicide surface.
Optionally, described Semiconductor substrate also comprises the 3rd region, described 3rd region is for the formation of MOS transistor, and the gate dielectric layer in the grid structure of described 4th insulating barrier, the second polysilicon material layer and the 3rd region MOS transistor, polygate electrodes are formed simultaneously.
Optionally, while described the first polysilicon resistance surface exposed forms metal silicide and conductive plunger, metal silicide and conductive plunger is formed on the wordline surface of described gate-division type flash memory.
Optionally, the length of described second polysilicon resistance is greater than the length of the second side wall, described second side wall only covers the surface, centre position of the second polysilicon resistance, the length of described control gate is greater than the length of the first side wall, the surface, centre position of a described first side wall Coverage Control grid, form metal silicide at two end surfaces of described control gate and two end surfaces of described second polysilicon resistance, form conductive plunger on described metal silicide surface.
Optionally, while the surface at described the second polysilicon resistance two ends exposed forms metal silicide and conductive plunger, form metal silicide and conductive plunger on the control gate surface of the described gate-division type flash memory exposed.
Optionally, the formation process of described metal silicide is self-aligned metal silicate formation process.
Optionally, the material of described control gate material layer is polysilicon, and doped with N-type impurity ion or p type impurity ion in described control gate material layer.
Optionally, in described first polysilicon resistance doped with N-type impurity ion or p type impurity ion.
Optionally, by controlling the width of the second opening and the second side wall, the resistance of the first polysilicon resistance and the second polysilicon resistance is controlled.、
The embodiment of the present invention additionally provides a kind of polysilicon resistance structure, comprise: Semiconductor substrate, be positioned at the separator of described semiconductor substrate surface, be positioned at even number second polysilicon resistance of described insulation surface, be positioned at the side wall on described second surface, polysilicon resistance centre position, the first polysilicon resistance in opening between every two adjacent side walls, be positioned at the metal silicide of the second polysilicon resistance two end surfaces and the first polysilicon resistance two end surfaces do not covered by side wall, be positioned at the conductive plunger on described metal silicide surface, described first polysilicon resistance is connected by the metal interconnecting layer be connected with described conductive plunger with the second polysilicon resistance.
Optionally, the first adjacent polysilicon resistance is connected by conductive plunger, metal interconnecting layer series connection, the second adjacent polysilicon resistance is connected by conductive plunger, metal interconnecting layer series connection, and one of them first polysilicon resistance described is connected by metal silicide, conductive plunger, metal interconnecting layer series connection with one of them second polysilicon resistance.
Optionally, the first adjacent polysilicon resistance, the second polysilicon resistance are connected by metal silicide, conductive plunger, metal interconnecting layer series connection.
Optionally, connect with other first polysilicon resistances, the second polysilicon resistance or both Parallel connection structures be connected by metal silicide, conductive plunger, metal interconnecting layer after the first adjacent polysilicon resistance, the second polysilicon resistance parallel connection.
Compared with prior art, the present invention has the following advantages:
The embodiment of the present invention is formation control gate material layer on first area and second area, and the control gate material layer of described first area and second area is synchronously etched, the control gate of gate-division type flash memory is formed in first area, the second polysilicon resistance is formed at second area, and the first polysilicon resistance is formed at second area while the wordline forming gate-division type flash memory, do not need to increase any extra technique, shorten process cycle, and save the consumption of the raw material of deposit spathic silicon, save production technology cost.
Further, the length of the second polysilicon resistance of the embodiment of the present invention is greater than the length of the second side wall, described second side wall only covers the surface, centre position of the second polysilicon resistance, utilize the second side wall being formed in the second polysilicon resistance surface as silicide barrier layer, and described second side wall is formed with the first side wall forming gate-division type flash memory simultaneously, do not need additionally to form self-aligned silicide barrier layer again, save production technology cost, shorten process cycle.
Further, the embodiment of the present invention forms the 4th insulating barrier on described first polysilicon resistance surface, the second polysilicon material layer is formed at described 4th surface of insulating layer, described second polysilicon material layer and the 4th insulating barrier are as self aligned silicide barrier layer, and described 4th insulating barrier, the second polysilicon material layer are formed with the gate dielectric layer formed in the grid structure of MOS transistor, polygate electrodes simultaneously, do not need additionally to form silicide barrier layer again, save production technology cost, shorten process cycle.
Accompanying drawing explanation
Fig. 1 is the structural representation of the gate-division type flash memory of prior art;
Fig. 2 is the schematic flow sheet of the formation method for integrated semiconductor device of the embodiment of the present invention;
The structural representation of the semiconductor integrated device forming process of Fig. 3 to Figure 19 embodiment of the present invention.
Embodiment
When utilizing existing technique to form gate-division type flash memory and polysilicon resistance, described gate-division type flash memory and polysilicon resistance separate to manufacture, namely after first forming gate-division type flash memory in appointed area, then form mask layer on described gate-division type flash memory surface, then form polysilicon resistance in other regions.But need deposit multilayer polysilicon layer to be used for formation control grid, floating boom or wordline owing to making described gate-division type flash memory, after the described mul-tiple layers of polysilicon layer in other regions being etched away after forming gate-division type flash memory, form another layer of polysilicon layer again to make polysilicon resistance, cause the waste of material and the increase of processing step.
Therefore, the formation method for integrated semiconductor device embodiments providing a kind of polysilicon resistance structure and polysilicon resistance structure and gate-division type flash memory are formed simultaneously, polysilicon resistance structure is formed while forming the control gate in gate-division type flash memory, extra technique need not be increased, save etching, deposition step, and save the consumption of the raw material of deposit spathic silicon, reduce process costs.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here to implement with multiple, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention.Therefore the present invention is not by the restriction of following public concrete enforcement.
The embodiment of the present invention provide firstly a kind of formation method for integrated semiconductor device, and concrete schematic flow sheet please refer to Fig. 2, comprising:
Step S101, Semiconductor substrate is provided, described Semiconductor substrate has first area and the second area relative with first area, the semiconductor substrate surface of described first area is formed with the first insulation material layer, described first insulation material layer surface is formed with floating gate material layer, described floating gate material layer surface is formed with the second insulation material layer, the semiconductor substrate surface of described second area is formed with separator, and the second insulation material layer surface of described first area and the insulation surface of second area are formed with control gate material layer;
Step S102, form the mask layer with opening in described control gate material surface, wherein, the opening being positioned at first area is the first opening, and the opening being positioned at second area is the second opening;
Step S103, forms the first side wall at the sidewall of described first opening, forms the second side wall at the sidewall of described second opening;
Step S104, the control gate material layer that the control gate material layer, the second insulation material layer, floating gate material layer, the first insulation material layer and the second opening that come out to described first opening come out etches, until expose the Semiconductor substrate of first area and the separator of second area;
Step S105, the first oxide layer is formed in described first opening, the second open bottom and sidewall surfaces, and in described first opening, the second opening, fill full polysilicon, the polysilicon wherein in the first opening forms wordline, and the polysilicon in the second opening forms the first polysilicon resistance;
Step S106, the part control gate material layer removed described mask layer and covered by mask layer, be positioned at the control gate material layer formation control grid below the first side wall, the control gate material layer be positioned at below the second side wall forms the second polysilicon resistance, and exposes two end surfaces of described control gate, polysilicon resistance;
Step S107, etches described the second insulation material layer, floating gate material layer, the first insulation material layer that are covered by mask layer, until expose the Semiconductor substrate of first area, forms gate-division type flash memory in first area;
Step S108, two end surfaces exposed at described first polysilicon resistance and the second polysilicon resistance form metal silicide and conductive plunger, form metal interconnecting layer on described conductive plunger surface, and by metal silicide, conductive plunger and metal interconnecting layer the first polysilicon resistance is connected with the second polysilicon resistance and forms polysilicon resistance structure.
Concrete, please refer to Fig. 3 to Figure 19, the structural representation of the semiconductor integrated device forming process of the embodiment of the present invention.
Please refer to Fig. 3, provide Semiconductor substrate 100, described Semiconductor substrate 100 has first area I and the second area II relative with first area I.
Described Semiconductor substrate 100 can be silicon substrate, germanium substrate, germanium silicon substrate, gallium arsenide substrate, gallium nitride substrate or silicon-on-insulator substrate one wherein.Those skilled in the art can select the type of described Semiconductor substrate 100 according to semiconductor integrated device to be formed, therefore the type of described Semiconductor substrate should not limit the scope of the invention.
Described Semiconductor substrate 100 has first area I and the second area II relative with first area I.Described first area I is adjacent with second area II or be separated by.On described first area I, form gate-division type flash memory in subsequent technique, second area II is formed polysilicon resistance structure.In the fabrication of semiconductor device of reality, described Semiconductor substrate 100 has one or more first area I and second area II, in the present embodiment, do exemplary illustrated with an a first area I and second area II adjacent with described first area I, the quantity of described first area and second area and position should too not limit the scope of the invention.
In the present embodiment, owing to often having some MOS transistor in memory circuitry as control transistor, described Semiconductor substrate 100 also comprises the 3rd region (not shown), and described 3rd region is for the formation of MOS transistor.
Please refer to Fig. 4, the first insulation material layer 111 is formed on Semiconductor substrate 100 surface of described first area I, floating gate material layer 112 is formed on described first insulation material layer 111 surface, the second insulation material layer 113 is formed on described floating gate material layer 112 surface, separator 200 is formed, in second insulation material layer 113 surface of described first area I and the surperficial formation control gate material layer 114 of separator 200 of second area II on Semiconductor substrate 100 surface of described second area II.
In the present embodiment, described separator 200 be shallow trench isolation from (STI) structure, in other embodiments, described separator can also for the silicon oxide layer utilizing selective oxidation (LOCOS) technique of silicon to be formed.Polysilicon resistance structure is follow-up is formed at described separator 200 surface, makes described polysilicon resistance structure and other device electric isolation such as gate-division type flash memory, MOS transistor.
In the present embodiment, the material of described first insulation material layer 111 and the second insulation material layer 113 is silica, and the technique forming described first insulation material layer 111 and the second insulation material layer 113 is thermal oxidation technology or chemical vapor deposition method.The material of described floating gate material layer 112 is polysilicon, silicon nitride or metal, described floating gate material layer 112 in subsequent technique for the formation of floating boom.The material of described control gate material layer 114 is polysilicon, the control gate material layer 114 of first area I in subsequent technique for the formation of control gate, the control gate material layer 114 of second area II for the formation of the second polysilicon resistance, can control the resistance of the final polysilicon resistance formed in subsequent technique by the thickness and doping content controlling described control gate material layer 114.In the present embodiment, the material of described floating gate material layer 112 and control gate material layer 114 is polysilicon, form described floating gate material layer 112 and control gate material layer 114 is chemical vapor deposition method, and the process situ of formation control gate material layer 114 is doped with the foreign ion of N-type or P type.In other embodiments, also ion implantation technology foreign ion doped with N-type or P type in control gate material layer can be utilized after described control gate material layer being formed.
In the present embodiment, first at first area I and second area II surface formation first insulation material layer 111 of described Semiconductor substrate 100, floating gate material layer 112 is formed on described first insulation material layer 111 surface, the second insulation material layer 113 is formed on described floating gate material layer 112 surface, grinding barrier layer (not shown) is formed on described second insulation material layer 113 surface, to the grinding barrier layer of described second area, second insulation material layer, floating gate material layer, the Semiconductor substrate of the first insulation material layer and partial depth is carried out etching and is formed groove, and insulating material is full of in described groove, such as silica, unnecessary insulating material is removed by chemical mechanical milling tech, until stop at grinding barrier layer surface, insulating material in described groove forms fleet plough groove isolation structure, then described grinding barrier layer is removed.Then in second insulation material layer 113 of described first area I and the surface of shallow trench isolation structure formation control gate material layer 114 of second area II.The apparent height of the fleet plough groove isolation structure formed owing to utilizing cmp usually can lower than the apparent height on grinding barrier layer, make the apparent height of the apparent height of the fleet plough groove isolation structure utilizing described technique to be formed and the second mask layer similar, the similar elevation of the control gate material layer of first area and the control gate material layer of second area can be made, make the similar elevation of the mask layer of the first area of follow-up formation and the mask layer of second area, be conducive to follow-up control polysilicon being carried out to when cmp forms wordline, grinding is stopped, avoid grinding occurring or also having polysilicon residue on mask layer surface.
In other embodiments, also first separator can be formed, the first insulation material layer is formed again in described Semiconductor substrate first area and insulation surface, floating gate material layer is formed on described first insulation material layer surface, the second insulation material layer is formed on described floating gate material layer surface, and the first insulation material layer of described insulation surface is removed by etching technics, floating gate material layer, second insulation material layer, only form the first insulation material layer at the semiconductor substrate surface of described first area, floating gate material layer, second insulation material layer, and in the second insulation material layer surface of described first area and the insulation surface formation control gate material layer of second area.
In other embodiments, also only the first insulation material layer can be formed at the semiconductor substrate surface of described first area, floating gate material layer, floating gate material layer surface in described first area and the insulation surface of second area form the second insulation material layer and are positioned at the control gate material layer on the second insulation material layer surface, because the material of the second insulation material layer and separator is all insulating material, both effects are identical, between described separator and control gate material layer, multiform becomes one deck second insulation material layer can not impact final the second polysilicon resistance formed.
After forming described control gate material layer 114, described control gate material layer 114 is etched, form the control gate material layer 114 of block rectangle, the control gate material layer 114 of each rectangle corresponds to gate-division type flash memory unit or the polysilicon resistance construction unit of one, and the width of wherein said rectangle has defined the follow-up length of formation second polysilicon resistance and the length of control gate.In the present embodiment, the length of described second polysilicon resistance is equal with the length of control gate.In other embodiments, the control gate material layer of the rectangle of described first area is not identical with the size of the control gate material layer of the rectangle of second area, makes the length of the length of final the second polysilicon resistance formed and control gate unequal.
In other embodiments, also can first not etch control gate material layer, after follow-up removal mask layer, patterned photoresist layer is utilized to etch control gate material layer, the second insulation material layer, floating gate material layer, the first insulation material layer for mask, define the graphics shape come out in control gate, the length of the second polysilicon resistance and control gate, the second polysilicon resistance two ends, make finally to form two control gates in described wordline both sides, form two the second polysilicon resistances in described dummy word line both sides.
In other embodiments, also the control gate material layer figure of the class rectangle with fracture can first be formed, described fracture corresponds to the first opening of follow-up formation and the position at the second opening two ends, make with described first opening and the second opening as after mask etches control gate material layer figure, the control gate material layer being positioned at the first opening and the second opening both sides is separated, and do not need to utilize photoetching process to be positioned at the control gate material layer of the first opening and the second opening both sides separately, finally can form two control gates in described wordline both sides, two the second polysilicon resistances are formed in described first polysilicon resistance both sides.
Please refer to Fig. 5, form the mask layer 120 with opening on described control gate material layer 114 surface, wherein, the opening being positioned at first area I is the first opening 121, and the opening being positioned at second area II is the second opening 122.
The material of described mask layer 120 is silica, silicon nitride or both laminated construction.In the present embodiment, the material of described mask layer 120 is silicon nitride.The technique forming described first opening 121 and the second opening 122 is dry etch process or wet-etching technology.In the present embodiment, the technique forming described first opening 121 and the second opening 122 is dry etch process, and described first opening 121 exposes control gate material layer 114 surface of first area I, described second opening 122 exposes control gate material layer 114 surface of second area II.Described first opening in subsequent technique for the formation of gate-division type flash memory, described second opening in subsequent technique for the formation of the first polysilicon resistance and the second polysilicon resistance.The size of described first opening and the second opening can be equal, also can be unequal.Width due to the first polysilicon resistance of follow-up formation depends on the width of the second opening and the width of follow-up formation second side wall, the width of the second polysilicon resistance of follow-up formation depends on the width of the second side wall, the length of the first polysilicon resistance depends on the length of the second opening, the height of the first polysilicon resistance and the height of gate-division type flash memory depend on the thickness of described mask layer, and due to the resistance of polysilicon resistance and the length positive correlation of polysilicon resistance, be inversely proportional to the area of section of polysilicon resistance, namely with the high negative correlation of the first polysilicon resistance, with the first polysilicon resistance, the width negative correlation of the second polysilicon resistance, by controlling the thickness of described mask layer, the width of the second opening, the width of length and follow-up formation second side wall, final the first polysilicon resistance formed can be controlled, the size of the second polysilicon resistance.
Please refer to Fig. 6, is the vertical view of second area II in Fig. 5, and in Fig. 5, the structure of second area is the cross-sectional view of Fig. 6 along AA ' direction.In the present embodiment, the length S2 of described second opening 122 is less than the width S 1 of the rectangle control gate material layer 114 of second area, the length of described first opening is less than the width of the rectangle control gate material layer of first area, the length of final the first side wall formed is made to be less than the length of control gate, the length of the second side wall of final formation is less than the length of the second polysilicon resistance, and described first opening 121, the position of the second opening 122 is positioned at the centre position of rectangle control gate material layer, the control gate of final formation, the two ends of the second polysilicon resistance are not by the first side wall, second side wall covers, the control gate exposed, two end surfaces of the second polysilicon resistance are for the formation of metal silicide and conductive plunger, make control gate, second polysilicon resistance is connected with metal interconnecting layer respectively.
Be the plan structure schematic diagram of the second area of Fig. 7 please also refer to Fig. 7 and Fig. 8, Fig. 8, form the first side wall 131 at the sidewall of described first opening 121, form the second side wall 132 at the sidewall of described second opening 122.
Described first side wall 131, second side wall 132 is silicon oxide layer, silicon nitride layer or both laminated construction, and the technique forming side wall is the known technology of those skilled in the art, and therefore not to repeat here.In the present embodiment, described first side wall 131 and the second side wall 132 adopt same formation process to be formed.In other embodiments, described first side wall and the second side wall also can separately be formed.The thickness of described first side wall also can not be identical with the thickness of the second side wall.Thickness due to the second side wall corresponds to the width of the first polysilicon resistance, the second polysilicon resistance, and namely the thickness therefore by controlling described second side wall can control the width of the first polysilicon resistance, the second polysilicon resistance.
Please refer to Fig. 9, the control gate material layer 114 that control gate material layer 114, second insulation material layer 113, floating gate material layer 112, first insulation material layer 111 and the second opening 122 that come out to described first opening 121 come out etches, until expose the Semiconductor substrate 100 of first area I and the separator 200 of second area II.
In the present embodiment, described etching technics specifically comprises: with described first side wall 131, second side wall 132 and mask layer 120 for mask, described control gate material layer 114 is etched, until expose the second insulation material layer 113 of first area and the separator 200 of second area, the sidewall of the first opening 121 after described etching and the second opening 122 forms the 3rd side wall 133; With described 3rd side wall 133 for mask, to the second insulation material layer 113, floating gate material layer 112, the first insulation material layer 111 continuation etching of described first area, until expose Semiconductor substrate 100 surface of described first area.
In other embodiments, because different gate-division type flash memory corresponds to different floating gate structure, control gate structure, namely different etching technics is corresponded to.Therefore the described lithographic method to floating gate material layer, control gate material layer can be implemented with multiple this alternate manner described that is different from, and those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention.
In the present embodiment, when the second insulation material layer 113, floating gate material layer 112, the first insulation material layer 111 that etching first opening 121 comes out, also etch the separator 200 that the second opening 122 comes out simultaneously, the separator 200 of segment thickness is etched.But because the second insulation material layer 113, first insulation material layer 111 is often very thin, and the etching gas etching floating gate material layer 112 often has higher etching selection ratio to silica, be not easy to etch away separator 200, make the thickness of the separator etched away very little.
Please refer to Figure 10, please refer to Fig. 9 at described first opening 121(), the second opening 122(please refer to Fig. 9) bottom and sidewall surfaces form the first oxide layer 140, and in described first opening 121, second opening 121, fill full polysilicon, the polysilicon that polysilicon wherein in the first opening 121 is formed in wordline 141, second opening 121 forms the first polysilicon resistance 142.
The technique forming described first oxide layer 140, wordline 141 and the first polysilicon resistance 142 specifically comprises: in described first opening 121, second opening 122 sidewall and lower surface, described mask layer 120 surface forms the first silica material layer (not shown), form the first polysilicon material layer (not shown) on described first silica material layer surface, and described first polysilicon material layer fills completely described first opening 121, second opening 122 completely, to first polysilicon material layer on described mask layer 120 surface, first silica material layer carries out cmp, until first polysilicon material layer on mask layer 120 surface of described first area and mask layer 120 surface of second area, first silica material layer is completely removed, expose described mask layer 120, make described first opening, full polysilicon is filled in second opening, wherein, the first polysilicon material layer 140 in first opening 121 forms tunnel oxide, polysilicon in first opening 121 forms wordline 141, polysilicon in second opening 122 forms the first polysilicon resistance 142.
In the present embodiment, described first polysilicon material layer situ is doped with N-type impurity ion or p type impurity ion, in other embodiments, after the described wordline of formation and the first polysilicon resistance, ion implantation is carried out to described wordline and the first polysilicon resistance, makes in the wordline of described formation and the first polysilicon resistance doped with N-type impurity ion or p type impurity ion.By controlling the concentration of described Doped ions, the resistance of the first polysilicon resistance can be controlled.
In the present embodiment, the first polysilicon resistance is defined while formation wordline, do not need additionally to form another layer of polysilicon layer again for the formation of the first polysilicon resistance, save the consumption of the raw material of deposit spathic silicon, and described first polysilicon resistance is formed self-aligned in described second opening, follow-up needs carries out chemical wet etching formation polysilicon resistance to polysilicon layer, saves processing step, improves process integration.
Please refer to Figure 11, remove described mask layer 120(and please refer to Figure 10) and be please refer to Figure 10 by the control gate material layer 114(that mask layer 120 covers), be positioned at the control gate material layer formation control grid 115 below the first side wall 131, the control gate material layer be positioned at below the second side wall 132 forms the second polysilicon resistance 116.
The technique removing described mask layer 120 is dry etch process or wet-etching technology.In the present embodiment, hot phosphoric acid is utilized to carry out wet etching to described mask layer 120.
After removing described mask layer 120, form patterned photoresist layer on the semiconductor substrate, described patterned photoresist layer covers the control gate material layer of wordline, the first polysilicon resistance, the first side wall and the second side wall and subregion.With described patterned photoresist layer for mask, originally the control gate material layer be positioned at below mask layer 120 is etched, until expose the second insulation material layer 113 of first area and the separator 200 of second area, the control gate material layer being positioned at wordline 141 both sides is separated, form two control gates 115, the control gate material layer being positioned at the first polysilicon resistance 142 both sides is separated, forms two the second polysilicon resistances 116.
In the present embodiment, the second polysilicon resistance is defined while formation control grid, do not need additionally to form another layer of polysilicon layer again for the formation of the second polysilicon resistance, save the consumption of the raw material of deposit spathic silicon, and described second polysilicon resistance utilizes, and the second side wall is self aligned to be etched, follow-uply do not need that chemical wet etching is carried out to polysilicon layer and form the second polysilicon resistance, save processing step, improve process integration.
Please refer to Figure 12, for the vertical view of second area in Figure 11, and in Figure 11, the structure of second area is the cross-sectional view of Figure 12 along AA ' direction, wherein, succinct in order to accompanying drawing, the first oxide layer 140 in described Figure 12 in not shown Figure 11 and the 3rd side wall 133.The length of the second polysilicon resistance 116 that described etching is formed is greater than the length of the second side wall 132, and the second side wall 132 covers the centre position of the second polysilicon resistance 116, the two ends of described second polysilicon resistance 116 not cover by the second side wall 132, make follow-up two end surfaces at described second polysilicon resistance 116 can form metal silicide and conductive plunger.
Please refer to Figure 13, after etching removes described control gate material layer (please refer to Figure 10), continue etching and originally be please refer to Figure 10 by mask layer 120() the second insulation material layer 113, floating gate material layer 112, first insulation material layer 111 that cover, until expose the Semiconductor substrate 100 of first area, form gate-division type flash memory 150 in first area.Described floating gate material layer forms the floating boom of gate-division type flash memory 150.
After forming described gate-division type flash memory 150, also form the 4th side wall (sign) in the sidewall surfaces of described gate-division type flash memory 150 sidewall and polysilicon resistance, make the second polysilicon resistance 116 under the floating boom in gate-division type flash memory 150, control gate, the second side wall and extraneous electric isolution, and to prevent from ion implantation in follow-up ion doping technique, in floating boom, control gate, the second polysilicon resistance, affecting the electric property of device.
Please refer to Figure 14, form the 4th insulating barrier 151 at described wordline 141, first polysilicon resistance 142 and Semiconductor substrate 100 surface, form the second polysilicon material layer 152 on described 4th insulating barrier 151 surface and the 4th side wall surface.
In the present embodiment, the gate dielectric layer in the grid structure of the MOS transistor in described 4th insulating barrier 151, second polysilicon material layer 152 and the 3rd region, polygate electrodes are formed simultaneously.Owing to usually there is MOS transistor in described memory circuitry, therefore utilize the gate dielectric layer, polygate electrodes formation the 4th insulating barrier 151, second polysilicon material layer 152 that form described grid structure, improve the integrated level of technique.In the present embodiment, the silicon oxide layer of described 4th insulating barrier 151 for utilizing thermal oxidation technology to be formed, the polysilicon layer of described second polysilicon material layer 152 for utilizing chemical vapor deposition method to be formed.
Please also refer to Figure 15 and Figure 16, Figure 15 is the cross-sectional view of the semiconductor integrated device forming process of the embodiment of the present invention, Figure 16 is the vertical view of the polysilicon resistance structure of second area in Figure 15, and the polysilicon resistance structure in Figure 15 is the cross-sectional view of Figure 12 along AA ' direction.Second polysilicon material layer 152 of first area I and part second area II and the 4th insulating barrier 151 are etched, form the 3rd opening 153, described 3rd opening 153 exposes the part surface at the first polysilicon resistance 142 two ends, and described second polysilicon material layer 152 exposes the part surface at the second polysilicon resistance 116 two ends.The 5th side wall 135 is formed at described 3rd opening 153 sidewall.Semiconductor substrate 100 surface in wordline 141 surface exposed described, control gate 115 surface, source region to be formed, the first polysilicon resistance 142 surface, the second polysilicon resistance 116 surface and the second polysilicon material layer 152 surface form metal silicide 160.
In the present embodiment, described metal silicide 160 is nickle silicide, titanium silicide, tantalum silicide, tungsten silicide, cobalt silicide etc., and the technique forming described metal silicide 160 is self-aligning metal silicide technology.Because self-aligning metal silicide technology is the known technology of those skilled in the art, be not described further at this.
The manufacture process forming polysilicon resistance due to existing technique first forms one deck polysilicon material layer; after etching formation polysilicon resistance is carried out to polysilicon material layer; silicide stop layer (salicideblocklayer is formed at described polysilicon resistance part surface; SAB); utilize described silicide stop layer to protect polysilicon resistance surface, make the polysilicon resistance surface be capped can not form less desirable silicide.But the introducing of silicide stop layer increases the complexity of technique, and increases manufacturing cost.
In the present embodiment, described 4th insulating barrier 151, second polysilicon material layer 152 is formed in the silicide barrier layer of described first polysilicon resistance surface as the first polysilicon resistance, described the second side wall 132 being formed in the surface in described second polysilicon resistance centre position is as the second polysilicon resistance silicide barrier layer, do not need additionally to form silicide barrier layer (SAB), make the first polysilicon resistance exposed described in being only formed in during follow-up formation self-aligned metal silicate, the surface at the second polysilicon resistance two ends, thus can on metal silicide surface by forming conductive plunger by described first polysilicon resistance, second polysilicon resistance is connected to each other.
Technique due to described formation metal silicide is self-aligning metal silicide technology, all metal silicide can be formed at the described silicon face exposed, therefore in the present embodiment, the 5th side wall 135 is formed at the sidewall of described 3rd opening 153, because the material of described 5th side wall 135 is silica or silicon nitride, described 5th side wall 135 surface can not form metal silicide, makes the metal silicide on the first polysilicon resistance 142 surface exposed and the metal silicide electric isolation on the second polysilicon material layer 152 surface.
Because existing gate oxide is very thin, if only utilize described gate oxide as silicide barrier layer, be easy to be destroyed in the process forming metal silicide, effectively can not play the effect of silicide barrier layer, therefore in the present embodiment, utilize the gate dielectric layer and polygate electrodes that form grid structure as silicide barrier layer, thus ensure the smooth formation of self-aligned metal silicate.And due to the described metal silicide on the first polysilicon resistance 142, second polysilicon resistance 116 surface and the metal silicide electric isolation on the second polysilicon material layer 152 surface, follow-up needs carries out etching removal to described remaining second polysilicon material layer 152, saves etching technics.
In other embodiments, second polysilicon material layer of first area and part second area and the 4th insulating barrier are etched, only retain the second polysilicon material layer near polysilicon resistance structure near zone, and be formed with the 3rd opening at the part surface at described first polysilicon resistance two ends, be formed with the 4th opening at the part surface at described second polysilicon resistance two ends.
In other embodiments, after described second polysilicon material layer and the 4th insulating barrier are etched, only retain the second polysilicon material layer and the 4th insulating barrier on the surface, centre position of the first polysilicon resistance, described be positioned at the surface, centre position of the first polysilicon resistance the second polysilicon material layer and the 4th insulating barrier as the silicide barrier layer of the first polysilicon resistance, second side wall is as the silicide barrier layer of the second polysilicon resistance, thus at described first polysilicon resistance, the surface that second polysilicon resistance two ends expose is formed self-aligned metal silicide.
In other embodiments, the 3rd insulating barrier can also be formed on described first polysilicon resistance surface, the two ends of described 3rd insulating barrier expose the first polysilicon resistance surface, described 3rd insulating barrier, as silicide barrier layer, makes follow-up the first polysilicon resistance surface exposed at the two ends of described 3rd insulating barrier form self-aligned metal silicate and conductive plunger.
After forming described metal silicide, the follow-up interlayer dielectric layer (not shown) forming covering gate-division type flash memory and polysilicon resistance structure at described semiconductor substrate surface, and on the metal silicide surface of described control gate 115, the metal silicide of wordline 141, the metal silicide surface of the first polysilicon resistance 142, conductive plunger is formed in the interlayer dielectric layer on the metal silicide surface of the second polysilicon resistance 116, and utilize the metal interconnecting layer on interlayer dielectric layer surface to be connected with the second polysilicon resistance 116 by described first polysilicon resistance 142 by conductive plunger to form polysilicon resistance structure.
In the present embodiment, metal silicide, the conductive plunger on the metal silicide on the control gate surface of described gate-division type flash memory, conductive plunger and the second polysilicon resistance surface are formed simultaneously, and metal silicide, the conductive plunger on the metal silicide on the wordline surface of described gate-division type flash memory, conductive plunger and the first polysilicon resistance surface are formed simultaneously.In other embodiments, the metal silicide on the metal silicide on the control gate of described gate-division type flash memory, wordline surface, conductive plunger and the first polysilicon resistance, the second polysilicon resistance surface, conductive plunger also can separate and formed.
In the present embodiment, please refer to Figure 17, the first adjacent polysilicon resistance 116 is by metal silicide 160, conductive plunger 161, metal interconnecting layer 162 series connection is connected, the second adjacent polysilicon resistance 142 is by metal silicide 160, conductive plunger 161, metal interconnecting layer 162 series connection is connected, and one of them first polysilicon resistance 142 described and one of them the second polysilicon resistance 116 are by metal silicide 160, conductive plunger 161, metal interconnecting layer 162 series connection is connected, all first polysilicon resistances 142 in a polysilicon resistance structure are connected with the second polysilicon resistance 116 series connection, thus form the larger polysilicon resistance structure of a resistance.And by controlling the number of the first polysilicon resistance and second polysilicon resistance of connecting, the resistance of the final polysilicon resistance structure produced can be controlled very easily.
In other embodiments, please refer to Figure 18, the first adjacent polysilicon resistance 142, second polysilicon resistance 116 can also be connected by metal silicide 160, conductive plunger 161, metal interconnecting layer 162 series connection, thus form the larger polysilicon resistance structure of a resistance.
In other embodiments, please refer to Figure 19, can also connect with other the first polysilicon resistance 142, second polysilicon resistances 116 or both Parallel connection structures after the first adjacent polysilicon resistance 142, second polysilicon resistance 116 parallel connection be connected by metal silicide 160, conductive plunger 161, metal interconnecting layer 162, thus form the larger polysilicon resistance structure of a resistance.
The embodiment of the present invention additionally provides a kind of polysilicon resistance structure, please also refer to Figure 15 and Figure 17, comprise: Semiconductor substrate 100, be positioned at the separator 200 on described Semiconductor substrate 100 surface, be positioned at even number second polysilicon resistance 116 on described separator 200 surface, be positioned at second side wall 132 on described second surface, polysilicon resistance 116 centre position, the first polysilicon resistance 142 in opening between every two adjacent second side walls 132, be positioned at the metal silicide 160 of the second polysilicon resistance 116 liang of end surfaces and the first polysilicon resistance 116 liang of end surfaces do not covered by the second side wall 132, be positioned at the conductive plunger 161 on described metal silicide 160 surface, described first polysilicon resistance 142 and the second polysilicon resistance 116 are connected by the metal interconnecting layer 162 be connected with described conductive plunger 161 and form polysilicon resistance structure.
In the present embodiment, the first adjacent polysilicon resistance 116 is by metal silicide 160, conductive plunger 161, metal interconnecting layer 162 series connection is connected, the second adjacent polysilicon resistance 142 is by metal silicide 160, conductive plunger 161, metal interconnecting layer 162 series connection is connected, and one of them first polysilicon resistance 142 described and one of them the second polysilicon resistance 116 are by metal silicide 160, conductive plunger 161, metal interconnecting layer 162 series connection is connected, all first polysilicon resistances 142 in a polysilicon resistance structure are connected with the second polysilicon resistance 116 series connection, thus form the larger polysilicon resistance structure of a resistance.
In other embodiments, the first adjacent polysilicon resistance, the second polysilicon resistance can also be connected by metal silicide, conductive plunger, metal interconnecting layer series connection, thus form the larger polysilicon resistance structure of a resistance.
In other embodiments, can also connect with other first polysilicon resistances, the second polysilicon resistance or both Parallel connection structures after the first adjacent polysilicon resistance, the second polysilicon resistance parallel connection be connected by metal silicide, conductive plunger, metal interconnecting layer, thus form the larger polysilicon resistance structure of a resistance.
To sum up, the embodiment of the present invention is formation control gate material layer on first area and second area, and the control gate material layer of described first area and second area is synchronously etched, the control gate of gate-division type flash memory is formed in first area, the second polysilicon resistance is formed at second area, and the first polysilicon resistance is formed at second area while the wordline forming gate-division type flash memory, do not need to increase any extra technique, shorten process cycle, and save the consumption of the raw material of deposit spathic silicon, save production technology cost.
Further, the length of the second polysilicon resistance of the embodiment of the present invention is greater than the length of the second side wall, described second side wall only covers the surface, centre position of the second polysilicon resistance, utilize the second side wall being formed in the second polysilicon resistance surface as silicide barrier layer, and described second side wall is formed with the first side wall forming gate-division type flash memory simultaneously, do not need additionally to form self-aligned silicide barrier layer again, save production technology cost.
Further, the embodiment of the present invention forms the 4th insulating barrier on described first polysilicon resistance surface, the second polysilicon material layer is formed at described 4th surface of insulating layer, described second polysilicon material layer and the 4th insulating barrier are as self aligned silicide barrier layer, and described 4th insulating barrier, the second polysilicon material layer are formed with the gate dielectric layer formed in the grid structure of MOS transistor, polygate electrodes simultaneously, do not need additionally to form silicide barrier layer again, save production technology cost.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (15)
1. a formation method for integrated semiconductor device, is characterized in that, comprising:
Semiconductor substrate is provided, described Semiconductor substrate has first area and the second area relative with first area, the semiconductor substrate surface of described first area is formed with the first insulation material layer, described first insulation material layer surface is formed with floating gate material layer, described floating gate material layer surface is formed with the second insulation material layer, the semiconductor substrate surface of described second area is formed with separator, and the second insulation material layer surface of described first area and the insulation surface of second area are formed with control gate material layer;
Form the mask layer with opening in described control gate material surface, wherein, the opening being positioned at first area is the first opening, and the opening being positioned at second area is the second opening;
Form the first side wall at the sidewall of described first opening, form the second side wall at the sidewall of described second opening;
The control gate material layer that the control gate material layer, the second insulation material layer, floating gate material layer, the first insulation material layer and the second opening that come out to described first opening come out etches, until expose the Semiconductor substrate of first area and the separator of second area;
The first oxide layer is formed in described first opening, the second open bottom and sidewall surfaces, and in described first opening, the second opening, fill full polysilicon, polysilicon wherein in the first opening forms wordline, and the polysilicon in the second opening forms the first polysilicon resistance;
The part control gate material layer removed described mask layer and covered by mask layer, be positioned at the control gate material layer formation control grid below the first side wall, the control gate material layer be positioned at below the second side wall forms the second polysilicon resistance, and exposes two end surfaces of described control gate, polysilicon resistance;
Etch described the second insulation material layer, floating gate material layer, the first insulation material layer that are covered by mask layer, until expose the Semiconductor substrate of first area, form gate-division type flash memory in first area;
Two end surfaces exposed at described first polysilicon resistance and the second polysilicon resistance form metal silicide and conductive plunger, form metal interconnecting layer on described conductive plunger surface, and by metal silicide, conductive plunger and metal interconnecting layer the first polysilicon resistance is connected with the second polysilicon resistance and forms polysilicon resistance structure.
2. formation method for integrated semiconductor device as claimed in claim 1, it is characterized in that, also comprise: after forming gate-division type flash memory, the 3rd insulating barrier is formed on described first polysilicon resistance surface, described 3rd insulating layer exposing goes out two end surfaces of the first polysilicon resistance, form metal silicide at described the first polysilicon resistance two end surfaces of exposing and wordline surface, form conductive plunger on described metal silicide surface.
3. formation method for integrated semiconductor device as claimed in claim 1, it is characterized in that, also comprise: after forming gate-division type flash memory, form the 4th insulating barrier on the semiconductor substrate, the second polysilicon material layer is formed at described 4th surface of insulating layer, to the second polysilicon material layer of described first area and part second area, 4th insulating barrier etches, expose the two ends of described first polysilicon resistance and the two ends of the second polysilicon resistance, metal silicide is formed at described the first polysilicon resistance two end surfaces of exposing and the second polysilicon resistance two end surfaces, conductive plunger is formed on described metal silicide surface.
4. formation method for integrated semiconductor device as claimed in claim 3, it is characterized in that, described Semiconductor substrate also comprises the 3rd region, described 3rd region is for the formation of MOS transistor, and the gate dielectric layer in the grid structure of described 4th insulating barrier, the second polysilicon material layer and the 3rd region MOS transistor, polygate electrodes are formed simultaneously.
5. formation method for integrated semiconductor device as claimed in claim 2 or claim 3, it is characterized in that, while described the first polysilicon resistance surface exposed forms metal silicide and conductive plunger, form metal silicide and conductive plunger on the wordline surface of described gate-division type flash memory.
6. formation method for integrated semiconductor device as claimed in claim 1, it is characterized in that, the length of described second polysilicon resistance is greater than the length of the second side wall, described second side wall only covers the surface, centre position of the second polysilicon resistance, the length of described control gate is greater than the length of the first side wall, the surface, centre position of a described first side wall Coverage Control grid, form metal silicide at two end surfaces of described control gate and two end surfaces of described second polysilicon resistance, form conductive plunger on described metal silicide surface.
7. formation method for integrated semiconductor device as claimed in claim 6, it is characterized in that, while the surface at described the second polysilicon resistance two ends exposed forms metal silicide and conductive plunger, form metal silicide and conductive plunger on the control gate surface of the described gate-division type flash memory exposed.
8. the formation method for integrated semiconductor device as described in claim 2,3 or 6, is characterized in that, the formation process of described metal silicide is self-aligned metal silicate formation process.
9. formation method for integrated semiconductor device as claimed in claim 1, it is characterized in that, the material of described control gate material layer is polysilicon, and doped with N-type impurity ion or p type impurity ion in described control gate material layer.
10. formation method for integrated semiconductor device as claimed in claim 1, is characterized in that, doped with N-type impurity ion or p type impurity ion in described first polysilicon resistance.
11. formation method for integrated semiconductor devices as claimed in claim 1, is characterized in that, by controlling the width of the second opening and the second side wall, controlling the resistance of the first polysilicon resistance and the second polysilicon resistance.
12. 1 kinds of polysilicon resistance structures, it is characterized in that, comprise: Semiconductor substrate, be positioned at the separator of described semiconductor substrate surface, be positioned at even number second polysilicon resistance of described insulation surface, be positioned at the side wall on described second surface, polysilicon resistance centre position, the first polysilicon resistance in opening between every two adjacent side walls, be positioned at the metal silicide of the second polysilicon resistance two end surfaces and the first polysilicon resistance two end surfaces do not covered by side wall, be positioned at the conductive plunger on described metal silicide surface, described first polysilicon resistance is connected by the metal interconnecting layer be connected with described conductive plunger with the second polysilicon resistance.
13. polysilicon resistance structures as claimed in claim 12, it is characterized in that, the first adjacent polysilicon resistance is connected by metal silicide, conductive plunger, metal interconnecting layer series connection, the second adjacent polysilicon resistance is connected by metal silicide, conductive plunger, metal interconnecting layer series connection, and one of them first polysilicon resistance is connected by metal silicide, conductive plunger, metal interconnecting layer series connection with one of them second polysilicon resistance.
14. polysilicon resistance structures as claimed in claim 12, is characterized in that, the first adjacent polysilicon resistance, the second polysilicon resistance are connected by metal silicide, conductive plunger, metal interconnecting layer series connection.
15. polysilicon resistance structures as claimed in claim 12, it is characterized in that, connect with other first polysilicon resistances, the second polysilicon resistance or both Parallel connection structures be connected by metal silicide, conductive plunger, metal interconnecting layer after the first adjacent polysilicon resistance, the second polysilicon resistance parallel connection.
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| CN103426727A (en) * | 2013-08-29 | 2013-12-04 | 上海宏力半导体制造有限公司 | Split-grid resistor structure and manufacturing method thereof |
| CN103839778B (en) * | 2014-03-17 | 2016-08-31 | 上海华虹宏力半导体制造有限公司 | Polysilicon resistor structure manufacture method and polysilicon resistor structure |
| CN107919346B (en) * | 2016-10-10 | 2019-12-31 | 北大方正集团有限公司 | Method for manufacturing polysilicon resistor |
| JP6800026B2 (en) * | 2017-01-17 | 2020-12-16 | エイブリック株式会社 | Semiconductor devices and methods for manufacturing semiconductor devices |
| CN114068710B (en) * | 2020-08-03 | 2024-06-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN112820649B (en) * | 2021-02-05 | 2024-04-09 | 上海华虹宏力半导体制造有限公司 | Split gate flash memory and preparation method thereof |
| CN113611745B (en) * | 2021-07-30 | 2024-05-14 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing semiconductor device |
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| US6974748B2 (en) * | 2003-08-21 | 2005-12-13 | Samsung Electronics Co., Ltd. | Semiconductor device with split gate electrode structure and method for manufacturing the semiconductor device |
| CN101377955A (en) * | 2007-08-28 | 2009-03-04 | 三星电子株式会社 | Electrically erasable programmable read-only memory (EEPROM) cell and methods for forming and reading the same |
| CN102290376A (en) * | 2011-08-26 | 2011-12-21 | 上海宏力半导体制造有限公司 | Formation method for integrated semiconductor device |
| CN102364675A (en) * | 2011-10-28 | 2012-02-29 | 上海宏力半导体制造有限公司 | Method for forming flash memory |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6974748B2 (en) * | 2003-08-21 | 2005-12-13 | Samsung Electronics Co., Ltd. | Semiconductor device with split gate electrode structure and method for manufacturing the semiconductor device |
| CN101377955A (en) * | 2007-08-28 | 2009-03-04 | 三星电子株式会社 | Electrically erasable programmable read-only memory (EEPROM) cell and methods for forming and reading the same |
| CN102290376A (en) * | 2011-08-26 | 2011-12-21 | 上海宏力半导体制造有限公司 | Formation method for integrated semiconductor device |
| CN102364675A (en) * | 2011-10-28 | 2012-02-29 | 上海宏力半导体制造有限公司 | Method for forming flash memory |
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