CN102290376B - Formation method for integrated semiconductor device - Google Patents
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- CN102290376B CN102290376B CN201110247674.8A CN201110247674A CN102290376B CN 102290376 B CN102290376 B CN 102290376B CN 201110247674 A CN201110247674 A CN 201110247674A CN 102290376 B CN102290376 B CN 102290376B
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Abstract
A kind of formation method for integrated semiconductor device, comprise: Semiconductor substrate is provided, described Semiconductor substrate has first area and the second area relative with first area, the semiconductor substrate surface of described first area is formed with ground floor silicon oxide layer, the first polysilicon layer, second layer silicon oxide layer successively, and the semiconductor substrate surface of described second area is formed with separation layer; Utilize same formation technique, form the second polysilicon layer at described second layer silicon oxide layer and insulation surface; Remove the second polysilicon layer, second layer silicon oxide layer, the first polysilicon layer, the ground floor silicon oxide layer of the part of described first area, form gate-division type flash memory; Remove the second polysilicon layer of the part of described second area, form polysilicon resistance. Polysilicon layer in described polysilicon resistance is to form in same formation technique with the control gate of gate-division type flash memory, has saved etching, deposition step, has improved technique integrated level.
Description
Technical field
The present invention relates to semiconductor fabrication, particularly formation method for integrated semiconductor device.
Background technology
Along with the characteristic size (CD, CriticalDimension) of semiconductor devices becomes more and more less,The integrated level of semiconductor chip is more and more higher, in unit are, need form element number and type alsoMore and more, thus also more and more higher to the requirement of semiconductor technology. How reasonable arrangement is various different singleThe position of unit and utilize the common ground of each unit manufacture to save semiconductor technology step and material becomesThe focus of research now.
In semiconductor devices is manufactured, polysilicon is a kind of conductive material being in daily use, conventionally can be forMake gate electrode, the high value polysilicon resistance of MOS transistor, floating boom, the control gate etc. of flash memory.
Publication number is that the Chinese patent literature of CN101465161A discloses a kind of gate-division type flash memory, specifically pleaseWith reference to figure 1, comprising: Semiconductor substrate 10, is positioned at two that described Semiconductor substrate 10 spaced surfaces are arrangedStorage bit unit 50, the groove between described two storage bit unit 50, is positioned at the side of described grooveThe tunnel oxide 70 of wall and lower surface, is positioned at tunnel oxide 70 surperficial and the full described groove of fillingPolysilicon word line 40, is positioned at the conductive plunger 20 on described Semiconductor substrate 10 surfaces, described conductive plunger 20Be positioned at the both sides of described storage bit unit 50. Wherein, described storage bit unit 50 comprises being positioned at and describedly partly leadsThe ground floor silicon oxide layer 51 on body substrate 10 surfaces, is positioned at first of described ground floor silicon oxide layer 51 surfacesMulti-crystal silicon floating bar 52, is positioned at the second layer silicon oxide layer 53 on described the first multi-crystal silicon floating bar 52 surfaces, is positioned atFirst polysilicon control grid 54 on described second layer silicon oxide layer 53 surfaces, covers described ground floor silicaThe oxidation of layer 51, the first multi-crystal silicon floating bar 52, second layer silicon oxide layer 53, the first polysilicon control grid 54Silicon side wall 55.
At present, described gate-division type flash memory is to separate to manufacture with polysilicon resistance, first in appointed areaForm after gate-division type flash memory, then form mask layer on described gate-division type flash memory surface, then in other regionsForm polysilicon resistance. But need to deposit one deck polysilicon layer to be used for owing to making described gate-division type flash memoryForm the first polysilicon control grid, after the described polysilicon layer in other regions is etched away, form again another layerPolysilicon layer, to make polysilicon resistance, has caused the waste of material and the increase of processing step, technique collectionCheng Du is lower.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method for integrated semiconductor device, is forming described pointWhen the polysilicon layer of the control gate in gate flash memory, form the polysilicon layer of polysilicon resistance, savedThe consumption of processing step and material, has improved technique integrated level.
For addressing the above problem, the embodiment of the present invention provides a kind of formation method for integrated semiconductor device,Comprise:
Semiconductor substrate is provided, and described Semiconductor substrate has first area and relative with first areaTwo regions, the semiconductor substrate surface of described first area is formed with ground floor silicon oxide layer, and described firstLayer silicon oxide layer surface is formed with the first polysilicon layer, and described the first polysilicon layer surface is formed with the second layerSilicon oxide layer, the semiconductor substrate surface of described second area is formed with separation layer;
Utilize same formation technique, form the second polycrystalline at described second layer silicon oxide layer and insulation surfaceSilicon layer;
Remove the second polysilicon layer, second layer silicon oxide layer, first polycrystalline of the part of described first areaSilicon layer, ground floor silicon oxide layer, until expose described Semiconductor substrate, form the first groove, in instituteState in the first groove and form successively monox lateral wall, tunnel oxide, polysilicon word line, form sub-gateFlash memory;
Remove the second polysilicon layer of the part of described second area, form polysilicon resistance.
Optionally, also comprise: utilize same formation technique to form the second polycrystalline that covers described second areaThe sacrifice silicon nitride on the second polysilicon layer surface of the mask layer of silicon surface and the described first area of coveringLayer.
Optionally, the material of described sacrificial silicon nitride layer and mask layer is silicon nitride.
Optionally, described sacrificial silicon nitride layer and mask layer are removed in same etching technics.
Optionally, the concrete steps that form described gate-division type flash memory comprise:
In described sacrificial silicon nitride layer, be formed with opening, along described opening, substep is to described ground floor oxidationSilicon layer, the first polysilicon layer, second layer silicon oxide layer, the second polysilicon layer carry out the first etching, untilExpose described Semiconductor substrate, form the first groove;
At described ground floor silicon oxide layer, the first polysilicon layer, second layer silicon oxide layer, the second polysiliconLayer, sacrificial silicon nitride layer sidewall surfaces form monox lateral wall, between described monox lateral wall secondThe sidewall of groove and lower surface form tunnel oxide, utilize polysilicon to fill described the second groove and formPolysilicon word line;
Sacrificial silicon nitride layer to described first area, ground floor silicon oxide layer, the first polysilicon layer,Two layers of silicon oxide layer and the second polysilicon layer carry out the second etching until expose Semiconductor substrate, form pointGate flash memory.
Optionally, utilize the second etching technics to carry out etching to the second polysilicon layer of described first areaMeanwhile, the second polysilicon layer of second area described in etching.
Optionally, the concrete steps that form described polysilicon resistance comprise:
Removal is positioned at part second polysilicon layer of second area until expose separation layer;
Form passivation layer on described the second polysilicon layer surface, described passivation layer exposes part described secondPolysilicon layer surface;
Described the second polysilicon layer surface exposing at described passivation layer forms metal silicide;
Surface and sidewall at described the second polysilicon layer, passivation layer, metal silicide form the 3rd layer of oxygenSiClx layer, forms polysilicon resistance.
Optionally, also comprise, form side wall at described the 3rd layer of silicon oxide layer and gate-division type flash memory sidewall.
Optionally, the side wall that is positioned at described the 3rd layer of silicon oxide layer and gate-division type flash memory sidewall is in same formationIn technique, complete.
Optionally, also comprise, when described the second polysilicon layer surface forms passivation layer, utilize sameOne forms technique, forms passivation layer, with described passivation on described Semiconductor substrate, gate-division type flash memory surfaceLayer is mask, forms transistor in other regions of described Semiconductor substrate.
Optionally, described passivation thickness range is layer by layer
Optionally, described first area is the region that forms gate-division type flash memory, and described second area is for formingThe region of polysilicon resistance.
Compared with prior art, the present invention has the following advantages:
The formation method for integrated semiconductor device of the embodiment of the present invention forms gate-division type flash memory and polysilicon simultaneouslyResistance, and the control gate of described gate-division type flash memory and the polysilicon layer of polysilicon resistance are at same processing stepIn complete, saved processing step, improved technique integrated level.
Further, by form and remove sacrificial silicon nitride layer and mask layer simultaneously, saved technique stepSuddenly, improved technique integrated level.
Further, by controlling the area of polysilicon layer of described passivation layer cover graphics, just canControl the resistance of described polysilicon resistance, simple and convenient.
Brief description of the drawings
Fig. 1 is the cross-sectional view of the gate-division type flash memory of prior art;
Fig. 2 is the schematic flow sheet of the formation method for integrated semiconductor device of the embodiment of the present invention;
Fig. 3 to Figure 11 is the cross-section structure signal of the formation method for integrated semiconductor device of the embodiment of the present inventionFigure.
Detailed description of the invention
When form gate-division type flash memory and polysilicon resistance on same substrate time, due to the polysilicon formingThe manufacture process of resistance all comprises formation polysilicon layer and described polysilicon layer is carried out to etching, if by shapeAfter becoming the polysilicon layer depositing in gate-division type flash memory process to etch away, deposit again another layer of polysilicon layer for shapeBecome polysilicon resistance, so not only increased processing step and wasted the raw material of deposit spathic silicon layer.
For this reason, inventor, through having researched and proposed a kind of formation method for integrated semiconductor device, comprising: carryFor Semiconductor substrate, described Semiconductor substrate has first area and the second area relative with first area,The semiconductor substrate surface of described first area is formed with ground floor silicon oxide layer, described ground floor silicaLayer surface is formed with the first polysilicon layer, and described the first polysilicon layer surface is formed with second layer silicon oxide layer,The semiconductor substrate surface of described second area is formed with separation layer; Utilize same formation technique, describedSecond layer silicon oxide layer and insulation surface form the second polysilicon layer; Remove the part of described first areaThe second polysilicon layer, second layer silicon oxide layer, the first polysilicon layer, ground floor silicon oxide layer, untilExpose described Semiconductor substrate, form the first groove, in described the first groove, form successively silicaSide wall, tunnel oxide, polysilicon word line, form gate-division type flash memory; Remove the portion of described second areaThe second polysilicon layer dividing, forms polysilicon resistance.
Due to the control gate of gate-division type flash memory described in the embodiment of the present invention be by first area secondPolysilicon layer etching forms, and polysilicon layer in described polysilicon resistance is also by by Second RegionThe second polysilicon layer etching in territory forms, and second polysilicon layer deposition and the etching in described two regionsTechnique is synchronously carried out, and has saved etching, deposition step, and has saved the consumption of the raw material of deposit spathic silicon,Improve technique integrated level.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawingThe specific embodiment of the present invention is described in detail.
Set forth detail in the following description so that fully understand the present invention. But the present invention canBe different from alternate manner described here and implement with multiple, those skilled in the art can be without prejudice to thisIn the situation of invention intension, do similar popularization. Therefore the present invention is not subject to the restriction of following public concrete enforcement.
The embodiment of the present invention provides a kind of formation method for integrated semiconductor device, concrete schematic flow sheetPlease refer to Fig. 2, comprising:
Step S101, provides Semiconductor substrate, described Semiconductor substrate have first area and with the firstth districtThe second area that territory is relative, forms ground floor silicon oxide layer at the semiconductor substrate surface of described first area,Form the first polysilicon layer on described ground floor silicon oxide layer surface, described the first polysilicon layer surface shapeBecome second layer silicon oxide layer, form separation layer at the semiconductor substrate surface of described second area;
Step S102, utilizes same formation technique, described second layer silicon oxide layer and insulation surface shapeBecome the second polysilicon layer;
Step S103, remove the part of described first area the second polysilicon layer, second layer silicon oxide layer,The first polysilicon layer, ground floor silicon oxide layer, until expose described Semiconductor substrate, form the first ditchGroove forms successively monox lateral wall, tunnel oxide, polysilicon word line, shape in described the first grooveBecome gate-division type flash memory;
Step S104, removes the second polysilicon layer of the part of described second area, forms polysilicon resistance.
Fig. 3 to Figure 11 is the cross-section structure signal of the formation method for integrated semiconductor device of the embodiment of the present inventionFigure.
Please refer to Fig. 3, Semiconductor substrate 100 is provided, described Semiconductor substrate 100 has first area IWith the second area II relative with first area I.
Described Semiconductor substrate 100 can be silicon substrate, germanium silicon substrate, gallium arsenide substrate, gallium nitride liningThe end or silicon-on-insulator substrate one wherein. Those skilled in the art can be according to be formed partly leadingBody integrated device is selected the type of described Semiconductor substrate 100, and therefore the type of described Semiconductor substrate is notShould too limit the scope of the invention.
Described Semiconductor substrate 100 has first area I and the second area II relative with first area I.Described first area I is adjacent with second area II or be separated by. In subsequent technique, form at described first area IGate-division type flash memory, forms polysilicon resistance at second area II. At actual fabrication of semiconductor deviceIn, described Semiconductor substrate 100 has one or more first area I and second area II, in this enforcementIn example, the second area II adjacent with described first area I with a first area I does exemplaryIllustrate, the quantity of described first area and second area and position should too not limit the scope of the invention.
Between described first area I and second area II, can also comprise fleet plough groove isolation structure (not shown),Described fleet plough groove isolation structure is for the device of the electricity described first area I of isolation and second area II formation.
Please refer to Fig. 4, form ground floor silica on Semiconductor substrate 100 surfaces of described first area ILayer 111, forms the first polysilicon layer 112 on described ground floor silicon oxide layer 111 surfaces, described firstPolysilicon layer 112 surfaces form second layer silicon oxide layer 113, in the Semiconductor substrate of described second area II100 surfaces form separation layer 210.
Described the first polysilicon layer 112 is used to form the floating boom of gate-division type flash memory in subsequent technique, described inGround floor silicon oxide layer 111 is for isolating the first polysilicon layer 112 and Semiconductor substrate 100, described secondLayer silicon oxide layer 113 is for isolating the first polysilicon layer 112 and the second polysilicon layer 114. Described ground floorThe formation technique of silicon oxide layer 111 and second layer silicon oxide layer 113 is thermal oxidation technology or chemical vapour deposition (CVD)Technique, the formation technique of described the first polysilicon layer 112 is chemical vapor deposition method.
Described separation layer 210 is silicon oxide film, is used to the polysilicon resistance of follow-up formation to do substrate,And the described Semiconductor substrate 100 of electricity isolation and the polysilicon resistance that is positioned at described separation layer 210 surfaces. ShapeThe technique that becomes described separation layer 210 is local oxidation of silicon technique (LOCOS) or shallow ditch groove separation process(STI) one wherein, in the present embodiment, the formation technique of described separation layer is that shallow trench isolation is from workSkill (STI).
The processing step that forms described separation layer 210 can enter before forming described ground floor silicon oxide layerOK, also form described second layer silicon oxide layer and carry out before, also can form described second layer silicaAfter layer, carry out. In the present embodiment, the technique of described formation separation layer 210 is forming the described second layerBefore silicon oxide layer, carry out. Described ground floor silicon oxide layer 111, the first polysilicon layer 112, second layer oxygenSiClx layer 113, the concrete formation step of separation layer 210 comprise: comply with on described Semiconductor substrate 100 surfacesInferior formation ground floor silicon oxide layer 111, the first polysilicon layer 112, show at described the first polysilicon layer 112Face forms silicon nitride layer (not shown), taking patterned photoresist layer as mask, to the nitrogenize of second areaSilicon layer, the first polysilicon layer 112, ground floor silicon oxide layer 111, Semiconductor substrate 100 are carved successivelyErosion, until expose the Semiconductor substrate 100 of second area II; At the silicon nitride layer of described first areaForm silicon oxide layer (not shown) with Semiconductor substrate 100 surface depositions of second area; With described nitrogenizeSilicon layer is polish stop, and described silicon oxide layer is carried out to chemically mechanical polishing, until expose describedThe silicon nitride layer surface in one region, the silicon oxide layer that is positioned at second area forms separation layer 210; Described in removingThe silicon nitride layer of first area; Form oxidation at described the first polysilicon layer 112 and separation layer 210 surfacesSilicon layer, removes the silicon oxide layer on described separation layer 210 surfaces, forms and is positioned at described the first polysilicon layer 112The second layer silicon oxide layer 113 on surface.
In other embodiments, because described the first polysilicon layer 112 and separation layer 210 surfaces formThe material of silicon oxide layer is identical with the material of separation layer, and the effect of two media layer is all electric isolation,Can not remove the silicon oxide layer on described separation layer 210 surfaces, reduce processing step.
Please refer to Fig. 5, utilize same formation technique, at described second layer silicon oxide layer 113 and separation layer210 surfaces form the second polysilicon layer 114.
Described the second polysilicon layer 114 that is arranged in first area I is used for forming sub-gate sudden strain of a muscle at subsequent techniqueThe control gate of depositing, described in be arranged in second area II the second polysilicon layer 114 at subsequent technique for shapeBecome polysilicon resistance. Because the second polysilicon layer 114 that utilizes same formation technique to form can be made respectivelyMake control gate and the polysilicon resistance of gate-division type flash memory, and do not need to sink forming in gate-division type flash memory processAfter long-pending polysilicon layer etches away, deposit again another layer of polysilicon layer and be used to form polysilicon resistance, savedEtching, deposition step, and the consumption of having saved the raw material of deposit spathic silicon, improved technique integrated level.
The technique that forms described the second polysilicon layer is chemical vapor deposition method, owing to forming described secondThe technique of polysilicon layer is the technology of the present invention those skilled in the art's known technology, is not repeating at this.
Please refer to Fig. 6, utilize same formation technique to form the second polysilicon that covers described second area IIThe mask layer 260 on layer 114 surface and cover the second polysilicon layer 114 surfaces sacrificial of described first area IDomestic animal silicon nitride layer 115.
Because the second polysilicon layer 114 surfaces that are positioned at second area II are formed with mask layer 260, make instituteThe second polysilicon layer 114 of stating second area II can not be subject to etching in follow-up formation gate-division type flash memory processOr the impact of depositing operation. The described sacrificial silicon nitride layer 115 that is positioned at first area I is divided in follow-up formationIn the technique of gate flash memory, serve as polish stop. Described mask layer 260 and sacrificial silicon nitride layer 115Material is silicon nitride layer, and the method that forms described mask layer 260 is chemical vapor deposition method. Due to instituteState mask layer 260 and sacrificial silicon nitride layer 115 and form in same formation technique, reduced processing step,Improve technique integrated level.
Please refer to Fig. 7, in described sacrificial silicon nitride layer 115, be formed with opening (not shown), along described inOpening, substep is to described ground floor silicon oxide layer 111, the first polysilicon layer 112, second layer silicon oxide layer113, the second polysilicon layer 114 carries out the first etching, until expose described Semiconductor substrate 100, shapeBecome the first groove 116.
Substep to described ground floor silicon oxide layer 111, the first polysilicon layer 112, second layer silicon oxide layer 113,The step that the second polysilicon layer 114 carries out the first etching comprises: first, adopt photoetching process to described theOne deck silicon oxide layer 111, the first polysilicon layer 112, second layer silicon oxide layer 113, the second polysilicon layer114 carry out etching, remove the described ground floor silicon oxide layer of part 111, the first polysilicon layer 112, secondLayer silicon oxide layer 113, the second polysilicon layer 114, until expose Semiconductor substrate 100; Afterwards, adoptWith photoetching process etching second layer silicon oxide layer 113, the second polysilicon layer 114, remove part second layer oxygenSiClx layer 113, the second polysilicon layer 114 are until expose the first polysilicon layer 112, formation the first groove116。
In other embodiments, also can be first the second polysilicon layer 114, to described opening exposed regionTwo layers of silicon oxide layer 113 carry out etching, until expose described the first polysilicon layer 112; To described firstThe exposed region of polysilicon layer 112 carries out etching, until expose described Semiconductor substrate 100. Described halfThe exposed region of conductive substrate 100 is less than the exposed region of described the first polysilicon layer 112.
Please refer to Fig. 8, at described ground floor silicon oxide layer 111, the first polysilicon layer 112, second layer oxygenSiClx layer 113, the second polysilicon layer 114, sacrificial silicon nitride layer 115 sidewall surfaces form monox lateral wall117, the sidewall of the second groove (not shown) between described monox lateral wall 117 and lower surface shapeBecome tunnel oxide 118, utilize polysilicon to fill described the second groove and form polysilicon word line 119;
Due in the operation of gate-division type flash memory data erase, utilize floating that the first polysilicon layer 112 formsElectronics in grid need to be tunneling to polysilicon word line 119 by tunnel oxide 118 and monox lateral wall 117In, the side wall ratio that is positioned at described the first polysilicon layer 112 sidewalls is positioned at described the second polysilicon layer 114 sidesThe side wall thicknesses of wall is thin, and described the first polysilicon layer 112 is than described the second polysilicon layer 114 etchingsLess, and the operating voltage difference of different flash memories, the thickness of required tunnel oxide also can be different,By adjusting the thickness of tunnel oxide, just can realize the effective control to the electronics in floating boom.
The technique that forms described polysilicon word line 119 comprises: in described Semiconductor substrate 100, sacrifice nitrogenizeSilicon layer 115, tunnel oxide 118 surfaces utilize chemical vapour deposition (CVD) to form polysilicon (not shown), instituteState polysilicon and filled up the second groove between described monox lateral wall 117, with sacrificial silicon nitride layer 115For etching barrier layer, described polysilicon is carried out to chemically mechanical polishing, until expose described sacrifice nitrogenizeSilicon layer 115 forms polysilicon word line 119 in described the second groove.
Incorporated by reference to reference to figure 9 and Fig. 8, remove described sacrificial silicon nitride layer 115 and mask layer 260, and rightDescribed ground floor silicon oxide layer 111, the first polysilicon layer 112, second layer silicon oxide layer 113, more than secondCrystal silicon layer 114 carries out the second etching, forms gate-division type flash memory 120, more than second of described second area IICrystal silicon layer 114 carries out the second etching, forms polysilicon resistance figure 220.
Described in etching, the method for sacrificial silicon nitride layer 115 and mask layer 260 comprises that dry etching and wet method carveErosion, in the present embodiment, utilizes hot phosphoric acid wet etching in same processing step to fall sacrificial silicon nitride layer115 and mask layer 260, save processing step. In other embodiments, described mask layer 260 is with sacrificialDomestic animal silicon nitride layer 115 can be removed in division step.
Remove after described sacrificial silicon nitride layer 115, taking patterned photoresist layer as mask, described figureThe photoresist layer of changing is corresponding with the position of monox lateral wall 117, polysilicon word line 119, and effects on surface is removedThe ground floor silicon oxide layer 111 of the first area I of sacrificial silicon nitride layer 115, the first polysilicon layer 112,Second layer silicon oxide layer 113, the second polysilicon layer 114 carry out etching, form gate-division type flash memory 120.
The concrete steps that form described polysilicon resistance figure 220 comprise: taking photoetching offset plate figure as mask,Described photoetching offset plate figure is corresponding to the shape of polysilicon resistance, concrete is shaped as strip, S shape etc., rightThe second polysilicon layer 114 of described second area II carries out etching, until expose separation layer 210, formsPatterned polysilicon layer 220. Wherein, described polysilicon resistance figure 220 is positioned at described separation layer 210Surface.
In the present embodiment, the second etching of the second polysilicon layer 114 to described first area I and to instituteState second being etched in same etching technics step and completing of the second polysilicon layer 114 of second area II, withSave processing step. In other embodiments, the second polysilicon layer 114 and the institute to described first area IStating the etching of the second polysilicon layer 114 of second area II separately carries out.
Form silicon oxide layer on described gate-division type flash memory 120 sidewalls, surface and Semiconductor substrate 100 surfaces(not shown), makes floating boom, control gate and extraneous electricity isolation in gate-division type flash memory 120, and preventsIn the ion doping technique of rear end by Implantation in floating boom, control gate, affect the electric property of device.
Before forming described polysilicon resistance figure 220, to the second polysilicon layer of described second area114 carry out ion doping, to regulate the resistivity of polysilicon resistance, the ion of described doping be phosphonium ion,Arsenic ion, boron ion one wherein. In other embodiments, to described the second polysilicon layer carry out fromThe technique of son doping also can be carried out after etching forms polysilicon resistance figure.
Please refer to Figure 10, form passivation layer 230 on described polysilicon resistance figure 220 surfaces, described bluntChange layer 230 and expose part polysilicon resistance figure 220 surfaces, expose at described passivation layer 230Described polysilicon resistance figure 220 surfaces form metal silicide 240.
The material of described passivation layer 230 is silicon nitride layer, and thickness range isDescribed in formationThe technique of passivation layer 230 comprises: at described Semiconductor substrate 100, polysilicon resistance figure 220, point gridFormula flash memory 120 surfaces form silicon nitride layer (not shown), adopt photoetching process to carry out described silicon nitride layerEtching, forms passivation layer 230. Described passivation layer 230 is positioned at the surperficial and sudden and violent of polysilicon resistance figure 220Expose the two ends of polysilicon resistance figure 220, the two ends of described polysilicon resistance figure 220 are used to formMetal silicide 240. Because polysilicon resistance figure 220 regions that covered by described passivation layer 230 are for realThe polysilicon resistance on border, and surface is formed with polysilicon resistance figure 220 regions of metal silicide 240Just be used for being electrically connected conductive plunger, the polysilicon resistance figure covering by controlling described passivation layer 230220 area, just can control the resistance of described polysilicon resistance.
In other embodiments, form polysilicon resistance at the second polysilicon layer of second area described in etchingBefore figure, form passivation layer on the second polysilicon layer surface of described second area, then by photoetching andEtching technics, forms the surperficial polysilicon resistance figure with passivation layer.
In other embodiments, in order further to improve technique integrated level, at its of described Semiconductor substrateHe is also formed with MOS transistor in region. At first area and the second area, many of described Semiconductor substrateCrystal silicon resistance pattern, gate-division type flash memory surface form after silicon nitride layer, and described silicon nitride layer is as passivation layerMask, utilizes described passivation layer mask, forms transistor in other regions of described Semiconductor substrate.
The technique that forms metal silicide 240 comprises: at the two ends of described patterned polysilicon layer 220Forming metal layer on surface (not shown), the material of described metal level be titanium, cobalt, tungsten, nickel, manganese, platinum,Tantalum one wherein, heat-treats described metal level, forms metal silicide 240. Form described goldThe known technology that the method that belongs to silicide is those skilled in the art, does not repeat them here.
Please refer to Figure 11, on the surface of described polysilicon layer 220, passivation layer 230, metal silicide 240Form the 3rd layer of silicon oxide layer 250 with sidewall, form polysilicon resistance 270.
Described the 3rd layer of silicon oxide layer 250 covers described polysilicon layer 220, passivation layer 230, metal silicationThe surface of thing 240 and sidewall, make described polysilicon layer 220 and extraneous electricity isolation.
Forming after the 3rd layer of silicon oxide layer 250, also comprise, described the 3rd layer of silicon oxide layer 250 HeGate-division type flash memory 120 sidewalls form side walls 300, the material of described side wall 300 be silicon nitride, silica orBoth laminated construction, described side wall 300 can prevent control gate in gate-division type flash memory 120, floating boom andPolysilicon layer and the external world in polysilicon resistance 270 electrically contact. Describedly be positioned at the 3rd layer of silicon oxide layer 250Can in same processing step, carry out with the side wall of gate-division type flash memory 120 sidewalls, to reduce processing step,Improve technique integrated level.
In other embodiments, in order further to improve technique integrated level, at its of described Semiconductor substrateHe is also formed with MOS transistor in region, the gate oxide of described MOS transistor and described the 3rd layer of oxygenSiClx layer 250 forms in same depositing operation, forms polysilicon on described the 3rd layer of silicon oxide layer surfaceLayer, described polysilicon layer is used to form the gate electrode of MOS transistor.
The formation method for integrated semiconductor device of the embodiment of the present invention forms gate-division type flash memory and polysilicon simultaneouslyResistance, and the control gate of described gate-division type flash memory and the polysilicon layer of polysilicon resistance are at same processing stepIn complete, saved processing step, improved technique integrated level.
Further, by form and remove sacrificial silicon nitride layer and mask layer simultaneously, saved technique stepSuddenly, improved technique integrated level.
Further, by controlling the area of polysilicon layer of described passivation layer cover graphics, just canControl the resistance of described polysilicon resistance, simple and convenient.
Although the present invention with preferred embodiment openly as above, it is not for limiting the present invention, appointsWhat those skilled in the art without departing from the spirit and scope of the present invention, can utilize above-mentioned announcementMethod and technology contents are made possible variation and amendment to technical solution of the present invention, therefore, every not de-From the content of technical solution of the present invention, that according to technical spirit of the present invention, above embodiment is done is anySimple modification, equivalent variations and modification, all belong to the protection domain of technical solution of the present invention.
Claims (20)
1. a formation method for integrated semiconductor device, is characterized in that, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate has first area and relative with first areaTwo regions, the semiconductor substrate surface of described first area is formed with ground floor silicon oxide layer, and described firstLayer silicon oxide layer surface is formed with the first polysilicon layer, and described the first polysilicon layer surface is formed with the second layerSilicon oxide layer, the semiconductor substrate surface of described second area is formed with separation layer;
Utilize same formation technique, form the second polycrystalline at described second layer silicon oxide layer and insulation surfaceSilicon layer;
Remove the second polysilicon layer, second layer silicon oxide layer, first polycrystalline of the part of described first areaSilicon layer, ground floor silicon oxide layer, until expose described Semiconductor substrate, form the first groove, in instituteState in the first groove and form successively monox lateral wall, tunnel oxide, polysilicon word line, form sub-gateFlash memory;
Remove the second polysilicon layer of the part of described second area, form polysilicon resistance;
Also comprise: utilize same formation technique to form the second polysilicon layer surface that covers described second areaMask layer and cover the sacrificial silicon nitride layer on the second polysilicon layer surface of described first area;
Wherein, the concrete steps that form described gate-division type flash memory comprise:
In described sacrificial silicon nitride layer, be formed with opening, along described opening, substep to described ground floor silicon oxide layer,The first polysilicon layer, second layer silicon oxide layer, the second polysilicon layer carry out the first etching, until exposeDescribed Semiconductor substrate, forms the first groove;
At described ground floor silicon oxide layer, the first polysilicon layer, second layer silicon oxide layer, the second polysiliconLayer, sacrificial silicon nitride layer sidewall surfaces form monox lateral wall, between described monox lateral wall secondThe sidewall of groove and lower surface form tunnel oxide, utilize polysilicon to fill described the second groove and formPolysilicon word line;
Sacrificial silicon nitride layer to described first area, ground floor silicon oxide layer, the first polysilicon layer,Two layers of silicon oxide layer and the second polysilicon layer carry out the second etching until expose Semiconductor substrate, form pointGate flash memory.
2. formation method for integrated semiconductor device as claimed in claim 1, is characterized in that, described sacrifice nitrogenThe material of SiClx layer and mask layer is silicon nitride.
3. formation method for integrated semiconductor device as claimed in claim 1, is characterized in that, described sacrifice nitrogenSiClx layer and mask layer are removed in same etching technics.
4. formation method for integrated semiconductor device as claimed in claim 1, is characterized in that, utilizes for the second quarterWhen etching technique carries out etching to the second polysilicon layer of described first area, Second Region described in etchingSecond polysilicon layer in territory.
5. formation method for integrated semiconductor device as claimed in claim 1, is characterized in that, forms described manyThe concrete steps of crystal silicon resistance comprise:
Removal is positioned at part second polysilicon layer of second area until expose separation layer;
Form passivation layer on described the second polysilicon layer surface, described passivation layer exposes part described secondPolysilicon layer surface;
Described the second polysilicon layer surface exposing at described passivation layer forms metal silicide;
Surface and sidewall at described the second polysilicon layer, passivation layer, metal silicide form the 3rd layer of oxygenSiClx layer, forms polysilicon resistance.
6. formation method for integrated semiconductor device as claimed in claim 5, is characterized in that, also comprise,Described the 3rd layer of silicon oxide layer and gate-division type flash memory sidewall form side wall.
7. formation method for integrated semiconductor device as claimed in claim 6, is characterized in that, is positioned at describedThe side wall of three layers of silicon oxide layer and gate-division type flash memory sidewall completes in same formation technique.
8. formation method for integrated semiconductor device as claimed in claim 5, is characterized in that, also comprise,When described the second polysilicon layer surface forms passivation layer, utilize same formation technique, described halfConductive substrate, gate-division type flash memory surface form passivation layer, taking described passivation layer as mask, described halfOther regions of conductive substrate form transistor.
9. formation method for integrated semiconductor device as claimed in claim 5, is characterized in that, described passivation layerThe thickness range of layer is
10. formation method for integrated semiconductor device as claimed in claim 1, is characterized in that, described the firstth districtTerritory is the region that forms gate-division type flash memory, and described second area is the region that forms polysilicon resistance.
11. 1 kinds of formation method for integrated semiconductor devices, is characterized in that, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate has first area and relative with first areaTwo regions, the semiconductor substrate surface of described first area is formed with ground floor silicon oxide layer, and described firstLayer silicon oxide layer surface is formed with the first polysilicon layer, and described the first polysilicon layer surface is formed with the second layerSilicon oxide layer, the semiconductor substrate surface of described second area is formed with separation layer;
Utilize same formation technique, form the second polycrystalline at described second layer silicon oxide layer and insulation surfaceSilicon layer;
Remove the second polysilicon layer, second layer silicon oxide layer, first polycrystalline of the part of described first areaSilicon layer, ground floor silicon oxide layer, until expose described Semiconductor substrate, form the first groove, in instituteState in the first groove and form successively monox lateral wall, tunnel oxide, polysilicon word line, form sub-gateFlash memory;
Remove the second polysilicon layer of the part of described second area, form polysilicon resistance;
Wherein, the concrete steps that form described polysilicon resistance comprise:
Removal is positioned at part second polysilicon layer of second area until expose separation layer;
Form passivation layer on described the second polysilicon layer surface, described passivation layer exposes part described secondPolysilicon layer surface;
Described the second polysilicon layer surface exposing at described passivation layer forms metal silicide;
Surface and sidewall at described the second polysilicon layer, passivation layer, metal silicide form the 3rd layer of oxygenSiClx layer, forms polysilicon resistance.
12. formation method for integrated semiconductor devices as claimed in claim 11, is characterized in that, also comprise: profitForm the mask layer on the second polysilicon layer surface that covers described second area and cover by same formation techniqueCover the sacrificial silicon nitride layer on the second polysilicon layer surface of described first area.
13. formation method for integrated semiconductor devices as claimed in claim 12, is characterized in that, described sacrifice nitrogenThe material of SiClx layer and mask layer is silicon nitride.
14. formation method for integrated semiconductor devices as claimed in claim 12, is characterized in that, described sacrifice nitrogenSiClx layer and mask layer are removed in same etching technics.
15. formation method for integrated semiconductor devices as claimed in claim 12, is characterized in that, form described pointThe concrete steps of gate flash memory comprise:
In described sacrificial silicon nitride layer, be formed with opening, along described opening, substep is to described ground floor oxidationSilicon layer, the first polysilicon layer, second layer silicon oxide layer, the second polysilicon layer carry out the first etching, untilExpose described Semiconductor substrate, form the first groove;
At described ground floor silicon oxide layer, the first polysilicon layer, second layer silicon oxide layer, the second polysiliconLayer, sacrificial silicon nitride layer sidewall surfaces form monox lateral wall, between described monox lateral wall secondThe sidewall of groove and lower surface form tunnel oxide, utilize polysilicon to fill described the second groove and formPolysilicon word line;
Sacrificial silicon nitride layer to described first area, ground floor silicon oxide layer, the first polysilicon layer,Two layers of silicon oxide layer and the second polysilicon layer carry out the second etching until expose Semiconductor substrate, form pointGate flash memory;
When utilizing the second etching technics to carry out etching to the second polysilicon layer of described first area, carveLose the second polysilicon layer of described second area.
16. formation method for integrated semiconductor devices as claimed in claim 11, is characterized in that, also comprise,Described the 3rd layer of silicon oxide layer and gate-division type flash memory sidewall form side wall.
17. formation method for integrated semiconductor devices as claimed in claim 16, is characterized in that, are positioned at describedThe side wall of three layers of silicon oxide layer and gate-division type flash memory sidewall completes in same formation technique.
18. formation method for integrated semiconductor devices as claimed in claim 11, is characterized in that, also comprise,When described the second polysilicon layer surface forms passivation layer, utilize same formation technique, described halfConductive substrate, gate-division type flash memory surface form passivation layer, taking described passivation layer as mask, described halfOther regions of conductive substrate form transistor.
19. formation method for integrated semiconductor devices as claimed in claim 11, is characterized in that, described passivation layerThe thickness range of layer is
20. formation method for integrated semiconductor devices as claimed in claim 11, is characterized in that, described the firstth districtTerritory is the region that forms gate-division type flash memory, and described second area is the region that forms polysilicon resistance.
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| CN103021953B (en) * | 2012-12-21 | 2016-05-11 | 上海华虹宏力半导体制造有限公司 | Formation method for integrated semiconductor device |
| CN103021955B (en) * | 2012-12-21 | 2016-04-06 | 上海华虹宏力半导体制造有限公司 | The formation method for integrated semiconductor device of polysilicon resistance structure and correspondence |
| CN103413809B (en) * | 2013-08-23 | 2016-04-06 | 上海华虹宏力半导体制造有限公司 | Gate-division type flash memory and forming method thereof |
| CN104916591B (en) * | 2014-03-11 | 2018-01-12 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of semiconductor devices |
| CN104538361B (en) * | 2014-12-25 | 2017-08-25 | 上海华虹宏力半导体制造有限公司 | The method for controlling flash cell threshold voltage |
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