CN103019291A - Low-voltage-difference linear voltage stabilizer circuit - Google Patents
Low-voltage-difference linear voltage stabilizer circuit Download PDFInfo
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- CN103019291A CN103019291A CN2012105641968A CN201210564196A CN103019291A CN 103019291 A CN103019291 A CN 103019291A CN 2012105641968 A CN2012105641968 A CN 2012105641968A CN 201210564196 A CN201210564196 A CN 201210564196A CN 103019291 A CN103019291 A CN 103019291A
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Abstract
The invention discloses a low-voltage-difference linear voltage stabilizer circuit. The low-voltage-difference linear voltage stabilizer circuit is characterized in that the output end of a low-voltage-difference linear voltage stabilizer is connected with an auxiliary circuit; the auxiliary circuit comprises a first resistor, a first capacitor and a pull-up transistor; and due to an RC (Resistance-Capacitance) oscillating circuit formed by the first resistor and the first capacitor, when negative pulse occurs on the voltage of the output end of the low-voltage-difference linear voltage stabilizer and the low-voltage-difference linear voltage stabilizer can not response in time, the RC oscillating circuit is utilized for opening the pull-up transistor, the pull-up transistor is utilized for pulling the voltage of the output end of the low-voltage-difference linear voltage stabilizer, so that the falling range of the voltage of the output end is less; and finally, the low-voltage-difference linear voltage stabilizer is utilized for restoring the voltage of the output end into the original output voltage. The low-voltage-difference linear voltage stabilizer circuit has the advantages that since the falling range of the voltage of the output end is less, a load device can work normally, and the reliability of the circuit in the load can not be influenced; and under the normal condition, the auxiliary circuit does not need to generate power consumption without influence on the normal working of a power supply.
Description
Technical field
The present invention relates to integrated circuit fields, particularly a kind of low differential voltage linear voltage stabilizer circuit.
Background technology
That low pressure difference linear voltage regulator (Low Dropout Regulator, LDO) has is simple in structure, low noise, low-power consumption and the advantages such as little encapsulation and less peripheral applications device, is widely used in portable type electronic product.Low pressure difference linear voltage regulator belongs to the step-down transformer in the DC/DC transducer, in the situation that load is certain, its output voltage is in certain scope, therefore, the low differential voltage linear voltage stabilizer circuit system can guarantee output voltage stable of power supply, is conducive to improve power source life.
Please refer to Fig. 1, be the structural representation of existing low differential voltage linear voltage stabilizer circuit.Described low pressure difference linear voltage regulator 10 comprises: error amplifier 11, voltage-reg-ulator tube 12, the second resistance 13, the 3rd resistance 14; The reverse input end of described error amplifier 11 links to each other with voltage reference signal Vref, the output terminal of described error amplifier 11 is connected with the grid of described voltage-reg-ulator tube 12, the source electrode of described voltage-reg-ulator tube 12 meets high level Vdd, the drain electrode of described voltage-reg-ulator tube 12 is connected with an end of the second resistance 13, one end of the other end of described the second resistance 13, the 3rd resistance 14 is connected with the positive input of error amplifier 11, the other end ground connection of described the 3rd resistance 14; Wherein, described voltage reference signal Vref is as the input signal of low pressure difference linear voltage regulator, and the end that the drain electrode of described voltage-reg-ulator tube 12 is connected with the second resistance R 2 is as the output end vo ut of low pressure difference linear voltage regulator.
Owing to the equivalent resistance of the output terminal of described low pressure difference linear voltage regulator can change along with the variation of load, so that the voltage of output terminal can change a lot, produce overshoot (overshoot) or lose punching (undershoot).For example when the load current of the load that links to each other with output terminal becomes suddenly large, the voltage of the output terminal of low pressure difference linear voltage regulator can diminish suddenly, produce and lose punching (undershoot), and because the low pressure difference linear voltage regulator response need to have the regular hour, before voltage-reg-ulator tube 12 did not return to original output voltage with the voltage of output terminal fully, the voltage of described output terminal had a negative pulse.When original stable output voltage was 3.3V, the voltage that is dragged down rear output terminal by described negative pulse only had 1V even lower, may make the part of devices cisco unity malfunction, can have a strong impact on the reliability of circuit in the load.
Therefore, please refer to Fig. 1, usually can add an output capacitance 15 at the output end vo ut of described low pressure difference linear voltage regulator 10, described output capacitance 15 has an equivalent resistance in series 16.Utilize 15 pairs of electric currents that increase suddenly of described output capacitance to compensate, thereby reduce negative pulse.But owing to being subject to the consideration of technique and cost of manufacture, the electric capacity of described output capacitance 15 is usually less, can not be effectively the electric current of unexpected increase be compensated, still can form larger negative pulse, the voltage that is dragged down rear output terminal by described negative pulse still can be down to 1.5V even lower.
More information about low pressure difference linear voltage regulator please refer to the Chinese patent literature that application publication number is CN102200791A.
Summary of the invention
The problem that the present invention solves provides a kind of low differential voltage linear voltage stabilizer circuit, so that load current is when becoming suddenly large, the negative pulse that the output terminal of low pressure difference linear voltage regulator produces is less.
For addressing the above problem, technical solution of the present invention provides a kind of low differential voltage linear voltage stabilizer circuit, comprising: low pressure difference linear voltage regulator and the auxiliary circuit that is connected with the output terminal of described low pressure difference linear voltage regulator; Wherein, described auxiliary circuit comprises the first resistance, the first electric capacity and pulls up transistor, one end of described the first resistance is connected with the output terminal of low pressure difference linear voltage regulator, one end of the other end of described the first resistance, the first electric capacity is connected with the grid that pulls up transistor, the described drain electrode that pulls up transistor is connected with the first high level, the described source electrode that pulls up transistor is connected with the output terminal of low pressure difference linear voltage regulator, and the other end of described the first electric capacity is connected with the second high level.
Optionally, described pulling up transistor is nmos pass transistor.
Optionally, the breadth length ratio of the grid of described nmos pass transistor is more than or equal to 100.
Optionally, the threshold voltage of described nmos pass transistor is greater than 0V, less than or equal to 1V.
Optionally, the time constant of the RC oscillatory circuit that forms of described the first resistance, the first electric capacity is more than or equal to the response time of low pressure difference linear voltage regulator.
Optionally, also comprise: the output capacitance that is connected with the output terminal of described low pressure difference linear voltage regulator.
Optionally, described output capacitance is perhaps tantalum electric capacity of ceramic electrical.
Optionally, described voltage difference linear voltage regulator comprises: error amplifier, voltage-reg-ulator tube, the second resistance, the 3rd resistance, and described the second resistance, the 3rd resistance are as feedback network; The reverse input end of described error amplifier is connected with voltage reference signal, the output terminal of described error amplifier is connected with the control end of described voltage-reg-ulator tube, the first end of described voltage-reg-ulator tube is connected with the third high level, the second end of described voltage-reg-ulator tube is connected with an end of the second resistance, one end of the other end of described the second resistance, the 3rd resistance is connected with the positive input of error amplifier, the other end ground connection of described the 3rd resistance; Wherein, described voltage reference signal is as the input signal of low pressure difference linear voltage regulator, and the second end of described voltage-reg-ulator tube is as the output terminal of low pressure difference linear voltage regulator.
Optionally, described voltage-reg-ulator tube is NPN Darlington transistor, NPN pipe, PNP pipe, nmos pass transistor or PMOS transistor.
Optionally, when described voltage-reg-ulator tube is the PMOS transistor, the output terminal of described error amplifier is connected with the transistorized grid of described PMOS, and the transistorized source electrode of described PMOS is connected with the third high level, and the transistorized drain electrode of described PMOS is connected with an end of the second resistance.
Optionally, also comprise: the impact damper between the control end of the output terminal of described error amplifier and described voltage-reg-ulator tube.
Optionally, described impact damper is source follower or cmos buffer device.
Optionally, described error amplifier has thermal-shutdown circuit, overvoltage crowbar, current foldback circuit, under-voltage protecting circuit or wherein one or more of reverse-connection protection circuit.
Optionally, the concrete structure of described error amplifier comprises: a PMOS transistor, the 2nd PMOS transistor, the 3rd PMOS transistor, the transistorized source electrode of the 4th PMOS are connected with supply voltage; The one PMOS transistor, the transistorized grid of the 2nd PMOS are connected with the drain electrode of the transistorized drain electrode of the 2nd PMOS, the second nmos pass transistor, and described the 3rd PMOS transistor, the transistorized grid of the 4th PMOS are connected with the drain electrode of the transistorized drain electrode of the 3rd PMOS, the 3rd nmos pass transistor; The transistorized drain electrode of a described PMOS is connected with drain electrode, the grid of the first nmos pass transistor, the transistorized drain electrode of described the 4th PMOS is connected with the drain electrode of the 4th nmos pass transistor, and the grid of described the first nmos pass transistor and the 4th nmos pass transistor is connected; The grid of described the second nmos pass transistor is connected with voltage reference signal as the reverse input end of error amplifier; The grid of described the 3rd nmos pass transistor is connected with described the second resistance, the 3rd resistance as the positive input of error amplifier; The source ground of described the first nmos pass transistor, the 4th nmos pass transistor, the source electrode of described the second nmos pass transistor, the 3rd nmos pass transistor is connected with an end of current source, and the other end ground connection of described current source.
Compared with prior art, the present invention has the following advantages:
The embodiment of the invention is connected with an auxiliary circuit at the output terminal of described low pressure difference linear voltage regulator, described auxiliary circuit comprises the first resistance, the first electric capacity and pulling up transistor, because described the first resistance, the RC oscillatory circuit that the first electric capacity forms, so that negative pulse occurs and low pressure difference linear voltage regulator when not having enough time to respond when the voltage of the output terminal of low pressure difference linear voltage regulator, utilize described RC oscillatory circuit so that pull up transistor and open, utilize the described voltage that pulls up transistor the output terminal of low pressure difference linear voltage regulator to draw high, so that the voltage drop amplitude of output terminal is less, utilize at last low pressure difference linear voltage regulator again the voltage of output terminal to be reverted to original output voltage.Because the voltage drop amplitude of described output terminal is less, can so that the device cisco unity malfunction of load, can not affect the reliability of circuit in the load.And under normal circumstances, described auxiliary circuit does not need to produce power consumption, can not affect the normal operation of power supply.
Further, the timeconstantτ of the RC oscillatory circuit that described the first resistance, the first electric capacity form is more than or equal to the response time of low pressure difference linear voltage regulator, no matter the response time of low pressure difference linear voltage regulator is long or shorter, in a timeconstantτ, the described grid voltage fall that pulls up transistor is little, so that intermediate voltage output can not descend much yet.Be less than or equal to timeconstantτ when the response time of described low pressure difference linear voltage regulator, intermediate voltage output fall low before, described low pressure difference linear voltage regulator returns to normal output voltage with the voltage of output terminal, can not affect the normal operation of load circuit.
Description of drawings
Fig. 1 is the structural representation of the low differential voltage linear voltage stabilizer circuit of prior art;
Fig. 2 to Fig. 5 is the structural representation of the low differential voltage linear voltage stabilizer circuit of the embodiment of the invention;
Fig. 6 is the variation comparison diagram of voltage of output terminal of the low pressure difference linear voltage regulator of the embodiment of the invention and prior art.
Embodiment
Because when load current became suddenly large, the output terminal of the low differential voltage linear voltage stabilizer circuit of prior art can produce a negative pulse, described negative pulse can make the part of devices cisco unity malfunction, can have a strong impact on the reliability of circuit in the load.Even the output terminal at low pressure difference linear voltage regulator is connected with an output capacitance, owing to being subject to the consideration of technique and cost of manufacture, the electric capacity of described output capacitance is usually less, and the final negative pulse that produces is still larger.
For this reason, the embodiment of the invention provides a kind of low differential voltage linear voltage stabilizer circuit, output terminal at described low pressure difference linear voltage regulator is connected with an auxiliary circuit, described auxiliary circuit comprises the first resistance, the first electric capacity and pulling up transistor, because described the first resistance, the RC oscillatory circuit that the first electric capacity forms, so that negative pulse occurs and low pressure difference linear voltage regulator when not having enough time to respond when the voltage of the output terminal of low pressure difference linear voltage regulator, utilize described RC oscillatory circuit so that pull up transistor and open, utilize described pulling up transistor that the voltage of the output terminal of low pressure difference linear voltage regulator is held, so that the voltage drop amplitude of output terminal is less, utilize at last low pressure difference linear voltage regulator again the voltage of output terminal to be reverted to original output voltage.Because the voltage drop amplitude of described output terminal is less, can so that the device cisco unity malfunction of load, can not affect the reliability of circuit in the load.And under normal circumstances, described auxiliary circuit does not need to produce power consumption, can not affect the normal operation of power supply.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
The embodiment of the invention at first provides a kind of low differential voltage linear voltage stabilizer circuit, please refer to Fig. 2, structural representation for the low differential voltage linear voltage stabilizer circuit of the embodiment of the invention, specifically comprise: low pressure difference linear voltage regulator 110, the output terminal of described low pressure difference linear voltage regulator 110 is connected with an auxiliary circuit 130, described auxiliary circuit 130 comprises the first resistance R 1, the first capacitor C 1 and pull up transistor 135, one end of described the first resistance R 1 is connected with the output end vo ut of low pressure difference linear voltage regulator 110, the other end of described the first resistance R 1, one end of the first capacitor C 1 is connected with 135 the grid of pulling up transistor, described 135 the drain electrode of pulling up transistor is connected with the first high level Vdd1, described 135 the source electrode of pulling up transistor is connected with the output end vo ut of low pressure difference linear voltage regulator 110, the output end vo ut of described low pressure difference linear voltage regulator 110 is connected with load (not shown), and the other end of described the first capacitor C 1 is connected with the second high level Vdd2.
In the present embodiment, the voltage of described the first high level Vdd1 and the second high level Vdd2 equates, all is 6V, and the output voltage of described low pressure difference linear voltage regulator 110 is 3.3V under normal circumstances.The output voltage of described low pressure difference linear voltage regulator is less than the voltage of the first high level Vdd1 and the second high level Vdd2.In other embodiments, the voltage of described the first high level Vdd1 and the second high level Vdd2 also can be unequal, the scope of the voltage of described the first high level Vdd1 and the second high level Vdd2 is 2V～6V, so that when forming negative pulse, the voltage of the output end vo ut of described low pressure difference linear voltage regulator 110 is at least greater than 2V, avoids the brownout of the output end vo ut of low pressure difference linear voltage regulator 110 to affect the stability of the circuit of load.
In the present embodiment, describedly pull up transistor 135 for nmos pass transistor.In the present embodiment, the breadth length ratio of the grid of described nmos pass transistor is more than or equal to 100, and larger breadth length ratio is conducive to accelerate the first high level to the upper pulling rate degree of output end voltage.And the threshold voltage of described nmos pass transistor is greater than 0V and less than or equal to 1V, less threshold voltage is conducive to improve the response time that pulls up transistor, so that the voltage of output end vo ut has just begun to reduce, pull up transistor and to open, thereby utilize the first high level to draw on the voltage of output end vo ut is carried out.
In other embodiments, the breadth length ratio of the grid of described nmos pass transistor also can be less than 100, and the threshold voltage of described nmos pass transistor also can be greater than 1V.
In the present embodiment, the time constant of the RC oscillatory circuit of described the first resistance R 1,1 formation of the first capacitor C is more than or equal to the response time of low pressure difference linear voltage regulator 110.The response time of described low pressure difference linear voltage regulator 110 is the voltage of the output terminal of low pressure difference linear voltage regulator 110 when changing, the time of utilizing described low pressure difference linear voltage regulator 110 that the voltage of output terminal is recovered.The response time of different low pressure difference linear voltage regulators 110 is different, and when the described response time was long, the duration that the voltage of output terminal changes was longer, and the step-down that negative pulse causes is larger, and is easier so that the device cisco unity malfunction.For the response time with low pressure difference linear voltage regulator 110 shortens, need to the circuit of low pressure difference linear voltage regulator 110 be redesigned, increase many devices, so that the circuit of low pressure difference linear voltage regulator 110 is more complicated, power consumption is higher.And utilize the auxiliary circuit of the embodiment of the invention, no matter the response time of low pressure difference linear voltage regulator 110 shorter or longer, can both effectively suppress the output voltage that negative pulse causes to descend, avoid affecting the stability of the circuit of load.
Please refer to Fig. 3, be the electrical block diagram of the low pressure difference linear voltage regulator 110 among Fig. 2, described low pressure difference linear voltage regulator 110 comprises: error amplifier 111, voltage-reg-ulator tube 112, the second resistance R 2, the 3rd resistance R 3; The reverse input end of described error amplifier 111 links to each other with voltage reference signal Vref, the output terminal of described error amplifier 111 is connected with the control end of described voltage-reg-ulator tube 112, the first end of described voltage-reg-ulator tube 112 is connected with third high level Vdd3, the second end of described voltage-reg-ulator tube 112 is connected with an end of the second resistance R 2, one end of the other end of described the second resistance R 2, the 3rd resistance R 3 is connected with the positive input of error amplifier 111, the other end ground connection of described the 3rd resistance R 3; Wherein, described voltage reference signal Vref is as the input signal of low pressure difference linear voltage regulator 110, and the end that the second end of described voltage-reg-ulator tube 112 is connected with the second resistance R 2 is as the output end vo ut of low pressure difference linear voltage regulator; Described the second resistance R 2, the 3rd resistance R 3 consist of feedback network 115, utilize described feedback network the situation of change of the voltage of output end vo ut to be fed back to the positive input of low pressure error amplifier 111 by sampling voltage.
In the present embodiment, please refer to Fig. 4, structural representation for the described error amplifier 111 among Fig. 3, comprise: a PMOS transistor MP1, the 2nd PMOS transistor MP2, the 3rd PMOS transistor MP3, the 4th PMOS transistor MP4, the first nmos pass transistor MN1, the second nmos pass transistor MN2, the 3rd nmos pass transistor MN3, the 4th nmos pass transistor MN4 and current source, the source electrode of a described PMOS transistor MP1, the 2nd PMOS transistor MP2, the 3rd PMOS transistor MP3, the 4th PMOS transistor MP4 is connected with supply voltage; The grid of the one PMOS transistor MP1, the 2nd PMOS transistor MP2 is connected with the drain electrode of the 2nd PMOS transistor MP2, the drain electrode of the second nmos pass transistor MN2, and the grid of described the 3rd PMOS transistor MP3, the 4th PMOS transistor MP4 is connected with the drain electrode of the 3rd PMOS transistor MP3, the drain electrode of the 3rd nmos pass transistor MN3; The drain electrode of a described PMOS transistor MP1 is connected with drain electrode, the grid of the first nmos pass transistor MN1, the drain electrode of described the 4th PMOS transistor MP4 is connected with the drain electrode of the 4th nmos pass transistor MN4, and the grid of the grid of described the first nmos pass transistor MN1 and the 4th nmos pass transistor MN4 is connected; The grid of described the second nmos pass transistor MN2 is connected with voltage reference signal as the reverse input end of error amplifier; The grid of described the 3rd nmos pass transistor MN3 is connected with described feedback network 115 as the positive input of error amplifier; The source ground of the source electrode of described the first nmos pass transistor MN1 and the 4th nmos pass transistor MN4, the source electrode of the source electrode of described the second nmos pass transistor MN2 and the 3rd nmos pass transistor MN3 is connected with an end of current source, and the other end ground connection of described current source.
The sampling voltage that described error amplifier 111 provides described feedback network 115 and the magnitude of voltage of voltage reference signal compare, when both deviation occurs, and after error amplifier 111 amplifies described deviation, the pressure drop of control voltage-reg-ulator tube 112.In the present embodiment, the sampling voltage value that is input to positive input when feedback network 115 reduces, difference between the magnitude of voltage of voltage reference signal Vref and the sampling voltage value of positive input increases, after both differences are amplified through error amplifier 111, the drive current of error amplifier 111 output terminals increases, increase so that be applied to the voltage of the control end of voltage-reg-ulator tube 112, conducting resistance between voltage-reg-ulator tube 112 first ends and the second end reduces, the pressure drop at voltage-reg-ulator tube 112 two ends reduces, thereby so that the voltage of the output terminal of low pressure difference linear voltage regulator 110 raises, return to normal output voltage.
In other embodiments, described error amplifier can also adopt other circuit structure.Because error amplifier is the integrated circuit unit of this area routine, concrete circuit structure is a lot, and therefore not to repeat here.
In the present embodiment, described voltage-reg-ulator tube 112 is the PMOS transistor, the transistorized grid of described PMOS is connected with the output terminal of error amplifier 111, the transistorized source electrode of described PMOS is connected with third high level Vdd3, and the transistorized drain electrode of described PMOS is connected with an end of the second resistance R 2.By controlling the transistorized grid voltage of described PMOS, control the transistorized source of PMOS leakage resistance, thereby control the pressure drop that described PMOS source transistor leaks two ends.
In other embodiments, described voltage-reg-ulator tube can also be NPN Darlington transistor, NPN pipe, PNP pipe, nmos pass transistor.
In the present embodiment, the voltage of described third high level Vdd3 is identical with the voltage of the first high level Vdd1, the second high level Vdd2.In other embodiments, the voltage of described third high level Vdd3 is different from the voltage of the first high level Vdd1, the second high level Vdd2, and the voltage of described third high level Vdd3 is greater than the output voltage of low pressure difference linear voltage regulator 110 output end vo ut under normal circumstances.
In other embodiments, can also have impact damper between the output terminal of described error amplifier and the control end of voltage-reg-ulator tube, the larger over the ground stray capacitance that is used for the grid of the output terminal of isolation error amplifier and voltage-reg-ulator tube, and Slew Rate drives so that described grid capacitance has faster, can improve the response time of low pressure difference linear voltage regulator, thereby reduce overshoot or lose punching.Among embodiment, described impact damper is source follower, cmos buffer device or other suitable impact dampers therein.
In other embodiments, described low pressure difference linear voltage regulator can also have thermal-shutdown circuit, overvoltage crowbar, current foldback circuit, under-voltage protecting circuit or wherein one or more of reverse-connection protection circuit.
In other embodiments, please refer to Fig. 5, can also be connected with output capacitance C at the output terminal 110 of described low pressure difference linear voltage regulator 110
L, described output capacitance C
LHas an equivalent resistance in series R
ESR, utilize described output capacitance C
LElectric current to unexpected increase compensates, thereby reduces negative pulse.Described output capacitance C
LBe ceramic electrical tantalum electric capacity perhaps.
When not forming negative pulse, it is constant that the voltage of the output terminal of described low pressure difference linear voltage regulator 110 keeps, corresponding, described 135 grid voltage and the source voltage of pulling up transistor keeps constant, in the present embodiment, the output voltage of described low pressure difference linear voltage regulator 110 is 3.3V, and the magnitude of voltage of described voltage reference signal Vref equates with the sampling voltage value that feedback network 115 is input to positive input.
When load caused load current to increase suddenly, the voltage that is applied to voltage-reg-ulator tube 112 two ends increased suddenly, so that the voltage of the output end vo ut of low pressure difference linear voltage regulator reduces suddenly, formed negative pulse.Simultaneously, described 135 the source voltage of pulling up transistor reduces suddenly, but because the effect of the RC oscillatory circuit of the first resistor R1,1 formation of the first capacitor C, described 135 the grid voltage of pulling up transistor can't reduce at once, therefore, described 135 the gate source voltage of pulling up transistor becomes large, 135 channel region is opened so that pull up transistor, the voltage of the output terminal of described low pressure difference linear voltage regulator 110 utilize the first high level Vdd1 that the voltage of the output terminal of described low pressure difference linear voltage regulator 110 is boosted, so that only can slightly reduce.And 135 the gate source voltage of ought describedly pulling up transistor diminishes again, when pulling up transistor 135 threshold voltage, described 135 the channel region of pulling up transistor is closed, the first high level Vdd1 does not continue the voltage of the output terminal of described low pressure difference linear voltage regulator 110 is boosted, so that the voltage stabilization of the output terminal of final low pressure difference linear voltage regulator 110 is at an intermediate voltage output, the output end voltage that described intermediate voltage output negative pulse in the prior art causes is until the later use low pressure difference linear voltage regulator returns to original output voltage with the voltage of the output terminal of low pressure difference linear voltage regulator 110 again.The voltage that described intermediate voltage output approximates the second high level Vdd1 deducts 135 the threshold voltage of pulling up transistor.Voltage by controlling described the second high level Vdd1 and 135 the threshold voltage of pulling up transistor, namely can control described intermediate voltage output, so that described intermediate voltage output is far longer than the very little output end voltage that causes because of negative pulse in the prior art, close to original output voltage, guarantee stability and the reliability of power supply and load.And under normal circumstances, pulling up transistor of described auxiliary circuit 135 do not opened, and can not produce extra power consumption, can not affect the normal use of power supply.
In the present embodiment, the timeconstantτ of the RC oscillatory circuit of described the first resistance R 1,2 formation of the first capacitor C is more than or equal to the response time of low pressure difference linear voltage regulator 110.No matter the response time of low pressure difference linear voltage regulator 110 is long or shorter, in a timeconstantτ, described 135 the grid voltage fall of pulling up transistor is little, so that intermediate voltage output can not descend much yet, be less than or equal to timeconstantτ when the response time of described low pressure difference linear voltage regulator, intermediate voltage output fall low before, described low pressure difference linear voltage regulator returns to normal output voltage with the voltage of output terminal, resistance value by adjusting the first resistance R 1 and the capacitance of the first capacitor C 2, the voltage that just can guarantee output terminal can not descend low, can not impact load circuit.And because the response time of low pressure difference linear voltage regulator 110 is generally tens microseconds to the hundreds of microsecond, the capacitance of described the first capacitor C 2 is usually less, the order of magnitude is generally nanofarad or pico farad rank, and the order of magnitude of the output capacitance of prior art is generally the microfarad rank, therefore the shared chip area of described auxiliary circuit is very little, and cost is lower.
Please refer to Fig. 6, be the variation comparison diagram of the voltage of the output terminal of the low pressure difference linear voltage regulator of the embodiment of the invention and prior art, horizontal ordinate is the time, and ordinate is the magnitude of voltage of output terminal.Time point at T1, the voltage of the output terminal of described low pressure difference linear voltage regulator is owing to the impact of load reduces suddenly, time point at T2, utilize described low pressure difference linear voltage regulator that the magnitude of voltage of output terminal is reverted to original output voltage again, time between described T1 and the T2 is the response time of low pressure difference linear voltage regulator, and dotted line represents to cause because of negative pulse in the prior art situation of change of the magnitude of voltage of output terminal, and what solid line represented the embodiment of the invention causes the situation of change of the magnitude of voltage of output terminal because of negative pulse.Because the unlatching meeting that pulls up transistor so that the first high level Vdd1 the voltage of output terminal is drawn high, thereby form a more stable intermediate voltage output, described intermediate voltage output is far longer than the voltage of the very little output terminal that causes because of negative pulse in the prior art, guarantees stability and the reliability of power supply and load.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection domain of technical solution of the present invention according to technical spirit of the present invention.
Claims (14)
1. a low differential voltage linear voltage stabilizer circuit is characterized in that, comprising:
Low pressure difference linear voltage regulator and the auxiliary circuit that is connected with the output terminal of described low pressure difference linear voltage regulator;
Wherein, described auxiliary circuit comprises the first resistance, the first electric capacity and pulls up transistor, one end of described the first resistance is connected with the output terminal of low pressure difference linear voltage regulator, one end of the other end of described the first resistance, the first electric capacity is connected with the grid that pulls up transistor, the described drain electrode that pulls up transistor is connected with the first high level, the described source electrode that pulls up transistor is connected with the output terminal of low pressure difference linear voltage regulator, and the other end of described the first electric capacity is connected with the second high level.
2. low differential voltage linear voltage stabilizer circuit as claimed in claim 1 is characterized in that, described pulling up transistor is nmos pass transistor.
3. low differential voltage linear voltage stabilizer circuit as claimed in claim 2 is characterized in that, the breadth length ratio of the grid of described nmos pass transistor is more than or equal to 100.
4. low differential voltage linear voltage stabilizer circuit as claimed in claim 2 is characterized in that, the threshold voltage of described nmos pass transistor is greater than 0V, and less than or equal to 1V.
5. low differential voltage linear voltage stabilizer circuit as claimed in claim 1 is characterized in that, the time constant of the RC oscillatory circuit that described the first resistance, the first electric capacity form is more than or equal to the response time of described low pressure difference linear voltage regulator.
6. low differential voltage linear voltage stabilizer circuit as claimed in claim 1 is characterized in that, also comprises: the output capacitance that is connected with the output terminal of described low pressure difference linear voltage regulator.
7. low differential voltage linear voltage stabilizer circuit as claimed in claim 6 is characterized in that, described output capacitance is perhaps tantalum electric capacity of ceramic electrical.
8. low differential voltage linear voltage stabilizer circuit as claimed in claim 1 is characterized in that, described low pressure difference linear voltage regulator comprises: error amplifier, voltage-reg-ulator tube, the second resistance, the 3rd resistance, and described the second resistance, the 3rd resistance are as feedback network; The reverse input end of described error amplifier is connected with voltage reference signal, the output terminal of described error amplifier is connected with the control end of described voltage-reg-ulator tube, the first end of described voltage-reg-ulator tube is connected with the third high level, the second end of described voltage-reg-ulator tube is connected with an end of the second resistance, one end of the other end of described the second resistance, the 3rd resistance is connected with the positive input of error amplifier, the other end ground connection of described the 3rd resistance; Wherein, described voltage reference signal is as the input signal of low pressure difference linear voltage regulator, and the second end of described voltage-reg-ulator tube is as the output terminal of low pressure difference linear voltage regulator.
9. low differential voltage linear voltage stabilizer circuit as claimed in claim 8 is characterized in that, described voltage-reg-ulator tube is NPN Darlington transistor, NPN pipe, PNP pipe, nmos pass transistor or PMOS transistor.
10. low differential voltage linear voltage stabilizer circuit as claimed in claim 9, it is characterized in that, when described voltage-reg-ulator tube is the PMOS transistor, the output terminal of described error amplifier is connected with the transistorized grid of described PMOS, the transistorized source electrode of described PMOS is connected with the third high level, and the transistorized drain electrode of described PMOS is connected with an end of the second resistance.
11. low differential voltage linear voltage stabilizer circuit as claimed in claim 8 is characterized in that, also comprises: the impact damper between the control end of the output terminal of described error amplifier and described voltage-reg-ulator tube.
12. low differential voltage linear voltage stabilizer circuit as claimed in claim 11 is characterized in that, described impact damper is source follower or cmos buffer device.
13. low differential voltage linear voltage stabilizer circuit as claimed in claim 8 is characterized in that, described error amplifier has thermal-shutdown circuit, overvoltage crowbar, current foldback circuit, under-voltage protecting circuit or wherein one or more of reverse-connection protection circuit.
14. low differential voltage linear voltage stabilizer circuit as claimed in claim 8, it is characterized in that, the concrete structure of described error amplifier comprises: a PMOS transistor MP1, the 2nd PMOS transistor MP2, the 3rd PMOS transistor MP3, the 4th PMOS transistor MP4, the first nmos pass transistor MN1, the second nmos pass transistor MN2, the 3rd nmos pass transistor MN3, the 4th nmos pass transistor MN4 and current source, and a described PMOS transistor, the 2nd PMOS transistor, the 3rd PMOS transistor, the transistorized source electrode of the 4th PMOS are connected with supply voltage; The one PMOS transistor, the transistorized grid of the 2nd PMOS are connected with the drain electrode of the transistorized drain electrode of the 2nd PMOS, the second nmos pass transistor, and described the 3rd PMOS transistor, the transistorized grid of the 4th PMOS are connected with the drain electrode of the transistorized drain electrode of the 3rd PMOS, the 3rd nmos pass transistor; The transistorized drain electrode of a described PMOS is connected with drain electrode, the grid of the first nmos pass transistor, the transistorized drain electrode of described the 4th PMOS is connected with the drain electrode of the 4th nmos pass transistor, and the grid of described the first nmos pass transistor and the 4th nmos pass transistor is connected; The grid of described the second nmos pass transistor is connected with voltage reference signal as the reverse input end of error amplifier; The grid of described the 3rd nmos pass transistor is connected with described the second resistance, the 3rd resistance as the positive input of error amplifier; The source ground of described the first nmos pass transistor, the 4th nmos pass transistor, the source electrode of described the second nmos pass transistor, the 3rd nmos pass transistor is connected with an end of current source, and the other end ground connection of described current source.
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| CN103970176A (en) * | 2014-05-26 | 2014-08-06 | 万高(杭州)科技有限公司 | Low-dropout linear voltage-stabilizing circuit and application system thereof |
| CN104020811A (en) * | 2014-06-11 | 2014-09-03 | 深圳市威益德科技有限公司 | Multi-channel voltage regulator circuit |
| CN105652945A (en) * | 2016-04-01 | 2016-06-08 | 电子科技大学 | Low dropout regulator |
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| CN110308756A (en) * | 2018-03-27 | 2019-10-08 | 艾普凌科有限公司 | Voltage regulator |
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| CN108616260A (en) * | 2018-04-02 | 2018-10-02 | 广州慧智微电子有限公司 | A kind of power circuit of power amplifier |
| CN108616260B (en) * | 2018-04-02 | 2022-05-10 | 广州慧智微电子股份有限公司 | Power supply circuit of power amplifier |
| CN111831046A (en) * | 2019-04-16 | 2020-10-27 | 联咏科技股份有限公司 | Output stage circuit and voltage stabilizer thereof |
| CN112667018A (en) * | 2020-12-14 | 2021-04-16 | 思瑞浦微电子科技（苏州）股份有限公司 | Power supply electrifying overshoot-prevention circuit based on LDO (Low dropout regulator) |
| CN113342115A (en) * | 2021-06-30 | 2021-09-03 | 上海料聚微电子有限公司 | LDO circuit |
| CN114740939A (en) * | 2022-04-19 | 2022-07-12 | 海光信息技术股份有限公司 | Power generation circuit, chip and voltage detection and compensation method |
| CN114740939B (en) * | 2022-04-19 | 2024-01-19 | 海光信息技术股份有限公司 | Power supply generating circuit, chip and voltage detecting and compensating method |
| CN117270619A (en) * | 2023-11-17 | 2023-12-22 | 苏州贝克微电子股份有限公司 | Circuit structure for improving stability of output voltage |
| CN117270619B (en) * | 2023-11-17 | 2024-02-09 | 苏州贝克微电子股份有限公司 | Circuit structure for improving stability of output voltage |
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