CN103001586A - Broadband two-channel digital down converter - Google Patents
Broadband two-channel digital down converter Download PDFInfo
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- CN103001586A CN103001586A CN201210534676XA CN201210534676A CN103001586A CN 103001586 A CN103001586 A CN 103001586A CN 201210534676X A CN201210534676X A CN 201210534676XA CN 201210534676 A CN201210534676 A CN 201210534676A CN 103001586 A CN103001586 A CN 103001586A
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Abstract
The invention discloses a broadband two-channel digital down converter which comprises an analog-to-digital (A/D) digital acquisition module, an interface control module, a frequency mixing and filer input control module and a parallel filter module. The modules are sequentially connected with one another on the basis of a field programmable gate array (FPGA) platform; and the A/D digital acquisition module acquires high frequency digital signals by means of a two-channel work mode, the high frequency digital signals are respectively subjected to first underclocking through the A/D digital acquisition module, an FPGA transceiving interface is configured by the frequency mixing and filer input control module, the signals are subjected to second underclocking through FPGA, each channel produces 16 ways of final frequency signals with frequencies accounting for 1/16 of those of original signals, then the 16 ways of signals of each channel are subjected to phase demodulation and extraction through the frequency mixing and filer input control module, and finally, parallel filtering is performed by means of the parallel filter module. By means of the broadband two-channel digital down converter, problems of strict bandwidth limitation, low data transmission rates and poor real-time performances of digital signal processing in broadband radar signal digital down converter design are solved.
Description
Technical field
The present invention relates to Radar Signal Processing System, particularly the Digital Down Convert of broadband signal is processed in the Radar Signal Processing of employing wideband phased array radar, sophisticated signal waveform, High Data Rate.
Background technology
Development along with Radar Technology and signal processing theory, modern radar mostly adopts the phase array system, its signal waveform and signal processing method become increasingly complex, and signal bandwidth is increasing, and it is also more and more higher to need data transfer rate to be processed and data to process requirement of real-time.And each wideband radar product signal processing subsystem all will be equipped with a Digital Down Converter Module, as the important component part of wideband radar product signal processor.
Classical mixing, phase demodulation and filtering principle are adopted in the at present development of Radar Products digital down converter substantially, use serial structure that the Digital Down Convert algorithm is carried out Direct Programming and realize that there are several large shortcomings in this definite method:
1. calculation of complex does not add screening to sample frequency, so that the frequency mixer coefficient value that uses in the optical mixing process without particularity, causes the computational process of whole mixing loaded down with trivial details, has affected precision and real-time that data are processed;
2. data transfer rate is low, the filter structure of serial is so that the digital down converter maximum operating frequency can't break through hardware constraints, limit the processing speed of digital signal without the optical mixing process of sample frequency screening, caused whole digital down conversion system can't realize large data rate transmission and processing;
3. real-time is poor, and data handling procedure is tediously long and processing speed low so that system is difficult to requirement of real time;
4. radar signal Bandwidth-Constrained, Digital Signal Processing speed can't satisfy the High Data Rate requirement of wideband radar digital signal, has limited the performance index of radar bandwidth.
Summary of the invention
In order to address the above problem, the invention provides a kind of broadband two-channel digital low-converter, comprise connecting successively based on the FPGA platform:
The A/D acquisition module carries out signals collecting to an initialize signal, is converted into high-frequency digital signal, and this high-frequency digital signal is made down conversion process, forms the first frequency digital signal;
Interface control module is received and dispatched at a high speed interface with described FPGA and is communicated, and described first frequency digital signal is sent into FPGA, and described first frequency digital signal is carried out again down conversion process in described FPGA, forms the second frequency digital signal;
Mixing and filter input control module carry out respectively I/Q phase demodulation, Frequency mixing processing and I/Q two ways of digital signals to described second frequency digital signal and extract; And
The parallel filtering module is carried out low-pass filtering to the second frequency signal after the settling signal extraction.
Preferably, described A/D acquisition module adopts the binary channels mode of operation, and described binary channels respectively produces four tunnel parallel first frequency digital signals, the frequency of described first frequency digital signal be described high-frequency digital signal frequency 1/4.
Preferably, described FPGA finishes the frequency reducing of described first frequency digital signal by string and conversion and FIFO read-write, and described binary channels produces respectively 1/4 the second frequency digital signal that 16 tunnel frequencies are described first frequency digital signal.
Preferably, to I road and the Q road signal extraction of the second frequency digital signal after each passage mixing, each passage is exported 8 road I railway digital signals and 8 road Q railway digital signals respectively for described mixing and filter input control module.
Preferably, described mixing and filter input control module are finished input control to the parallel filtering module by the register integral shift of one 8 signal word lengths.
Preferably, described parallelism wave filter improves its throughput efficiency and clock frequency by the FIR filter by multi-stage pipeline.
Preferably, the frequency of described high-frequency signal is 5GHz.
Compared with prior art, beneficial effect of the present invention is as follows:
Realized that by general-purpose platform frequency is up to the Digital Down Convert processing of the digital signal of 5GHz, the invention solves the problems such as limit bandwidth is strict in the design of wideband radar signal digital low-converter, message transmission rate is low, the Digital Signal Processing real-time is poor.
Certainly, implement arbitrary product of the present invention and might not need to reach simultaneously above-described all advantages.
Description of drawings
Fig. 1 is the workflow diagram of broadband provided by the invention two-channel digital low-converter.
Embodiment
The invention provides as shown in Figure 1 a kind of broadband two-channel digital low-converter, comprise connecting successively based on the FPGA platform:
The A/D acquisition module carries out signals collecting to an initialize signal, is converted into high-frequency digital signal, and this high-frequency digital signal is made down conversion process, forms the first frequency digital signal;
Interface control module is received and dispatched at a high speed interface with described FPGA and is communicated, and described first frequency digital signal is sent into FPGA, and described first frequency digital signal is carried out again down conversion process in described FPGA, forms the second frequency digital signal;
Mixing and filter input control module carry out respectively I/Q phase demodulation, Frequency mixing processing and I/Q two ways of digital signals to described second frequency digital signal and extract; And
The parallel filtering module is carried out low-pass filtering to the second frequency signal after the settling signal extraction.
Thought of the present invention is: the present invention is by utilizing the collection of A/D digital collection module to adopt the binary channels mode of operation to obtain high-frequency digital signal, each passage has high-frequency digital signal, twin-channel high-frequency digital signal passes through respectively the frequency reducing first time of A/D digital collection module, FPGA transmitting-receiving interface signal after mixing and the configuration of filter input control module carries out the frequency reducing second time by FPGA, twice frequency reducing is reduced to respectively 1/4 of primary frequency, last each passage produces 1/16 the final frequency signal that 16 tunnel frequencies are original signal, then by mixing and filter input control module 16 road signal phase demodulations to each passage, extract, and finally by parallel filtering module parallel filtering, so far finished the whole process of frequency conversion.
Below only illustrate, can not limit to composition of the present invention and function.
Application examples:
The present invention gathers the wideband radar echo data by the A/D data acquisition module that adopts the binary channels mode of operation by its A/D capture card, in should use-case, the A/D data acquisition module is converted to the high-frequency digital signal that frequency is 5GHz with the wideband radar echo data, this high-frequency digital signal is through a frequency reducing, two passages are 1/4 first frequency digital signal of high-frequency digital signal frequency by 4 tunnel parallel frequencies respectively, are 1.25GHz in this first frequency digital signal frequency;
Finish communicating by letter of A/D data acquisition module and fpga chip High Speed I/O by interface control module configuration by disposing its SPI interface register again, finish the down conversion process of each passage 4 road first frequency digital signal by FPGA string and conversion and FIFO read-write operation, exporting 16 tunnel frequencies is the second frequency digital signal of 312.5MHz, the mode of operation of each passage wherein, gain, biasing, differ with parameters such as input impedance and can pass through SPI serial line interface programming Control and adjustment, phase place when guaranteeing four passage interlaced samplings of monolithic, gain, the consistency of side-play amount;
Mixing and filter input control module are by the data flow of the parallel input of control, 16 road second frequency digital signals to each passage input are carried out mixing and I/Q phase demodulation, finish simultaneously the once extraction of I/Q two paths of signals and export 8 road I road signals and 8 road Q road signals, the input control to 8 parallel filtering modules calling is finished in the integral shift operation by 8 signal word lengths.
The parallel filtering module, by the structure of streamline the digital signal of parallel input being carried out FIR filtering processes, pipeline organization has improved data throughput and the clock frequency of digital signal down variable frequency device, each clock is finished the parallel filtering of 8 supplied with digital signal, maximum clock frequency is 328MHz, and can finish frequency is the filter task of the second frequency signal of 312.5MHz.
The invention provides a kind of digital down converter that is common to the wideband radar product, owing to take above-mentioned technical scheme, adopt conventional general device to build general-purpose platform, realized that by general-purpose platform frequency is up to the Digital Down Convert processing of the digital signal of 5GHz.The present invention can be used for the Digital Down Convert of wideband radar product signal treatment system and processes, and further research has great importance and purposes.The invention solves the problems such as limit bandwidth is strict in the design of wideband radar signal digital low-converter, message transmission rate is low, the Digital Signal Processing real-time is poor.
More than the disclosed preferred embodiment of the present invention just be used for helping to set forth the present invention.Preferred embodiment does not have all details of detailed descriptionthe, does not limit this invention yet and only is described embodiment.Obviously, according to the content of this specification, can make many modifications and variations.These embodiment are chosen and specifically described to this specification, is in order to explain better principle of the present invention and practical application, thereby the technical field technical staff can understand and utilize the present invention well under making.The present invention only is subjected to the restriction of claims and four corner and equivalent.
Claims (7)
1. a broadband two-channel digital low-converter is characterized in that, comprises connecting successively based on the FPGA platform:
The A/D acquisition module carries out signals collecting to an initialize signal, is converted into high-frequency digital signal, and this high-frequency digital signal is made down conversion process, forms the first frequency digital signal;
Interface control module is received and dispatched at a high speed interface with described FPGA and is communicated, and described first frequency digital signal is sent into FPGA, and described first frequency digital signal is carried out again down conversion process in described FPGA, forms the second frequency digital signal;
Mixing and filter input control module carry out respectively I/Q phase demodulation, Frequency mixing processing and I/Q two ways of digital signals to described second frequency digital signal and extract; And
The parallel filtering module is carried out low-pass filtering to the second frequency signal after the settling signal extraction.
2. broadband as claimed in claim 1 two-channel digital low-converter, it is characterized in that, described A/D acquisition module adopts the binary channels mode of operation, described binary channels respectively produces four tunnel parallel described first frequency digital signals, the frequency of described first frequency digital signal be described high-frequency digital signal frequency 1/4.
3. broadband as claimed in claim 1 two-channel digital low-converter, it is characterized in that, described FPGA finishes the frequency reducing of described first frequency digital signal by string and conversion and FIFO read-write, and described binary channels produces respectively 1/4 the described second frequency digital signal that 16 tunnel frequencies are described first frequency digital signal.
4. broadband as claimed in claim 1 two-channel digital low-converter, it is characterized in that, to I road and the Q road signal extraction of the described second frequency digital signal after each passage mixing, each passage is exported 8 road I railway digital signals and 8 road Q railway digital signals respectively for described mixing and filter input control module.
5. broadband as claimed in claim 1 two-channel digital low-converter is characterized in that, described mixing and filter input control module are finished input control to the parallel filtering module by the register integral shift of one 8 signal word lengths.
6. broadband as claimed in claim 1 two-channel digital low-converter is characterized in that described parallelism wave filter improves its throughput efficiency and clock frequency by the FIR filter by multi-stage pipeline.
7. broadband as claimed in claim 1 two-channel digital low-converter is characterized in that the frequency of described high-frequency signal is 5GHz.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107659272A (en) * | 2017-09-21 | 2018-02-02 | 天津光电通信技术有限公司 | A kind of new up-converter circuit |
| CN110007122A (en) * | 2018-01-05 | 2019-07-12 | 罗德施瓦兹两合股份有限公司 | For the signal evaluation circuit and method of oscillograph to be arranged automatically |
| CN112104382A (en) * | 2020-09-10 | 2020-12-18 | 中国电子科技集团公司第五十八研究所 | Parallel digital down-conversion processing system based on digital signals |
| CN113114166A (en) * | 2021-03-12 | 2021-07-13 | 成都辰天信息科技有限公司 | High-speed parallel DDC (direct digital control) and FIR (finite impulse response) filtering processing method based on FPGA (field programmable Gate array) |
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| CN101610095A (en) * | 2009-05-12 | 2009-12-23 | 北京航空航天大学 | A kind of ultra-wideband radio frequency digital receiver device and its implementation based on FPGA |
| CN101621301A (en) * | 2009-07-27 | 2010-01-06 | 重庆华伟工业（集团）有限责任公司 | Broadband digital monitoring receiver |
| CN101707473A (en) * | 2009-09-25 | 2010-05-12 | 中国科学院上海天文台 | GHz ultra wide band digital down converter method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107659272A (en) * | 2017-09-21 | 2018-02-02 | 天津光电通信技术有限公司 | A kind of new up-converter circuit |
| CN110007122A (en) * | 2018-01-05 | 2019-07-12 | 罗德施瓦兹两合股份有限公司 | For the signal evaluation circuit and method of oscillograph to be arranged automatically |
| CN112104382A (en) * | 2020-09-10 | 2020-12-18 | 中国电子科技集团公司第五十八研究所 | Parallel digital down-conversion processing system based on digital signals |
| CN113114166A (en) * | 2021-03-12 | 2021-07-13 | 成都辰天信息科技有限公司 | High-speed parallel DDC (direct digital control) and FIR (finite impulse response) filtering processing method based on FPGA (field programmable Gate array) |
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