CN103001205A - Electrostatic protection circuit applied to power supply pin - Google Patents
Electrostatic protection circuit applied to power supply pin Download PDFInfo
- Publication number
- CN103001205A CN103001205A CN2012104318847A CN201210431884A CN103001205A CN 103001205 A CN103001205 A CN 103001205A CN 2012104318847 A CN2012104318847 A CN 2012104318847A CN 201210431884 A CN201210431884 A CN 201210431884A CN 103001205 A CN103001205 A CN 103001205A
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- Prior art keywords
- electrostatic
- circuit
- power supply
- supply pin
- electrostatic discharge
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses an electrostatic protection circuit applied to a power supply pin. The circuit controls instantaneous conduction of an MOS (metal oxide semiconductor) field-effect transistor by response characteristics of an RC (resistor-capacitor) circuit to electrostatic pulse, an electrostatic discharge closed circuit to ground is closed, electrostatic discharge time can be controlled by adjusting values of RC, the electrostatic discharge closed circuit can be opened after the time to complete electrostatic discharge, and accordingly the power supply pin is protected from electrostatic damage.
Description
Technical field
The present invention relates generally to the ESD Circuits Design for High field, refers in particular to a kind of electrostatic discharge protective circuit that is applied to power pin.
Background technology
Integrated circuit (IC) chip must have electrostatic leakage (ESD:electrostatic discharge) problem with the interface in the external world.When the electrified body of a high potential touched the outer pin of circuit, the electrostatic leakage phenomenon will occur.Since chip each to input or output the electric capacity of pin very little, so the voltage that ESD produces is very large, the device on the possible defective chip causes chip failure.
In order to alleviate the problem of ESD, chip I/O can adopt esd protection circuit usually, normally with the external charge Clamping to VDD or GND, thereby limited the voltage that is added on the chip internal circuit.Because the circuit structure of ESD itself is different, has also introduced some serious problems in protective circuit, first esd protection circuit has reduced the matching degree of operating rate and circuit input/output port at node sizable electric capacity of introducing over the ground and between VDD; It two is that the ESD device can be with the input of the noise coupling on the VDD-to-VSS signal to circuit, thereby has affected the quality of signal; If three to be that the ESD circuit designs improper for it, may cause when electrostatic leakage, causing cmos circuit generation latch-up.
Summary of the invention
The problem to be solved in the present invention just is: the technical problem for prior art exists proposes a kind of electrostatic discharge protective circuit that is applied to power pin.
The solution that the present invention proposes is: this circuit is by the response characteristic of RC circuit to electrostatic pulse; the instantaneous conducting of control metal-oxide-semiconductor; open electrostatic leakage path over the ground; the value of regulating RC can be controlled the time t of electrostatic leakage; t after the time electrostatic leakage path can turn-off; finish electrostatic leakage, the protection power source pin is not subjected to electrostatic damage.
Description of drawings
Fig. 1 is circuit theory schematic diagram of the present invention;
Embodiment
Below with reference to accompanying drawing and implementation the present invention is described in further details.
As shown in Figure 1, suppose that static is a step signal U
s, suppose metal-oxide-semiconductor M
1, M
2, M
3, M
4Corresponding threshold voltage is respectively V
TH1, V
TH2, V
TH3And V
TH4, grid voltage is respectively V
G1, V
G2, V
G3And V
G4, then PMOS manages M
1Grid voltage V
G1Can be expressed as
Wherein t represents the time, and τ is time constant, i.e. τ=R
1C
1According to be (1) as can be known, V
G1Along with the variation of time, namely magnitude of voltage increases gradually from 0, when the time is tending towards infinity, and V
G1=U
s, namely PMOS manages M
1Have from being opened to the process of shutoff, its critical condition namely
U
s-V
G1(t
1)=|V
TH1| (2)
Namely
Namely
As time t ∈ (0, t
1) time, PMOS manages M
1Open, suppose that its leakage current is I
D1, because V
G1, V
G2All at temporal evolution, so I
D1Also be temporal evolution, in like manner PMOS manages M
2Also have from being opened to the process of shutoff, if with M
1Consider that as perfect switch then its critical condition is
U
s-V
G2(t
2)=|V
TH2| (5)
As time t ∈ (0, t
2) time, PMOS manages M
2Can open bias voltage VB〉V
TH3, NMOS manages M
3Be in conducting state always, but because M
2Breadth length ratio (W/L) much larger than M
3Breadth length ratio (W/L) so that this moment V
G4Be high level, NMOS pipe M4 conducting, static passes through M
4GND releases; Behind the electrostatic leakage, i.e. t ∈ (t
2, in the time of ∞), M
1, M
2Turn-off in the capital, and NMOS pipe M
3Conducting is so that V
G4Be low level, M
4Turn-off, ESD finishes.Occurrence that it should be noted that R, C need to be according to actual conditions and applied environment setting, and NMOS manages M
4Size need to determine in conjunction with ESD electric current and technological parameter.
In sum, this circuit is by the response characteristic of RC circuit to electrostatic pulse, and the instantaneous conducting of control metal-oxide-semiconductor has realized electrostatic leakage, has protected power pin not to be subjected to electrostatic damage.
Claims (1)
1. electrostatic discharge protective circuit that is applied to power pin is characterized in that:
Power pin signal VDD is connected to resistance R
1, PMOS manages M
1Source electrode and NMOS pipe M
4Drain electrode; Earth signal GND is connected to capacitor C
1, capacitor C
2, NMOS manages M
3Source electrode and NMOS pipe M
4Source electrode; Resistance R
1The other end is connected to PMOS pipe M
1Grid and capacitor C
1An end, resistance R
2An end be connected to PMOS pipe M
1Drain electrode and PMOS pipe M
2Source electrode, the other end is connected to capacitor C
2With PMOS pipe M
2Grid; NMOS manages M
3Grid meets offset signal VB; NMOS manages M
4Grid be connected to PMOS pipe M
2With NMOS pipe M
3Drain electrode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2012104318847A CN103001205A (en) | 2012-11-02 | 2012-11-02 | Electrostatic protection circuit applied to power supply pin |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2012104318847A CN103001205A (en) | 2012-11-02 | 2012-11-02 | Electrostatic protection circuit applied to power supply pin |
Publications (1)
Publication Number | Publication Date |
---|---|
CN103001205A true CN103001205A (en) | 2013-03-27 |
Family
ID=47929476
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2012104318847A Pending CN103001205A (en) | 2012-11-02 | 2012-11-02 | Electrostatic protection circuit applied to power supply pin |
Country Status (1)
Country | Link |
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CN (1) | CN103001205A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104392984A (en) * | 2014-12-12 | 2015-03-04 | 长沙景嘉微电子股份有限公司 | Electrostatic protection circuit applied to power pin |
CN109314388A (en) * | 2018-09-13 | 2019-02-05 | 深圳市汇顶科技股份有限公司 | Circuit for electrostatic discharge (ESD) protection and IC chip |
CN110187260A (en) * | 2019-06-11 | 2019-08-30 | 珠海市一微半导体有限公司 | A kind of automatic testing method based on ESD circuit integrality |
WO2021180120A1 (en) * | 2020-03-12 | 2021-09-16 | 长鑫存储技术有限公司 | Electrostatic protection circuit, integrated circuit, and electrostatic discharge method |
WO2023077625A1 (en) * | 2021-11-04 | 2023-05-11 | 长鑫存储技术有限公司 | Electrostatic protection circuit for chip |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7394638B2 (en) * | 2003-12-26 | 2008-07-01 | Stmicroelectronics Pvt. Ltd. | System and method for a whole-chip electrostatic discharge protection that is independent of relative supply rail voltages and supply sequencing |
US7626790B2 (en) * | 2007-10-05 | 2009-12-01 | Smartech Worldwide Limited | Electrostatic discharge protection for a circuit capable of handling high input voltage |
CN101640411A (en) * | 2009-09-07 | 2010-02-03 | 北京时代民芯科技有限公司 | Dual-channel electrostatic discharge protecting circuit based on RC-triggering |
CN102185305A (en) * | 2011-05-18 | 2011-09-14 | 北京大学 | High-reliability power supply clamping ESD (Electronic Static Discharge) protection circuit |
-
2012
- 2012-11-02 CN CN2012104318847A patent/CN103001205A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7394638B2 (en) * | 2003-12-26 | 2008-07-01 | Stmicroelectronics Pvt. Ltd. | System and method for a whole-chip electrostatic discharge protection that is independent of relative supply rail voltages and supply sequencing |
US7626790B2 (en) * | 2007-10-05 | 2009-12-01 | Smartech Worldwide Limited | Electrostatic discharge protection for a circuit capable of handling high input voltage |
CN101640411A (en) * | 2009-09-07 | 2010-02-03 | 北京时代民芯科技有限公司 | Dual-channel electrostatic discharge protecting circuit based on RC-triggering |
CN102185305A (en) * | 2011-05-18 | 2011-09-14 | 北京大学 | High-reliability power supply clamping ESD (Electronic Static Discharge) protection circuit |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104392984A (en) * | 2014-12-12 | 2015-03-04 | 长沙景嘉微电子股份有限公司 | Electrostatic protection circuit applied to power pin |
CN104392984B (en) * | 2014-12-12 | 2017-05-31 | 长沙景嘉微电子股份有限公司 | A kind of electrostatic discharge protective circuit for being applied to power pin |
CN109314388A (en) * | 2018-09-13 | 2019-02-05 | 深圳市汇顶科技股份有限公司 | Circuit for electrostatic discharge (ESD) protection and IC chip |
CN110187260A (en) * | 2019-06-11 | 2019-08-30 | 珠海市一微半导体有限公司 | A kind of automatic testing method based on ESD circuit integrality |
CN110187260B (en) * | 2019-06-11 | 2021-04-02 | 珠海市一微半导体有限公司 | Automatic detection method based on ESD circuit integrity |
WO2021180120A1 (en) * | 2020-03-12 | 2021-09-16 | 长鑫存储技术有限公司 | Electrostatic protection circuit, integrated circuit, and electrostatic discharge method |
US11721688B2 (en) | 2020-03-12 | 2023-08-08 | Changxin Memory Technologies, Inc. | Electrostatic protection circuit, integrated circuit and electrostatic discharge method |
WO2023077625A1 (en) * | 2021-11-04 | 2023-05-11 | 长鑫存储技术有限公司 | Electrostatic protection circuit for chip |
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Application publication date: 20130327 |