CN106899011A - Electrostatic discharge protective circuit - Google Patents
Electrostatic discharge protective circuit Download PDFInfo
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- CN106899011A CN106899011A CN201510974300.4A CN201510974300A CN106899011A CN 106899011 A CN106899011 A CN 106899011A CN 201510974300 A CN201510974300 A CN 201510974300A CN 106899011 A CN106899011 A CN 106899011A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
- H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
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- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The present invention provides a kind of electrostatic discharge protective circuit, including：Discharge circuit, bleeder circuit, control circuit, isolation and transmission circuit and functional circuit.In the present invention, when input produces electrostatic pulse, the voltage of the first power line that bleeder circuit produces electrostatic pulse carries out partial pressure, so that Section Point exports a less voltage to control circuit, first delay circuit causes that electrostatic pulse postpones transmission, and now, the low potential of the 3rd node and the high potential of fourth node cause that isolation and transmission circuit is closed, so as to the voltage of electrostatic pulse is not transmitted to functional circuit.Afterwards, the high potential of the 3rd node and the low potential of fourth node cause that isolation and transmission circuit is opened so that functional circuit normal work.In the present invention, in the stage that electrostatic pulse rises, it is to avoid the high voltage of electrostatic pulse is transferred to functional circuit, so that defencive function circuit.
Description
Technical field
The present invention relates to IC design technical field, more particularly to a kind of electrostatic discharge protective circuit.
Background technology
Integrated circuit is in manufacture, assembling and test or in final application, it is easy to the influence of the static discharge (ESD) of the generation being subjected to during manufacture or use, so that integrated circuit is damaged by electrostatic.
Electrostatic discharge protective circuit of the prior art is with reference to shown in Fig. 1, including PMOS transistor P1, nmos pass transistor N1 and functional circuit 1, is a negative circuit in functional circuit 1, including the source electrode of PMOS P2 and NMOS tube N2, PMOS P1 connects power line VDD.When electrostatic pulse is produced on input IN, electrostatic pulse can be by the voltage high of power line VDDH, PMOS P1 and NMOS tube N1 is closed, the voltage of power line VDDH is discharged into ground wire VSS by the electric leakage of PMOS P1 and NMOS tube N1, the voltage of node O slowly rises, and less than the voltage of power line VDDH so that power line VDDH with less control source to functional unit 1 in, it is to avoid the grid oxic horizon of PMOS P2 and NMOS tube N2 is punctured due to overtension.But; the output circuit of PMOS P1 and NMOS tube N1 equally exists the phenomenon for puncturing in electrostatic discharge protective circuit of the prior art; with the rising of the voltage of VDDH; the voltage of node O is first slow to be raised; when the voltage of VDDH reaches a certain magnitude of voltage, the voltage of node O can rise rapidly, so that the output circuit of PMOS P1 and NMOS tube N1 punctures; when the breakdown voltage of grid oxic horizon of the magnitude of voltage more than PMOS P2 and NMOS tube N2, then grid oxic horizon can be punctured.
The content of the invention
It is an object of the present invention to provide a kind of electrostatic discharge protective circuit, it is to avoid the grid oxic horizon in functional circuit is breakdown due to electrostatic pulse.
In order to solve the above technical problems, the present invention provides a kind of electrostatic discharge protective circuit, including；
Discharge circuit, the discharge circuit includes the first onunit and the second onunit, first onunit is connected in first node with second onunit, the first node connects an input, first onunit and connects the first power line, and second onunit connects second source line；
Bleeder circuit, the bleeder circuit includes the first partial pressure unit and the second partial pressure unit, first partial pressure unit is connected in Section Point with second partial pressure unit, and first partial pressure unit connects first power line, and second partial pressure unit connects the second source line；
Control circuit, the control circuit includes the first delay circuit, the second delay circuit and negative circuit, first delay circuit is connected in the Section Point with second delay circuit, second delay circuit connects first power line, first delay circuit connects the second source line, and the input of the negative circuit connects first delay circuit with one the 3rd node；
Isolation and transmission circuit, the isolation and transmission circuit includes the first NMOS tube and the first PMOS, the grid of first PMOS connects the output end of the negative circuit with a fourth node, the grid of first NMOS tube connects the 3rd node, the source electrode of first PMOS is connected in one the 5th node with the source electrode of first NMOS tube, and the drain electrode of first PMOS is connected in one the 6th node with the drain electrode of first NMOS tube；
Functional circuit, the functional circuit connects the 3rd power line and the 5th node.
Optionally, first onunit is the first diode, and the positive pole of first diode connects the input, and negative pole connects first power line.
Optionally, second onunit is the second diode, and the positive pole of second diode connects the second source line, and negative pole connects the input.
Optionally, the negative circuit includes the second PMOS and the second NMOS tube, the grid of the grid of second PMOS and second NMOS tube connects described 3rd node, and the drain electrode of second PMOS is all connected with the fourth node with the drain electrode of second NMOS tube.
Optionally, first delay circuit includes first resistor and the first electric capacity, and the first resistor connects the Section Point and the 3rd node, the 3rd node and the second source line described in first capacitance connection.
Optionally, the control circuit also includes one the 3rd PMOS, and the grid of the 3rd PMOS connects second delay circuit, and source electrode connects first power line, the source electrode of drain electrode connection second PMOS.
Optionally, second delay circuit includes second resistance and the second electric capacity, and the second resistance connects the grid of first power line and the 3rd PMOS, the grid and the Section Point of the 3rd PMOS described in second capacitance connection.
Optionally, the functional circuit includes the 4th PMOS and the 3rd NMOS tube, the grid of the 4th PMOS and the grid of the 3rd NMOS tube are all connected with the 5th node, the drain electrode of the 4th PMOS is connected with the drain electrode of the 3rd NMOS tube, the source electrode of the 4th PMOS connects the 3rd power line, and the source electrode of the 3rd NMOS tube connects the second source line.
Optionally, first partial pressure unit is the 5th PMOS, and the grid of the 5th PMOS is connected with drain electrode, and connects the Section Point, and source electrode connects first power line.
Optionally, second partial pressure unit is the 6th PMOS, and the grid of the 6th PMOS is connected with drain electrode, and connects the second source line, and source electrode connects the Section Point.
Optionally, first partial pressure unit is four resistance, and second partial pressure unit is the 5th resistance.
Optionally, the substrate of first PMOS connects the Section Point, and the substrate of first NMOS tube connects the first node.
Optionally, it is also connected with a 3rd resistor between the first node and the 6th node.
Optionally, the voltage of first power line is higher than the voltage of the 3rd power line, and the second source line connects ground terminal.
In electrostatic discharge protective circuit of the invention; the voltage of the first power line that bleeder circuit produces electrostatic pulse carries out partial pressure; so that Section Point exports a less voltage to control circuit; first delay circuit causes that electrostatic pulse postpones transmission; now; the low potential of the 3rd node and the high potential of fourth node cause that isolation and transmission circuit is closed, so that, the voltage of electrostatic pulse is not transmitted to functional circuit.Afterwards, the high potential of the 3rd node and the low potential of fourth node cause that isolation and transmission circuit is opened so that functional circuit normal work.In the present invention, in the stage that electrostatic pulse rises, it is to avoid the high voltage of electrostatic pulse is transferred to functional circuit, so that defencive function circuit.
Brief description of the drawings
Fig. 1 is the electrical block diagram of electrostatic discharge protective circuit of the prior art；
Fig. 2 is the electrical block diagram of electrostatic discharge protective circuit in one embodiment of the invention；
Fig. 3 is the emulation schematic diagram of electrostatic discharge protective circuit in one embodiment of the invention.
Specific embodiment
Wafer embarkation case of the invention and preparation method thereof is described in more detail below in conjunction with schematic diagram, which show the preferred embodiments of the present invention, it should be appreciated that those skilled in the art can change invention described herein, and still realize advantageous effects of the invention.Therefore, description below is appreciated that widely known for those skilled in the art, and is not intended as limitation of the present invention.
Core concept of the invention is, when input produces positive electrostatic pulse, electrostatic pulse passes through the first onunit by the voltage high of the first power line, so that bleeder circuit is opened, the voltage of the first power line is carried out partial pressure by the first bleeder circuit and the second bleeder circuit so that Section Point exports a less voltage to control circuit.Due to the effect of the first delay circuit delays transmission, so that the stage that electrostatic pulse rises, the current potential of the 3rd node is low, and cause that the current potential of fourth node is height by negater circuit, so as to the first PMOS and the first NMOS tube are turned off, so that isolation and transmission circuit is closed, electrostatic pulse is not transmitted to functional circuit.Afterwards, the voltage of the 3rd node is slowly raised, and the voltage of fourth node is slowly reduced so that the first PMOS and the first NMOS tube are opened, so that functional circuit normal work.When input produces negative electrostatic pulse, electrostatic pulse spreads out of second source line by the second onunit, and electrostatic pulse is discharged.In the present invention, the stage that electrostatic pulse rises, high-tension electrostatic pulse will not produce influence to functional circuit, it is ensured that functional circuit normal work.
Electrostatic discharge protective circuit of the invention is described in detail below in conjunction with Fig. 2-Fig. 3.With reference to shown in Fig. 2, it is specifically included the circuit diagram of electrostatic discharge protective circuit of the invention；
Discharge circuit 20, the discharge circuit 20 includes the first onunit 21 and the second onunit 22, first onunit 21 is connected in first node A with second onunit 22, the first node A connects an input IN, the first onunit D1 the first power line of connection VDDH, the connection second source line of the second onunit 22 VSS.In the present embodiment, first onunit 21 is the positive pole connection input IN of the first diode D1, the first diode D1, and negative pole connects the first power line VDDH.Second onunit 22 connects the second source line VSS for the positive pole of the second diode D2, the second diode D2, and negative pole connects the input IN.In the present embodiment, input IN can produce electrostatic pulse, and be transferred to the first power line VDDH and second source line VSS by the first onunit 21 and the second onunit 22.
Bleeder circuit 30, the bleeder circuit 30 includes the first partial pressure unit 31 and the second partial pressure unit 32, first partial pressure unit 31 is connected in Section Point B with second partial pressure unit 32, first partial pressure unit 31 connects the first power line VDDH, and second partial pressure unit 32 connects the second source line VSS.First partial pressure unit 31 is the 5th PMOS MP5, and the grid of the 5th PMOS MP5 is connected with drain electrode, connects the Section Point B, and source electrode connects the first power line VDDH, and substrate connects the first power line VDDH.The unit of second partial pressure 32 is the 6th PMOS MP6, and the grid of the 6th PMOS MP6 is connected with drain electrode, connects the second source line VSS, and source electrode connects the Section Point B, substrate connection second source line VSS.By bleeder circuit 30 so that the voltage of Section Point B less than the first power line VDDH voltage, also, the voltage of Section Point B size depend on the 5th PMOS MP5 and the 6th PMOS MP6 impedance size.It should be noted that in other embodiments of the invention, first partial pressure unit 31 can also be the 4th resistance (not shown), and second partial pressure unit 32 can also be the 5th resistance (not shown).
Control circuit 40, the control circuit 40 includes the first delay circuit 41, the second delay circuit 42 and negative circuit 43, first delay circuit 41 is connected in the Section Point B with second delay circuit 42, second delay circuit 42 connects the first power line VDDH, first delay circuit 41 connects the second source line VSS, and the input of the negative circuit 43 connects first delay circuit 41 with one the 3rd node C.In the present embodiment, first delay circuit 41 includes that first resistor R1 and the first electric capacity C1, the first resistor R1 connect the Section Point B and the 3rd node C, and the first electric capacity C1 connects the 3rd node C and second source line VSS.The negative circuit 43 includes the second PMOS MP2 and the second NMOS tube MN2, the grid of the grid of the second PMOS MP2 and the second NMOS tube MN2 connects described 3rd node C (Coupling point of the first delay circuit 41), the drain electrode of the second PMOS MP2 is all connected with the fourth node D with the drain electrode of the second NMOS tube MN2, the substrate of the second PMOS MP2 connects source electrode and substrate connection second source the line VSS of the first power line VDDH, the second NMOS tube MN2.The control circuit 40 also includes one the 3rd PMOS MP3, the grid of the 3rd PMOS MP3 connects second delay circuit 42, connect the Coupling point of second resistance R2 and the second electric capacity C2, the first power line VDDH described in source electrode, the source electrode of drain electrode connection the second PMOS MP2.Second delay circuit 42 includes second resistance R2 and the second electric capacity C2, the second resistance R2 connects the grid of the first power line VDDH and the 3rd PMOS MP3, and the second electric capacity C2 connects the grid and the Section Point B of the 3rd PMOS MP3.
Isolation and transmission circuit 50, the isolation and transmission circuit 50 includes the first NMOS tube MN1 and the first PMOS MP1, the grid connection of the first PMOS MP1 connects the output end of the negative circuit 43 with a fourth node D, the grid of the first NMOS tube MN1 connects the 3rd node C, the source electrode of the first PMOS MP1 is connected in one the 5th node E with the source electrode of the first NMOS tube MN1, and the drain electrode of the first PMOS MP1 is connected in one the 6th node F with the drain electrode of the first NMOS tube MN1.The substrate of the first PMOS MP1 connects the Section Point B, and the substrate of the first NMOS tube MN1 connects the first node A.In the present invention, the stage for rising in electrostatic pulse, the delay circuit 42 of first delay circuit 41 and second transmits the voltage delay of Section Point B, so as to control the switch of isolation and transmission circuit 50.
Functional circuit 10, the connection of the functional circuit 10 the 3rd power line VDD and the 5th node E.In the present embodiment, illustrated so that the functional circuit 10 is as negative circuit as an example, the functional circuit 10 includes the 4th PMOS MP4 and the 3rd NMOS tube MN3, the grid of the 4th PMOS MP4 and the grid of the 3rd NMOS tube MN3 are all connected with the 5th node E, the drain electrode of the 4th PMOS MP4 is connected with the drain electrode of the 3rd NMOS tube MN3, the source electrode of the 4th PMOS N4 connects the 3rd power line VDD, and the source electrode of the 3rd NMOS tube MN3 connects the second source line VSS.Certainly, it will be appreciated by persons skilled in the art that functional unit of the invention 10 can also be any other circuit, the present invention should be not limited.In the present embodiment, the voltage of the voltage higher than the 3rd power line VDD of the first power line VDDH, the second source line VSS connects ground terminal, and the electrostatic pulse that input IN is produced can be discharged into ground terminal by second source line VSS.
Additionally, in the present embodiment, being also connected with a 3rd resistor R3 between the first node A and the 6th node F so that the voltage of the 6th node F is smaller.
The operation principle of electrostatic discharge protective circuit of the invention is as follows：
When input IN produces positive electrostatic pulse, electrostatic pulse passes through the first onunit D1 by the voltage high of the first power line VDDH, so that bleeder circuit 30 is opened, the voltage of the first power line VDDH is carried out partial pressure by the first bleeder circuit 31 and the second bleeder circuit 32, so that voltage of the voltage of Section Point B less than the first power line VDDH, for example, can be 1/2nd, three/first-class of the voltage of the first power line VDDH.The voltage signal of Section Point B is transferred to control circuit 40 by the first delay circuit 41 and negative circuit 43.First delay circuit 41 postpones to transmit the voltage signal, so as to the stage risen in electrostatic pulse, so that the current potential of the 3rd node C is low, and cause that the current potential of fourth node D is height by negative circuit 43, so as to the first PMOS MP1 and the first NMOS tube MN1 is turned off, so that isolation and transmission circuit 50 is closed, electrostatic pulse is not transmitted to functional circuit 10.Simultaneously, the voltage signal of Section Point B is postponed by the second delay circuit 42, so that the grid of the 3rd PMOS MP3 is low potential, so that the transistor in negative circuit 43 is not above the voltage that the second PMOS MP2 and the second NMOS tube MN2 can bear, it is ensured that negative circuit 43 being capable of normal work.By the transmission of negative circuit 43 so that electrostatic pulse discharges into second source line VSS.The time constant of the first delay circuit 41 is
The time constant of the second delay circuit 42 is
Coupling with the first delay circuit 41 and the second delay circuit 42 decays, the voltage of the 3rd node C gradually rises, the voltage of fourth node D is gradually reduced, so that the first PMOS MP1 and the first NMOS tube MN1 are opened, so that isolation and transmission circuit 50 is opened, voltage signal is transferred to functional circuit 10, so that the normal work of functional circuit 10.
When input IN produces negative electrostatic pulse, electrostatic pulse spreads out of second source line VSS by the second onunit D2, and electrostatic pulse is discharged.
In the present invention, high-tension electrostatic pulse will not produce influence to functional circuit, it is ensured that functional circuit normal work.With reference to shown in Fig. 3, abscissa is the time to the analogous diagram of electrostatic discharge protective circuit in Fig. 3, and ordinate is voltage.The first power line VDDH, the voltage relationship of the 6th node F and the 5th node E are sets forth in Fig. 3.It can be seen that when electrostatic pulse is produced on input IN, in the stage that electrostatic pulse rises, isolation and transmission circuit 50 is closed so that functional circuit 10 is not influenceed by electrostatic pulse.When electrostatic pulse plateau, isolation and transmission circuit 50 is opened, so as to the voltage of the 6th node F is transferred into the 5th node E, and because isolation and transmission circuit 50 is in the state not fully opened (the first PMOS MP1 and the first NMOS tube MN1 are equivalent to resistance), so that the voltage of the 5th node E is less than the voltage of the 6th node, so that the grid voltage (voltage of the 5th node E) of transistor is smaller in functional circuit 10, the grid oxic horizon of the 4th PMOS MP4 and the 3rd NMOS tube MN3 in assurance function circuit 10 will not produce the phenomenon for puncturing, ensure the normal work of circuit.Voltage on electrostatic pulse decline stage, the first power line VDDH declines rapidly, meanwhile, the voltage of the 6th node F lower key therewith.Due to there is electric leakage on the second source line VSS in circuit so that the source voltage (voltage of the 5th node E) of the first PMOS MP1 and the first NMOS tube MN1 in isolation and transmission circuit 50 slowly reduces.Be can be seen that from the simulation result in Fig. 3; in electrostatic discharge protective circuit of the invention; electrostatic pulse is input to the voltage of transistor gate in functional circuit 10 much smaller than the voltage on the first power line VDDH; so as to the grid oxic horizon of defencive function circuit 10 is not breakdown; the normal work of assurance function circuit 10
In sum; in electrostatic discharge protective circuit of the invention; when electrostatic pulse is produced on input; the voltage of the first power line that bleeder circuit produces electrostatic pulse carries out partial pressure so that Section Point exports a less voltage to control circuit, and the first delay circuit causes that electrostatic pulse postpones transmission; now; the low potential of the 3rd node and the high potential of fourth node cause that isolation and transmission circuit is closed, so that, the voltage of electrostatic pulse is not transmitted to functional circuit.Afterwards, the high potential of the 3rd node and the low potential of fourth node cause that isolation and transmission circuit is opened so that functional circuit normal work.In the present invention, in the stage that electrostatic pulse rises, it is to avoid the high voltage of electrostatic pulse is transferred to functional circuit, so that defencive function circuit.
Obviously, those skilled in the art can carry out various changes and modification without departing from the spirit and scope of the present invention to the present invention.So, if these modifications of the invention and modification belong within the scope of the claims in the present invention and its equivalent technologies, then the present invention is also intended to comprising these changes and modification.
Claims (14)
1. a kind of electrostatic discharge protective circuit, it is characterised in that including；
Discharge circuit, the discharge circuit includes the first onunit and the second onunit, and described first leads
Logical unit is connected in first node with second onunit, and the first node connects an input, institute
State the first onunit and connect the first power line, second onunit connects second source line；
Bleeder circuit, the bleeder circuit includes the first partial pressure unit and the second partial pressure unit, described first point
Pressure unit is connected in Section Point, the first partial pressure unit connection described first with second partial pressure unit
Power line, second partial pressure unit connects the second source line；
Control circuit, the control circuit includes the first delay circuit, the second delay circuit and negative circuit,
First delay circuit is connected in the Section Point, second deferred telegram with second delay circuit
Road connects first power line, and first delay circuit connects the second source line, the anti-phase electricity
The input on road connects first delay circuit with one the 3rd node；
Isolation and transmission circuit, the isolation and transmission circuit includes the first NMOS tube and the first PMOS, institute
State the output end that the grid of the first PMOS connects the negative circuit with a fourth node, described first
The grid of NMOS tube connects the 3rd node, the source electrode of first PMOS and described first
The source electrode of NMOS tube is connected in one the 5th node, the drain electrode of first PMOS and described first
The drain electrode of NMOS tube is connected in one the 6th node；
Functional circuit, the functional circuit connects the 3rd power line and the 5th node.
2. electrostatic discharge protective circuit as claimed in claim 1, it is characterised in that first onunit is
First diode, the positive pole of first diode connects the input, and negative pole connects first power supply
Line.
3. electrostatic discharge protective circuit as claimed in claim 1, it is characterised in that second onunit is
Second diode, the positive pole of second diode connects the second source line, and negative pole connects the input
End.
4. electrostatic discharge protective circuit as claimed in claim 1, it is characterised in that the negative circuit includes the
Two PMOSs and the second NMOS tube, the grid of second PMOS and second NMOS tube
Grid connect described 3rd node, the drain electrode of second PMOS and second NMOS tube
Drain electrode is all connected with the fourth node.
5. electrostatic discharge protective circuit as claimed in claim 4, it is characterised in that the first delay circuit bag
First resistor and the first electric capacity are included, the first resistor connects the Section Point and the 3rd node, institute
State the 3rd node described in the first capacitance connection and the second source line.
6. electrostatic discharge protective circuit as claimed in claim 4, it is characterised in that the control circuit also includes
One the 3rd PMOS, the grid of the 3rd PMOS connects second delay circuit, source electrode connection
First power line, the source electrode of drain electrode connection second PMOS.
7. electrostatic discharge protective circuit as claimed in claim 6, it is characterised in that the second delay circuit bag
Second resistance and the second electric capacity are included, the second resistance connects first power line and the 3rd PMOS
The grid of pipe, the grid and the Section Point of the 3rd PMOS described in second capacitance connection.
8. electrostatic discharge protective circuit as claimed in claim 1, it is characterised in that the functional circuit includes the
Four PMOSs and the 3rd NMOS tube, the grid and the 3rd NMOS tube of the 4th PMOS
Grid be all connected with the 5th node, the drain electrode of the 4th PMOS and the 3rd NMOS tube
Drain electrode is connected, and the source electrode of the 4th PMOS connects the 3rd power line, the 3rd NMOS tube
Source electrode connect the second source line.
9. electrostatic discharge protective circuit as claimed in claim 1, it is characterised in that first partial pressure unit is
5th PMOS, the grid of the 5th PMOS is connected with drain electrode, and connects the Section Point,
Source electrode connects first power line.
10. electrostatic discharge protective circuit as claimed in claim 9, it is characterised in that second partial pressure unit is
6th PMOS, the grid of the 6th PMOS is connected with drain electrode, and connects the second source line,
Source electrode connects the Section Point.
11. electrostatic discharge protective circuits as claimed in claim 1, it is characterised in that first partial pressure unit is
Four resistance, second partial pressure unit is the 5th resistance.
12. electrostatic discharge protective circuits as claimed in claim 1, it is characterised in that first PMOS
Substrate connects the Section Point, and the substrate of first NMOS tube connects the first node.
13. electrostatic discharge protective circuits as claimed in claim 1, it is characterised in that the first node with it is described
A 3rd resistor is also connected between 6th node.
14. electrostatic discharge protective circuits as claimed in claim 1, it is characterised in that the electricity of first power line
Pressure is higher than the voltage of the 3rd power line, and the second source line connects ground terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510974300.4A CN106899011B (en) | 2015-12-18 | 2015-12-18 | Electrostatic discharge protective circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510974300.4A CN106899011B (en) | 2015-12-18 | 2015-12-18 | Electrostatic discharge protective circuit |
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| CN106899011A true CN106899011A (en) | 2017-06-27 |
| CN106899011B CN106899011B (en) | 2019-01-18 |
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| CN201510974300.4A Active CN106899011B (en) | 2015-12-18 | 2015-12-18 | Electrostatic discharge protective circuit |
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| CN109828629A (en) * | 2017-11-23 | 2019-05-31 | 北京展讯高科通信技术有限公司 | A kind of VCO circuit |
| CN110138224A (en) * | 2019-05-13 | 2019-08-16 | 上海安费诺永亿通讯电子有限公司 | A kind of wireless charging receiving terminal and mobile terminal for supporting multi-coil switching |
| CN110912098A (en) * | 2019-11-25 | 2020-03-24 | 南京尔芯电子有限公司 | Circuit for preventing electrostatic discharge ESD protection from causing leakage current under power-off |
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| CN1420563A (en) * | 2001-11-16 | 2003-05-28 | 松下电器产业株式会社 | Semiconductor device |
| CN1466267A (en) * | 2002-07-04 | 2004-01-07 | 旺宏电子股份有限公司 | Gate equal potential circuit and method for input/output electrostatic dischare protection |
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| CN110912098A (en) * | 2019-11-25 | 2020-03-24 | 南京尔芯电子有限公司 | Circuit for preventing electrostatic discharge ESD protection from causing leakage current under power-off |
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| Publication number | Publication date |
|---|---|
| CN106899011B (en) | 2019-01-18 |
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