CN102983102A - Array substrate and manufacturing method thereof, as well as display device - Google Patents
Array substrate and manufacturing method thereof, as well as display device Download PDFInfo
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- CN102983102A CN102983102A CN2012105132972A CN201210513297A CN102983102A CN 102983102 A CN102983102 A CN 102983102A CN 2012105132972 A CN2012105132972 A CN 2012105132972A CN 201210513297 A CN201210513297 A CN 201210513297A CN 102983102 A CN102983102 A CN 102983102A
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Abstract
The invention discloses a manufacturing method of an array substrate. The manufacturing method of the array substrate comprises the following steps: forming a graph comprising a grid line, a first grid electrode, a second grid electrode, a grid insulating layer, a first active layer and a second active layer on the substrate; forming a graphing comprising data lines, a first source electrode, a first drain electrode, a second source electrode and a second drain electrode, so that the second grid electrode, the grid insulating layer, the second active layer, the second source electrode and the second drain electrode form a static dredge thin transistor, and at least one static dredge thin transistor is formed between each two adjacent data lines to form static electricity for dredging the data lines; forming an image comprising a via hole and a pixel electrode; and forming a peripheral circuit and connecting the second grid electrode to a low level signal end of the peripheral circuit. The invention further discloses the array substrate and a display device, so that the static electricity is consumed step by step, static breakdown of the array substrate in the manufacturing process is avoided and the yield is increased.
Description
Technical field
The present invention relates to the Display Technique field, particularly a kind of array base palte and preparation method thereof, display unit.
Background technology
In the TFT-LCD panel manufacturing process, especially after (SD) metal procedure is leaked in the source, because the accumulation of existing double layer of metal, accumulated static a large amount of, wait for and discharging, after the SD metal is made, can cause a large amount of electrostatic breakdowns, especially in the overlapping place of the two ends of data wire (Data) line and grid (Gate) metal wire.And do not finish owing to technical process also this time, do not have via layer and pixel electrode ITO layer, and the antistatic cell ESD that designs on the panel is not worked, so can not play a protective role.
Summary of the invention
The technical problem that (one) will solve
The technical problem to be solved in the present invention is: how to protect in panel manufacturing process the electrostatic breakdown phenomenon not to occur.
(2) technical scheme
For solving the problems of the technologies described above, the invention provides a kind of array substrate manufacturing method, comprise step:
Form the figure that comprises grid line, first grid, second grid, gate insulation layer, the first active layer and the second active layer at substrate;
Formation comprises the figure of data wire, the first source electrode, the first drain electrode, the second source electrode and the second drain electrode, and first grid, gate insulation layer, the first active layer, the first source electrode and the first drain electrode form and drive thin-film transistor; Second grid, gate insulation layer, the second active layer, the second source electrode and the second drain electrode form the Anti-static thin-film transistor, and make at least one described Anti-static thin-film transistor of formation between every adjacent two data wires, to dredge the static of data wire;
Formation comprises the figure of passivation layer, via hole and pixel electrode;
Form peripheral circuit, and described second grid is connected to the low level signal end of peripheral circuit.
Wherein, the step that forms the figure of grid line, first grid, second grid, gate insulation layer, the first active layer and the second active layer at substrate specifically comprises:
Form the grid metallic film, form the figure of grid line, first grid and second grid by composition technique, make the zone of correspondence between every adjacent two data wires of data wire to be formed all be formed with the figure of second grid;
Form gate insulation layer;
Form semiconductive thin film, form the figure of the first active layer and the second active layer by composition technique, make described the first active layer and the second active layer lay respectively at described first grid and zone corresponding to second grid.
Wherein, the step of the figure of formation data wire, the first source electrode, the first drain electrode, the second source electrode and the second drain electrode specifically comprises:
Metallic film is leaked in the formation source, forms data wire, forms the first source electrode and the first figure that drains in zone corresponding to the first active layer by composition technique, forms the figure of the second source electrode and the second drain electrode in zone corresponding to the second active layer; And make the second source electrode connect respectively adjacent two data wires with being connected to drain, second grid is unsettled.
Wherein, the figure that forms second grid specifically comprises: the figure that is formed on N second grid between every adjacent two data wires of data wire to be formed; The figure that forms the second active layer specifically comprises: zone corresponding to figure that is formed on N second grid forms the figure of N the second active layer; The figure that forms the second source electrode and the second drain electrode specifically comprises: zone corresponding to figure that is formed on N the second active layer forms the figure of N the second source electrode and N the second drain electrode, be connected in parallel on N Anti-static thin-film transistor between every adjacent two data wires, N 〉=1 thereby form.
Wherein, specifically also comprise when forming second grid: form the extension integrally formed with second grid, described extension is used for being connected to the low level signal end of peripheral circuit.
Wherein, describedly dredge the non-pixel region that thin-film transistor is formed on substrate edges.
The present invention also provides a kind of array base palte, be connected with at least one Anti-static thin-film transistor between every adjacent two data wires on the described array base palte, the source of described Anti-static thin-film transistor is leaked and is connected respectively described adjacent two data wires, grid connects the low voltage signal end of described array base palte, and a plurality of Anti-static thin-film transistors that level is associated between adjacent two data wires form the Anti-static path.
Wherein, a plurality of thin-film transistors that are connected in parallel between every adjacent two data wires.
Wherein, described Anti-static path is positioned at the non-pixel region at described array base palte edge.
The invention also discloses a kind of display unit, comprise above-mentioned each described array base palte.
(3) beneficial effect
The present invention is by increasing the thin-film transistor that at least one is used for Anti-static between adjacent two data wires at array base palte, the passage that provides static to discharge, static is consumed down step by step, avoided array base palte that electrostatic breakdown occurs in manufacturing process, thereby improve yield.
Description of drawings
Fig. 1 is a kind of array substrate manufacturing method flow chart of the embodiment of the invention;
Fig. 2 is the structural representation of the non-pixel region in edge of a kind of array base palte of the embodiment of the invention.
Embodiment
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.Following examples are used for explanation the present invention, but are not used for limiting the scope of the invention.
As shown in Figure 1, the array substrate manufacturing method of present embodiment comprises:
Step S100 forms the figure that comprises grid line, first grid, second grid, gate insulation layer, the first active layer and the second active layer at substrate.This step specifically comprises:
Form (comprising the various ways such as deposition, coating and sputter) grid metallic film, form the figure of grid line, first grid and second grid by composition technique (composition technique generally includes the techniques such as photoresist coating, exposure, development, etching, photoresist lift off), make the zone of correspondence between every adjacent two data wires of data wire to be formed all be formed with the figure of second grid.
Form gate insulation layer at substrate surface behind the figure of formation grid line, first grid and second grid.
Form semiconductive thin film at gate insulation layer, form the figure of the first active layer and the second active layer by composition technique, make the first active layer and the second active layer lay respectively at described first grid and zone corresponding to second grid, and be positioned at top corresponding to grid region on the insulating barrier.
Step S200 forms the figure that comprises data wire, the first source electrode, the first drain electrode, the second source electrode and the second drain electrode.This step specifically comprises: metallic film is leaked in the formation source on the substrate behind the step S100, forms data wire by composition technique; Above zone corresponding to the first active layer, form the figure of the first source electrode and the first drain electrode, above zone corresponding to the second active layer, form the figure of the second source electrode and the second drain electrode; And make the second source electrode connect respectively adjacent two data wires with being connected to drain, second grid is unsettled.First grid, gate insulation layer, the first active layer, the first source electrode and the first drain electrode form and drive thin-film transistor; Second grid, gate insulation layer, the second active layer, the second source electrode and the second drain electrode form the Anti-static thin-film transistor, and make at least one Anti-static thin-film transistor of formation between every adjacent two data wires, to dredge the static of data wire.
Step S300 forms the figure that comprises passivation layer, via hole and pixel electrode.The technological process of this step and prior art are similar to be repeated no more herein.
Step S400 forms peripheral circuit, and second grid is connected to the low level signal end of peripheral circuit.Because after array base palte completed, the antistatic cell ESD of peripheral circuit was started working, and no longer needs the Anti-static thin-film transistor, therefore second grid is connected to the low level signal end of peripheral circuit, make it forever be in off state.
Because when in step S100, making grid, the first grid line and the second grid line, the grid Metal-accumulation produce static in the manufacture process, being equivalent to has certain micro voltage on the grid line, make the Anti-static thin-film transistor belong to the crack state that opens, when a certain data lines happens suddenly large voltage static, can pass to next data wire by the Anti-static thin-film transistor, so transmit, because RC delay principle, with voltage consumption, be unlikely to whole voltages and concentrate on the data lines and puncture, produce yield thereby improved array base palte.
Further, the figure that forms second grid specifically comprises: the figure that is formed on N second grid between every adjacent two data wires of data wire to be formed; The figure that forms the second active layer specifically comprises: zone corresponding to figure that is formed on N second grid forms the figure of N the second active layer; The figure that forms the second source electrode and the second drain electrode specifically comprises: zone corresponding to figure that is formed on N the second active layer forms the figure of N the second source electrode and N the second drain electrode, be connected in parallel on N Anti-static thin-film transistor between every adjacent two data wires, N 〉=1 thereby form.N is the bigger the better in theory, and reality can be determined according to the array base palte size reasonable quantity of N.Because a plurality of Anti-static thin-film transistors in parallel when a certain data lines happens suddenly large voltage static, can pass to next data wire by a plurality of Anti-static thin-film transistors between two data wires, and voltage is consumed quickly.
Further, when forming second grid, specifically also comprise: form the extension integrally formed with second grid, this extension is used for being connected to the low level signal end of peripheral circuit, to make things convenient for when array base palte completes second grid, be the low level signal end that the grid of Anti-static thin-film transistor is connected to peripheral circuit, thoroughly turn-off.
Further, dredge the non-pixel region that thin-film transistor is formed on substrate edges, not only make things convenient for being connected of low level signal end of its grid and peripheral circuit, and do not affect the display quality of pixel region when display frame.
As shown in Figure 2, the array base palte for making as stated above.Be on the array base palte at least one Anti-static thin-film transistor 2 of being connected between every adjacent two data wires 1 with the difference of existing array base palte, a plurality of Anti-static thin-film transistors 2 that have been connected in parallel among Fig. 2, these thin-film transistor cascades have consisted of some Anti-static paths.The source of Anti-static thin-film transistor 2 is leaked and is connected respectively adjacent two data wires 1, when on array base palte, also not forming pixel electrode layer and corresponding via hole, the grid of thin-film transistor is in vacant state, since the grid Metal-accumulation produce static in the manufacture process, being equivalent to has certain micro voltage on the grid line, thin-film transistor belongs to the crack state that opens, when a certain data lines happens suddenly large voltage static, can pass to next data wire by thin-film transistor, so transmit, many thin-film transistors of flowing through are with current drain, be unlikely to whole voltages and concentrate on the data lines, puncture.And after thereafter pixel electrode layer and corresponding via layer form, this grid access VGL(low-voltage) signal, be in thorough off state, ensure array base palte manufacturing process finish after not short circuit between the data wire.
Further, in order to make things convenient for the making of array base palte, and do not affect final display effect, some thin-film transistors are produced on the two ends of data wire, thereby make the Anti-static path be positioned at the non-pixel region at array base palte edge.
The present invention also provides a kind of display unit, comprises above-mentioned array base palte.This display unit can be any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, oled panel, LCD TV, liquid crystal display, DPF, mobile phone, panel computer.
Above execution mode only is used for explanation the present invention; and be not limitation of the present invention; the those of ordinary skill in relevant technologies field; in the situation that does not break away from the spirit and scope of the present invention; can also make a variety of changes and modification; therefore all technical schemes that are equal to also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.
Claims (10)
1. an array substrate manufacturing method is characterized in that, comprises step:
Form the figure that comprises grid line, first grid, second grid, gate insulation layer, the first active layer and the second active layer at substrate;
Formation comprises the figure of data wire, the first source electrode, the first drain electrode, the second source electrode and the second drain electrode, and first grid, gate insulation layer, the first active layer, the first source electrode and the first drain electrode form and drive thin-film transistor; Second grid, gate insulation layer, the second active layer, the second source electrode and the second drain electrode form the Anti-static thin-film transistor, and make at least one described Anti-static thin-film transistor of formation between every adjacent two data wires, to dredge the static of data wire;
Formation comprises the figure of passivation layer, via hole and pixel electrode;
Form peripheral circuit, and described second grid is connected to the low level signal end of peripheral circuit.
2. array substrate manufacturing method as claimed in claim 1 is characterized in that, the step that forms the figure of grid line, first grid, second grid, gate insulation layer, the first active layer and the second active layer at substrate specifically comprises:
Form the grid metallic film, form the figure of grid line, first grid and second grid by composition technique, make the zone of correspondence between every adjacent two data wires of data wire to be formed all be formed with the figure of second grid;
Form gate insulation layer;
Form semiconductive thin film, form the figure of the first active layer and the second active layer by composition technique, make described the first active layer and the second active layer lay respectively at described first grid and zone corresponding to second grid.
3. array substrate manufacturing method as claimed in claim 1 is characterized in that, the step that forms the figure of data wire, the first source electrode, the first drain electrode, the second source electrode and the second drain electrode specifically comprises:
Metallic film is leaked in the formation source, forms data wire by composition technique, forms the figure of the first source electrode and the first drain electrode in zone corresponding to the first active layer, forms the figure of the second source electrode and the second drain electrode in zone corresponding to the second active layer; And make the second source electrode connect respectively adjacent two data wires with being connected to drain, second grid is unsettled.
4. such as each described array substrate manufacturing method in the claim 1 ~ 3, it is characterized in that the figure that forms second grid specifically comprises: the figure that is formed on N second grid between every adjacent two data wires of data wire to be formed; The figure that forms the second active layer specifically comprises: zone corresponding to figure that is formed on N second grid forms the figure of N the second active layer; The figure that forms the second source electrode and the second drain electrode specifically comprises: zone corresponding to figure that is formed on N the second active layer forms the figure of N the second source electrode and N the second drain electrode, be connected in parallel on N Anti-static thin-film transistor between every adjacent two data wires, N 〉=1 thereby form.
5. such as each described array substrate manufacturing method in the claim 1 ~ 3, it is characterized in that, specifically also comprise when forming second grid: form the extension integrally formed with second grid, described extension is used for being connected to the low level signal end of peripheral circuit.
6. such as each described array substrate manufacturing method in the claim 1 ~ 3, it is characterized in that, describedly dredge the non-pixel region that thin-film transistor is formed on substrate edges.
7. array base palte, it is characterized in that, be connected with at least one Anti-static thin-film transistor between every adjacent two data wires on the described array base palte, the source of described Anti-static thin-film transistor is leaked and is connected respectively described adjacent two data wires, grid connects the low voltage signal end of described array base palte, and a plurality of Anti-static thin-film transistors that level is associated between adjacent two data wires form the Anti-static path.
8. array base palte as claimed in claim 7 is characterized in that, a plurality of thin-film transistors are connected in parallel between every adjacent two data wires.
9. such as claim 7 or 8 described array base paltes, it is characterized in that described Anti-static path is positioned at the non-pixel region at described array base palte edge.
10. a display unit is characterized in that, comprises such as each described array base palte in the claim 7 ~ 9.
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| CN201210513297.2A CN102983102B (en) | 2012-12-04 | 2012-12-04 | Array substrate and manufacturing method thereof, as well as display device |
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| CN201210513297.2A CN102983102B (en) | 2012-12-04 | 2012-12-04 | Array substrate and manufacturing method thereof, as well as display device |
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| CN104752442A (en) * | 2015-03-26 | 2015-07-01 | 京东方科技集团股份有限公司 | Array substrate |
| CN105093739A (en) * | 2015-07-30 | 2015-11-25 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and antistatic array substrate thereof |
| CN105242463A (en) * | 2015-11-03 | 2016-01-13 | 深圳市华星光电技术有限公司 | Liquid crystal display device |
| CN111180523A (en) * | 2019-12-31 | 2020-05-19 | 成都中电熊猫显示科技有限公司 | Thin film transistor, array substrate and liquid crystal display panel |
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| CN102655145A (en) * | 2012-01-12 | 2012-09-05 | 京东方科技集团股份有限公司 | Static releasing protection circuit and working method thereof |
| CN202550507U (en) * | 2012-03-15 | 2012-11-21 | 京东方科技集团股份有限公司 | Electrostatic protection circuit, array substrate and display device |
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| US20070273802A1 (en) * | 2006-05-23 | 2007-11-29 | Casio Computer Co., Ltd. | Display device with static electricity protecting circuit |
| CN101995714A (en) * | 2009-08-28 | 2011-03-30 | 北京京东方光电科技有限公司 | Array substrate and manufacturing method thereof |
| US20120075546A1 (en) * | 2010-09-28 | 2012-03-29 | Chengming He | Lcd panel and method for manufacturing the same |
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| CN104752442A (en) * | 2015-03-26 | 2015-07-01 | 京东方科技集团股份有限公司 | Array substrate |
| CN104752442B (en) * | 2015-03-26 | 2017-08-11 | 京东方科技集团股份有限公司 | A kind of array base palte |
| CN105093739A (en) * | 2015-07-30 | 2015-11-25 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and antistatic array substrate thereof |
| CN105242463A (en) * | 2015-11-03 | 2016-01-13 | 深圳市华星光电技术有限公司 | Liquid crystal display device |
| CN105242463B (en) * | 2015-11-03 | 2018-10-19 | 深圳市华星光电技术有限公司 | Liquid crystal display device |
| CN111180523A (en) * | 2019-12-31 | 2020-05-19 | 成都中电熊猫显示科技有限公司 | Thin film transistor, array substrate and liquid crystal display panel |
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| CN102983102B (en) | 2015-01-14 |
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