CN106356381B - A kind of array substrate and preparation method thereof, display panel - Google Patents
A kind of array substrate and preparation method thereof, display panel Download PDFInfo
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- CN106356381B CN106356381B CN201611015730.4A CN201611015730A CN106356381B CN 106356381 B CN106356381 B CN 106356381B CN 201611015730 A CN201611015730 A CN 201611015730A CN 106356381 B CN106356381 B CN 106356381B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
Abstract
The present invention provides a kind of array substrate and preparation method thereof, display panel, is related to field of display technology, can reduce the load in display device on data line, to reduce the power consumption of display device.The array substrate includes viewing area and the virtual viewing area that the viewing area periphery is arranged in；The viewing area includes sub-pixel, and the virtual viewing area includes virtual sub-pixel；The first transparency electrode that the sub-pixel and the virtual sub-pixel include thin film transistor (TFT), is electrically connected with the drain electrode of the thin film transistor (TFT)；Wherein, the source electrode of the thin film transistor (TFT) in the sub-pixel is connect with data line；The source electrode and the data line of the thin film transistor (TFT) in the virtual sub-pixel disconnect.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of array substrate and preparation method thereof, display panel.
Background technique
Currently, such as mobile phone or other some mobile devices, since its display screen occupies larger proportion, when leading to standby
Between it is too short, to need often charging, bring certain trouble, thus the logic power consumption for reducing display screen is particularly important.
Wherein, in display screen, since data line is more, by taking resolution ratio is the UHD display screen of 3840*2160 as an example,
There is 3840*3 root data line altogether, when display screen works normally, the data line is constantly in scanning mode, therefore, reduces
Load on data line can cut much ice to the power consumption for reducing display screen.
Summary of the invention
The embodiment of the present invention provides a kind of array substrate and preparation method thereof, display panel, can reduce in display device
Load on data line, to reduce the power consumption of display device.
In order to achieve the above objectives, the embodiment of the present invention adopts the following technical scheme that
In a first aspect, a kind of array substrate is provided, including viewing area and the virtual display that the viewing area periphery is arranged in
Area；The viewing area includes sub-pixel, and the virtual viewing area includes virtual sub-pixel；The sub-pixel and the virtual subnet picture
The first transparency electrode that element includes thin film transistor (TFT), is electrically connected with the drain electrode of the thin film transistor (TFT)；Wherein, it is located at the son
The source electrode of the thin film transistor (TFT) in pixel is connect with data line；The thin film transistor (TFT) in the virtual sub-pixel
Source electrode and the data line disconnect.
Preferably, the grid of the thin film transistor (TFT) in the sub-pixel is connected with grid line；Positioned at described virtual
The grid of the thin film transistor (TFT) in sub-pixel is electrically connected with the first public electrode wire；Wherein, it is located at the virtual sub-pixel
In the first transparency electrode be electrically connected with first public electrode wire.
It is further preferred that the sub-pixel and the virtual sub-pixel respectively further comprise second transparency electrode；Described
Two transparent electrodes are electrically connected with the second public electrode wire；Wherein, second public electrode wire and first public electrode wire
Electrical connection.
Preferably, the first transparency electrode in the virtual sub-pixel passes through with first public electrode wire
Via hole is connected.
Preferably, described in the first transparency electrode in the virtual sub-pixel and the virtual sub-pixel
Second transparency electrode is connected by via hole；Alternatively, the first transparency electrode being located in the virtual sub-pixel and described the
Two public electrode wires are connected by via hole.
Second aspect provides a kind of display panel, including above-mentioned array substrate.
Preferably, the display panel further includes to box substrate；Second transparency electrode setting is described to box substrate or institute
It states in array substrate.
The third aspect provides a kind of preparation method of array substrate, comprising: and it is synchronous to form sub-pixel in viewing area, in institute
The virtual viewing area for stating viewing area periphery forms virtual sub-pixel；The sub-pixel and the virtual sub-pixel include film crystalline substance
Body pipe, the first transparency electrode being electrically connected with the drain electrode of the thin film transistor (TFT)；Wherein, described thin in the sub-pixel
The source electrode of film transistor is connect with data line；The source electrode and the number of the thin film transistor (TFT) in the virtual sub-pixel
It is disconnected according to line.
Preferably, the grid of the thin film transistor (TFT) in the sub-pixel is connected with grid line；Positioned at described virtual
The grid of the thin film transistor (TFT) in sub-pixel is electrically connected with the first public electrode wire；Wherein, it is located at the virtual sub-pixel
In the first transparency electrode be connected with first public electrode wire by via hole.
Preferably, the sub-pixel and the virtual sub-pixel respectively further comprise second transparency electrode；Described second is transparent
Electrode is electrically connected with the second public electrode wire；Wherein, the first transparency electrode in the virtual sub-pixel and described
The second transparency electrode in virtual sub-pixel is connected by via hole；Alternatively, being located at described the in the virtual sub-pixel
One transparent electrode is connected with second public electrode wire by via hole.
The embodiment of the present invention provides a kind of array substrate and preparation method thereof, display panel, by the array substrate
Viewing area periphery virtual viewing area is set, the poor problem of array substrate etching edge homogeneity can be improved.It is basic herein
On, by by virtual sub-pixel thin film transistor (TFT) and data line disconnect, can avoid data line with it is thin in virtual sub-pixel
Coupled capacitor is generated between film transistor, so that the load of data line is reduced, and then when array substrate is used for display device,
The power consumption of display device can be reduced.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is a kind of schematic top plan view one of array substrate provided in an embodiment of the present invention；
When Fig. 2 is that a kind of data line provided in an embodiment of the present invention is connect with the thin film transistor (TFT) in virtual sub-pixel, number
According to the load schematic diagram on line；
When Fig. 3 is that the thin film transistor (TFT) in a kind of data line and virtual sub-pixel provided in an embodiment of the present invention disconnects, number
According to the load schematic diagram on line；
Fig. 4 is a kind of schematic top plan view two of array substrate provided in an embodiment of the present invention；
Fig. 5 (a) is a kind of schematic top plan view three of array substrate provided in an embodiment of the present invention；
Fig. 5 (b) be in Fig. 5 (a) AA ' to schematic cross-sectional view；
Fig. 6 (a) is a kind of schematic top plan view one of the virtual viewing area of array substrate provided in an embodiment of the present invention；
Fig. 6 (b) be in Fig. 6 (a) BB ' to schematic cross-sectional view；
Fig. 7 (a) is a kind of schematic top plan view two of the virtual viewing area of array substrate provided in an embodiment of the present invention；
Fig. 7 (b) be in Fig. 7 (a) CC ' to schematic cross-sectional view.
Detailed description of the invention:
The viewing area 01-；The virtual viewing area 02-；10- sub-pixel；20- virtual sub-pixel；30- thin film transistor (TFT)；The source 31-
Pole；32- drain electrode；41- first transparency electrode；42- second transparency electrode；50- data line；61- grid line；The first public electrode of 62-
Line；The second public electrode wire of 63-；70- substrate；80- gate insulation layer；90- passivation layer.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
The embodiment of the present invention provides a kind of array substrate, as shown in Figure 1, including viewing area 01 and setting viewing area 01 week
The virtual viewing area 02 on side；Viewing area 01 includes sub-pixel 10, and virtual viewing area 02 includes virtual sub-pixel 20；10 He of sub-pixel
The first transparency electrode 41 that virtual sub-pixel 20 includes thin film transistor (TFT) 30, is electrically connected with the drain electrode 32 of thin film transistor (TFT) 30；
Wherein, the source electrode 31 of the thin film transistor (TFT) 30 in sub-pixel 10 is connect with data line 50；In virtual sub-pixel 20
The source electrode 31 and data line 50 of thin film transistor (TFT) 30 disconnect.
If the source electrode 31 of thin film transistor (TFT) 30 in virtual sub-pixel 20 is connect with data line 50, for any radical evidence
Line 50, the load on the data line 50 are as shown in Figure 2.The embodiment of the present invention is by the source of thin film transistor (TFT) 30 in virtual sub-pixel 20
Pole 31 and data line 50 disconnect, and the load on the data line 50 is as shown in Figure 3.Comparison diagram 2 and Fig. 3 can be seen that virtual subnet
The source electrode 31 of thin film transistor (TFT) 30 and data line 50 disconnect in pixel 20 so that in virtual sub-pixel 20, data line 50 with it is thin
Coupled capacitor Cdc is not present between film transistor 30, to reduce the load on data line 50.
It should be noted that first, virtual viewing area 02 can be located at least in the side on one of side of viewing area 01, tool
Body can be configured according to the actual situation.
Second, the source electrode 31 of thin film transistor (TFT) 30, drain electrode 32 are symmetrical, so its source electrode 31, drain electrode 32 are no areas
It is other.In embodiments of the present invention, to distinguish the two poles of the earth of thin film transistor (TFT) 30 in addition to grid, wherein source electrode will be known as in a pole
31, another pole is known as drain electrode 32.
Wherein, the type of thin film transistor (TFT) is not defined in present example, can be amorphous silicon film transistor,
Polycrystalline SiTFT, oxide semiconductor thin-film transistor, Organic Thin Film Transistors etc..
Third, when the array substrate is the array substrate in liquid crystal display, first transparency electrode 41 is pixel electricity
Pole.Further, array substrate can also include public electrode.Certainly, public electrode can be set in array substrate, can also
Be arranged in liquid crystal display on box substrate.
When the array substrate is the array substrate in organic electroluminescent LED display, first transparency electrode 41
For anode, it is based on this, which further includes cathode, the organic material functional layer between anode and cathode.
The embodiment of the present invention provides a kind of array substrate, virtual by being arranged on 01 periphery of the viewing area of the array substrate
Viewing area 02 can improve the poor problem of array substrate etching edge homogeneity.On this basis, by by virtual sub-pixel
Thin film transistor (TFT) 30 and data line 50 in 20 disconnect, and can avoid data line 50 and the thin film transistor (TFT) 30 in virtual sub-pixel 20
Between generate coupled capacitor, to reduce the load of data line 50, and then when array substrate is used for display device, can reduce
The power consumption of display device.
Preferably, the structure of virtual sub-pixel 20 is identical with the structure of sub-pixel 10, only will be in virtual sub-pixel 20
The source electrode 31 and data line 50 of thin film transistor (TFT) 30 disconnect.In this way, can be in the every layer of structure formed in sub-pixel 10, it can be right
The poor problem of array substrate etching edge homogeneity is improved.
Preferably, as shown in figure 4, the grid for the thin film transistor (TFT) 30 being located in sub-pixel 10 is connected with grid line 61；It is located at
The grid of thin film transistor (TFT) 30 in virtual sub-pixel 20 is electrically connected with the first public electrode wire 62；Wherein, it is located at virtual subnet picture
First transparency electrode 41 in element 20 is electrically connected with the first public electrode wire 62.
Herein, the grid of the thin film transistor (TFT) 30 in sub-pixel 10 is connected with grid line 61, drives when applying on grid line 61
When dynamic signal, it can control the thin film transistor (TFT) 30 in sub-pixel 10 to open, work normally array substrate.
First public electrode wire 62 is equivalent to the grid line of thin film transistor (TFT) 30 in driving virtual sub-pixel 20.That is, when first
When voltage on public electrode wire 62 is greater than the cut-in voltage of thin film transistor (TFT) 30, the film crystal in virtual sub-pixel 20
Pipe 30 is constantly in opening state.
It should be noted that first, as shown in figure 4, the grid for the thin film transistor (TFT) 30 being located in sub-pixel 10 can be used
It serves as the part of grid line 61；The first public electrode wire 62 can be used in the grid of thin film transistor (TFT) 30 in virtual sub-pixel 20
Part serve as.
Certainly, grid can also be separately provided in thin film transistor (TFT) 30, the grid of the thin film transistor (TFT) 30 in sub-pixel 10
It is connected with grid line 61, the grid of the thin film transistor (TFT) 30 in virtual sub-pixel 20 is connected with the first public electrode wire 62.
Second, the connection type not being electrically connected to first transparency electrode 41 with the first public electrode wire 62 is specifically limited,
As long as 62 equipotential of first transparency electrode 41 and the first public electrode wire can be made.
The embodiment of the present invention will be located at the grid and first transparency electrode 41 of the thin film transistor (TFT) 30 in virtual sub-pixel 20
It is electrically connected with the first public electrode wire 62, makes 41 equipotential of grid and first transparency electrode, and then make in virtual sub-pixel 20
The source electrode 31 of thin film transistor (TFT) 30, drain electrode 32 and grid equipotential, so as to avoid the generation of electrostatic.
It is further preferred that sub-pixel 10 and virtual sub-pixel 20 respectively further comprise the second transparent electricity as shown in Fig. 5 (a)
Pole 42；Second transparency electrode 42 is electrically connected with the second public electrode wire 63；Wherein, the second public electrode wire 63 and the first common electrical
Polar curve 62 is electrically connected.When the array substrate is the array substrate in liquid crystal display, the sub-pixel 10 and described virtual
Second transparency electrode 42 in sub-pixel 20 is public electrode, and first transparency electrode 41 is pixel electrode.Wherein, transparent with second
The second public electrode wire 63 that electrode 42 connects can reduce the resistance of second transparency electrode 42.
Second public electrode wire 63 (that is, public electrode) is arranged in array substrate, can increase by the embodiment of the present invention
The visual angle of display panel in liquid crystal display reduces power consumption.Wherein, by the second public electrode wire 63 and the first public electrode wire 62
Electrical connection, so that 42 equipotential of first transparency electrode 41 and second transparency electrode in virtual sub-pixel 20, avoids virtual subnet
The light leakage of pixel 20.
It is further preferred that the first public electrode wire 62, the second public electrode wire 63, grid line 61, the second public electrode wire
63 are formed by a patterning processes.
Based on above-mentioned, first transparency electrode 41 and the first public electrode wire 62 in virtual sub-pixel 20 can be by such as
Lower several ways realize electrical connection:
Mode one, as shown in Fig. 4 and Fig. 5 (a)-Fig. 5 (b), first transparency electrode 41 in virtual sub-pixel 20 with
First public electrode wire 62 is connected by via hole.
That is, the first transparency electrode 41 in virtual sub-pixel 20 is extended to 62 top of the first public electrode wire, so that empty
First transparency electrode 41 in quasi- sub-pixel 20 is connected with the first public electrode wire 62 by via hole.
Wherein, as shown in Fig. 5 (b), first transparency electrode 41 can be by being arranged on passivation layer 90 and gate insulation layer 80
Via hole is connected with the first public electrode wire 62.
Mode two, as shown in Fig. 6 (a) and Fig. 6 (b), first transparency electrode 41 in virtual sub-pixel 20 and virtually
Second transparency electrode 42 in sub-pixel 20 is connected by via hole.
Since second transparency electrode 42 is electrically connected with the second public electrode wire 63, and the second public electrode wire 63 and first is public
Common-battery polar curve 62 is electrically connected, therefore, by the in the first transparency electrode 41 and virtual sub-pixel 20 in virtual sub-pixel 20
Two transparent electrodes 42 pass through after via hole is connected first transparency electrode 41 and the first public electrode, it can be achieved that in virtual sub-pixel 20
The electrical connection of line 62.
Wherein, as shown in Fig. 6 (b), when second transparency electrode 42 and the first public electrode wire 62, the second public electrode wire
63, grid line 61 etc. is synchronous forms, and when the close setting of substrate 70, first transparency electrode 41 can be by being arranged in passivation layer 90 and grid
Via hole on insulating layer 80 is connected with second transparency electrode 42.
Mode three, the first transparency electrode 41 and second as shown in Fig. 7 (a) and Fig. 7 (b), in virtual sub-pixel 20
Public electrode wire 63 is connected by via hole.
Since the second public electrode wire 63 is electrically connected with the first public electrode wire 62, it will be in virtual sub-pixel 20
First transparency electrode 41 extends to the top of the second public electrode wire 63 so that the first transparency electrode 41 in virtual sub-pixel 20 with
Second public electrode wire 63 is connected by via hole, can realize first transparency electrode 41 in virtual sub-pixel 20 and first public
The electrical connection of electrode wires 62.
Wherein, as shown in Fig. 6 (b), when second transparency electrode 42 and the first public electrode wire 62, the second public electrode wire
63, grid line 61 etc. is synchronous forms, and when the close setting of substrate 70, first transparency electrode 41 can be by being arranged in passivation layer 90 and grid
Via hole on insulating layer 80 is connected with the second public electrode wire 63.
Based on above-mentioned preferred, the two sides along 50 direction of data line of viewing area 01 are arranged in virtual viewing area 02；Data
Line 50 extends to virtual viewing area 02 by viewing area 01.
In order to which the problem for keeping each etching edge homogeneity in viewing area 01 poor is improved, virtual viewing area 02 is also set
It sets in the two sides along 61 direction of grid line of viewing area 01, it at this time can be by source electrode 31 in virtual sub-pixel 20 and the second public electrode wire
63 electrical connections, to avoid the increase for causing data line 50 to load.
The embodiment of the present invention provides a kind of display panel, including above-mentioned array substrate.
The embodiment of the present invention provides a kind of display panel, virtual by being arranged on 01 periphery of the viewing area of the array substrate
Viewing area 02 can improve the poor problem of array substrate etching edge homogeneity.On this basis, by by virtual sub-pixel
Thin film transistor (TFT) 30 and data line 50 in 20 disconnect, and can avoid data line 50 and the thin film transistor (TFT) 30 in virtual sub-pixel 20
Between generate coupled capacitor, to reduce the load of data line 50, and then when array substrate is used for display device, can reduce
The power consumption of display device.
Preferably, the display panel further includes to box substrate；The setting of second transparency electrode 42 it is described to box substrate or
In the array substrate.
Wherein, described can also include black matrix to box substrate；Chromatic filter layer may be provided in box substrate, can also set
It sets in array substrate.
The embodiment of the present invention provides a kind of preparation method of array substrate, as shown in Figure 1, comprising: synchronous in viewing area 01
Sub-pixel 10 is formed, forms virtual sub-pixel 20 in the virtual viewing area 02 on 01 periphery of viewing area；Sub-pixel 10 and virtual subnet picture
The first transparency electrode 41 that element 20 includes thin film transistor (TFT) 30, is electrically connected with the drain electrode 32 of thin film transistor (TFT) 30；Wherein, it is located at
The source electrode 31 of thin film transistor (TFT) 30 in sub-pixel 10 is connect with data line 50；Thin film transistor (TFT) in virtual sub-pixel 20
30 source electrode 31 and data line 50 disconnects.
Preferably, the structure of virtual sub-pixel 20 is identical with the structure of sub-pixel 10, only will be in virtual sub-pixel 20
The source electrode 31 and data line 50 of thin film transistor (TFT) 30 disconnect.
The embodiment of the present invention provides a kind of preparation method of array substrate, by forming the same of sub-pixel 10 in viewing area 01
When, virtual sub-pixel is formed in virtual viewing area 02, the poor problem of array substrate etching edge homogeneity can be improved, and
It can avoid the increase of patterning processes.On this basis, by by virtual sub-pixel 20 thin film transistor (TFT) 30 and data line 50
It disconnects, can avoid generating coupled capacitor between the thin film transistor (TFT) 30 in data line 50 and virtual sub-pixel 20, to reduce
The load of data line 50, and then when array substrate is used for display device, the power consumption of display device can be reduced.
Optionally, as shown in Fig. 4 and Fig. 5 (a)-Fig. 5 (b), the grid of the thin film transistor (TFT) 30 in the sub-pixel
It is connected with grid line 61；The grid of thin film transistor (TFT) 30 in virtual sub-pixel 20 is electrically connected with the first public electrode wire 62；
Wherein, the first transparency electrode 41 in virtual sub-pixel 20 is connected with the first public electrode wire 62 by via hole.
Optionally, sub-pixel 10 and virtual sub-pixel 20 respectively further comprise second transparency electrode 42；Second transparency electrode 42
It is electrically connected with the second public electrode wire 63；Wherein, as shown in Fig. 6 (a) and Fig. 6 (b), first in virtual sub-pixel 20 is saturating
Prescribed electrode 41 is connected with the second transparency electrode 42 in virtual sub-pixel 20 by via hole.Alternatively, such as Fig. 7 (a) and Fig. 7 (b) institute
Show, the first transparency electrode 41 in virtual sub-pixel 20 is connected with the second public electrode wire 63 by via hole.
More than, by the grid of thin film transistor (TFT) 30 and first transparency electrode 41 that will be located in virtual sub-pixel 20 with
The electrical connection of first public electrode wire 62, makes 41 equipotential of grid and first transparency electrode, and then make thin in virtual sub-pixel 20
Source electrode 31, drain electrode 32 and the grid equipotential of film transistor 30, so as to avoid the generation of electrostatic.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (8)
1. a kind of array substrate, which is characterized in that including viewing area and the virtual viewing area that the viewing area periphery is arranged in；Institute
Stating viewing area includes sub-pixel, and the virtual viewing area includes virtual sub-pixel；
The sub-pixel and the virtual sub-pixel include thin film transistor (TFT), are electrically connected with the drain electrode of the thin film transistor (TFT)
First transparency electrode；
Wherein, the source electrode of the thin film transistor (TFT) in the sub-pixel is connect with data line；Positioned at the virtual subnet picture
The source electrode and the data line of the thin film transistor (TFT) in element disconnect；
The grid of the thin film transistor (TFT) in the sub-pixel is connected with grid line；
The grid of the thin film transistor (TFT) in the virtual sub-pixel is electrically connected with the first public electrode wire；
Wherein, the first transparency electrode in the virtual sub-pixel is electrically connected with first public electrode wire.
2. array substrate according to claim 1, which is characterized in that the sub-pixel and the virtual sub-pixel are also distinguished
Including second transparency electrode；
The second transparency electrode is electrically connected with the second public electrode wire；
Wherein, second public electrode wire is electrically connected with first public electrode wire.
3. array substrate according to claim 1, which is characterized in that described first in the virtual sub-pixel is saturating
Prescribed electrode is connected with first public electrode wire by via hole.
4. array substrate according to claim 2, which is characterized in that described first in the virtual sub-pixel is saturating
Prescribed electrode is connected with the second transparency electrode in the virtual sub-pixel by via hole；Alternatively,
The first transparency electrode in the virtual sub-pixel is connected with second public electrode wire by via hole.
5. a kind of display panel, which is characterized in that including the described in any item array substrates of claim 1-4.
6. a kind of display panel, which is characterized in that
Including viewing area and the virtual viewing area that the viewing area periphery is arranged in；The viewing area includes sub-pixel, the void
Quasi- viewing area includes virtual sub-pixel；
The sub-pixel and the virtual sub-pixel include thin film transistor (TFT), are electrically connected with the drain electrode of the thin film transistor (TFT)
First transparency electrode；
Wherein, the source electrode of the thin film transistor (TFT) in the sub-pixel is connect with data line；Positioned at the virtual subnet picture
The source electrode and the data line of the thin film transistor (TFT) in element disconnect；
The grid of the thin film transistor (TFT) in the sub-pixel is connected with grid line；
The grid of the thin film transistor (TFT) in the virtual sub-pixel is electrically connected with the first public electrode wire；
Wherein, the first transparency electrode in the virtual sub-pixel is electrically connected with first public electrode wire；Institute
It states sub-pixel and the virtual sub-pixel respectively further comprises second transparency electrode；
The second transparency electrode is electrically connected with the second public electrode wire；
Wherein, second public electrode wire is electrically connected with first public electrode wire；
It further include to box substrate；
Second transparency electrode is arranged described in box substrate.
7. a kind of preparation method of array substrate characterized by comprising it is synchronous to form sub-pixel in viewing area, described aobvious
Show that the virtual viewing area on area periphery forms virtual sub-pixel；
The sub-pixel and the virtual sub-pixel include thin film transistor (TFT), are electrically connected with the drain electrode of the thin film transistor (TFT)
First transparency electrode；
Wherein, the source electrode of the thin film transistor (TFT) in the sub-pixel is connect with data line；Positioned at the virtual subnet picture
The source electrode and the data line of the thin film transistor (TFT) in element disconnect；
The grid of the thin film transistor (TFT) in the sub-pixel is connected with grid line；
The grid of the thin film transistor (TFT) in the virtual sub-pixel is electrically connected with the first public electrode wire；
Wherein, the first transparency electrode in the virtual sub-pixel passes through via hole phase with first public electrode wire
Even.
8. preparation method according to claim 7, which is characterized in that the sub-pixel and the virtual sub-pixel are also distinguished
Including second transparency electrode；
The second transparency electrode is electrically connected with the second public electrode wire；
Wherein, described second in the first transparency electrode and the virtual sub-pixel in the virtual sub-pixel is saturating
Prescribed electrode is connected by via hole；Alternatively,
The first transparency electrode in the virtual sub-pixel is connected with second public electrode wire by via hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611015730.4A CN106356381B (en) | 2016-11-18 | 2016-11-18 | A kind of array substrate and preparation method thereof, display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611015730.4A CN106356381B (en) | 2016-11-18 | 2016-11-18 | A kind of array substrate and preparation method thereof, display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106356381A CN106356381A (en) | 2017-01-25 |
| CN106356381B true CN106356381B (en) | 2019-06-14 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107644879B (en) | 2017-09-19 | 2019-11-05 | 京东方科技集团股份有限公司 | Prepare method, array substrate, the display device of array substrate |
| CN107870493B (en) * | 2017-11-01 | 2021-06-04 | 厦门天马微电子有限公司 | Display panel and display device |
| CN109375439A (en) | 2018-12-20 | 2019-02-22 | 武汉华星光电技术有限公司 | Array substrate and display panel |
| JP7237649B2 (en) * | 2019-02-27 | 2023-03-13 | 株式会社ジャパンディスプレイ | Display device |
| CN209946604U (en) * | 2019-06-12 | 2020-01-14 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
| CN110718180B (en) * | 2019-11-15 | 2023-07-18 | 京东方科技集团股份有限公司 | Display substrate and manufacturing method thereof |
| CN112764281B (en) * | 2021-01-28 | 2021-11-23 | Tcl华星光电技术有限公司 | Array substrate and display panel |
| WO2024044933A1 (en) * | 2022-08-30 | 2024-03-07 | Boe Technology Group Co., Ltd. | Array substrate and display apparatus |
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| JPH07333654A (en) * | 1994-06-10 | 1995-12-22 | Sony Corp | Active matrix type liquid crystal display device |
| CN103018985A (en) * | 2012-11-26 | 2013-04-03 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN103116237A (en) * | 2011-11-16 | 2013-05-22 | 索尼公司 | Liquid crystal display panel and liquid crystal projector |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07333654A (en) * | 1994-06-10 | 1995-12-22 | Sony Corp | Active matrix type liquid crystal display device |
| CN103116237A (en) * | 2011-11-16 | 2013-05-22 | 索尼公司 | Liquid crystal display panel and liquid crystal projector |
| CN103018985A (en) * | 2012-11-26 | 2013-04-03 | 京东方科技集团股份有限公司 | Array substrate and display device |
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