CN102931235B - MOS transistor and manufacture method thereof - Google Patents
MOS transistor and manufacture method thereof Download PDFInfo
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- CN102931235B CN102931235B CN201110231903.7A CN201110231903A CN102931235B CN 102931235 B CN102931235 B CN 102931235B CN 201110231903 A CN201110231903 A CN 201110231903A CN 102931235 B CN102931235 B CN 102931235B
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Abstract
The invention provides a kind of MOS transistor and manufacture method thereof, by removing the light doping section of segment thickness immediately below grid structure or full depth, namely reduce even to eliminate this short-channel effect caused by part light doping section, even if thus form the darker source and drain extension of junction depth to reduce the series resistance of source and drain extension, also well can control short-channel effect, achieve the series resistance controlling short-channel effect simultaneously preferably and obtain less source and drain extension area.
Description
Technical field
The present invention relates to integrated circuit fabrication process, particularly a kind of MOS transistor and manufacture method thereof.
Background technology
Traditional MOS transistor comprises: Semiconductor substrate; Be positioned at the grid structure in described Semiconductor substrate, described grid structure exceeds described Semiconductor substrate; Be positioned at the source-drain area of described grid structure both sides, described source-drain area is arranged in described Semiconductor substrate.Along with semiconductor device is to high density and small size development, the size of MOS transistor is also more and more less, the channel length of MOS transistor is also shorter and shorter, thus, to be too close between the source-drain area depletion region of MOS transistor, thus cause occurring undesirable break-through (punchthrough) electric current, create short-channel effect (ShortChannelEffect, SCE).
Therefore, those skilled in the art adopts light doping section (LightlyDopedDrain usually, LDD) structure, form source and drain extension area, inject heavier Doped ions such as arsenic ion in source and drain extension area to form shallow junction (ShallowJunction), thus effectively control short-channel effect.As shown in Figure 1, it is the structural representation of existing MOS transistor.
As shown in Figure 1, MOS transistor 1 comprises: Semiconductor substrate 10; Be positioned at the grid structure 11 in described Semiconductor substrate 10, described grid structure 11 exceeds described Semiconductor substrate 10; Be positioned at the source and drain extension area 12 of described grid structure 11 both sides, described source and drain extension area 12 is arranged in described Semiconductor substrate 10; Be positioned at the sidewall structure 13 of described grid structure 11 both sides, described sidewall structure 13 exceeds described Semiconductor substrate 10; Be positioned at the source-drain area 14 of described sidewall structure 13 both sides, described source-drain area 14 is arranged in described Semiconductor substrate 10.
MOS transistor 1 as shown in Figure 1 controls short-channel effect preferably, but, due to the shallow junction of source and drain extension area 12, source and drain extension area 12 will be caused to have very large series resistance, the size of this series resistance and the junction depth negative correlation of source and drain extension area, namely junction depth is darker, and series resistance is less.In addition, due to the diffusion effect that Doped ions has, the source and drain extension area 12 being arranged in grid structure 11 both sides also can be spread in Semiconductor substrate 10, thus make part source and drain extension area 12 be positioned at immediately below grid structure 11, and this diffusion effect becomes positive correlation with the junction depth of source and drain extension area, namely the junction depth of source and drain extension area is darker, then source and drain extension area is larger to the diffusion immediately below grid structure 11, from and will larger short channel effect problem be produced.Therefore, in the prior art, compromise between short-channel effect (shallow junction) and the series resistance (junction depth is darker) obtaining less source and drain extension area can only controlled preferably.
Summary of the invention
The object of the present invention is to provide a kind of MOS transistor and manufacture method thereof, to solve in prior art, the problem of the series resistance controlling short-channel effect preferably and obtain less source and drain extension area can not be realized simultaneously.
For solving the problems of the technologies described above, the invention provides a kind of MOS transistor, comprising: Semiconductor substrate; Grid structure, comprise the first grid structure that is arranged in described Semiconductor substrate and be positioned at the structural second grid structure of described first grid, described second grid structure exceeds described Semiconductor substrate; Be positioned at the sidewall structure of described grid structure both sides, described sidewall structure exceeds Semiconductor substrate; Source and drain extension, is arranged in the Semiconductor substrate of described grid structure both sides; And source-drain area, be arranged in the Semiconductor substrate of described sidewall structure both sides.
Optionally, in described MOS transistor, the thickness of described first grid structure is 200 dust ~ 1500 dusts.
Optionally, in described MOS transistor, described grid structure comprises high-K dielectric layer and is arranged in the metal level of described high-K dielectric layer.
Optionally, in described MOS transistor, also comprise the metal silicide layer being positioned at described sidewall structure both sides, described metal silicide layer is positioned at the surface of described source and drain extension and described Semiconductor substrate.
The present invention also provides a kind of MOS transistor, comprising: Semiconductor substrate; Grid structure, comprise the first grid structure that is arranged in described Semiconductor substrate and be positioned at the structural second grid structure of described first grid, described second grid structure exceeds described Semiconductor substrate; Be positioned at the sidewall structure of described grid structure both sides, described sidewall structure exceeds described Semiconductor substrate; Source and drain extension, the second source and drain extension of the first source and drain extension comprising the Semiconductor substrate be arranged in immediately below grid structure and the Semiconductor substrate being arranged in grid structure both sides; Source-drain area, is arranged in the Semiconductor substrate of described sidewall structure both sides.
The present invention also provides a kind of manufacture method of MOS transistor, comprising: provide Semiconductor substrate, and described Semiconductor substrate is formed with dummy gate; With described dummy gate for mask, carry out ion implantation technology and form light doping section, described light doping section comprises the first light doping section and the second light doping section, described first light doping section is arranged in the Semiconductor substrate immediately below described dummy gate, and described second light doping section is arranged in the Semiconductor substrate of described dummy gate both sides; Form sidewall structure in described dummy gate both sides, described sidewall structure exceeds Semiconductor substrate; With described dummy gate and sidewall structure for mask, carry out ion implantation technology and form source-drain area; Remove described dummy gate, expose described Semiconductor substrate and the first light doping section; Remove the Semiconductor substrate exposed of segment thickness and the first light doping section of full depth, form source and drain extension, described source and drain extension comprises the second light doping section; Grid structure is formed in the position of described dummy gate, described grid structure comprises the first grid structure that is arranged in described Semiconductor substrate and is positioned at the structural second grid structure of described first grid, and described second grid structure exceeds described Semiconductor substrate.
Optionally, in the manufacture method of described MOS transistor, after formation source-drain area, before removing dummy gate, also comprise: form metal silicide layer in described sidewall structure both sides, described metal silicide layer is positioned at the surface of described source-drain area and Semiconductor substrate.
Optionally, after formation metal silicide layer, before removing dummy gate, also comprise: form the interlayer dielectric layer covering described metal silicide layer and sidewall structure.
Optionally, form grid structure to comprise the steps: to form high-K dielectric layer, the part semiconductor substrate that described high-K dielectric layer covers described interlayer dielectric layer, sidewall structure and exposes; Described high-K dielectric layer forms metal level; Utilize chemical mechanical milling tech to remove partial metal layers, form grid structure.
The present invention also provides a kind of manufacture method of MOS transistor, comprising: provide Semiconductor substrate, and described Semiconductor substrate is formed with dummy gate; With described dummy gate for mask, carry out ion implantation technology and form light doping section, described light doping section comprises the first light doping section and the second light doping section, described first light doping section is arranged in the Semiconductor substrate immediately below described dummy gate, and described second light doping section is arranged in the Semiconductor substrate of described dummy gate both sides; Form sidewall structure in described dummy gate both sides, described sidewall structure exceeds Semiconductor substrate; With described dummy gate and sidewall structure for mask, carry out ion implantation technology and form source-drain area in described sidewall structure both sides; Remove described dummy gate, expose described Semiconductor substrate and the first light doping section; Remove the Semiconductor substrate exposed of segment thickness and the first light doping section of segment thickness, form source and drain extension, described source and drain extension comprises the second light doping section and remaining first light doping section; Grid structure is formed in the position of described dummy gate, described grid structure comprises the first grid structure that is arranged in described Semiconductor substrate and is positioned at the structural second grid structure of described first grid, and described second grid structure exceeds in described Semiconductor substrate.
In MOS transistor provided by the invention and manufacture method thereof, by removing the light doping section of segment thickness immediately below grid structure or full depth, namely reduce even to eliminate this short-channel effect caused by part light doping section, even if thus form the darker source and drain extension of junction depth to reduce the series resistance of source and drain extension, also well can control short-channel effect, achieve the series resistance controlling short-channel effect simultaneously preferably and obtain less source and drain extension area.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing MOS transistor;
Fig. 2 is the structural representation of the MOS transistor of the embodiment of the present invention one;
Fig. 3 is the structural representation of the MOS transistor of the embodiment of the present invention two;
Fig. 4 a ~ 4n is the generalized section of the manufacture method of the MOS transistor of the embodiment of the present invention three.
Embodiment
The MOS transistor proposed the present invention below in conjunction with the drawings and specific embodiments and manufacture method thereof are described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Embodiment one
Please refer to Fig. 2, it is the structural representation of the MOS transistor of the embodiment of the present invention one.As shown in Figure 2, MOS transistor 2 comprises:
Semiconductor substrate 20;
Grid structure 21, comprises the first grid structure 210 being arranged in described Semiconductor substrate 20 and the second grid structure 211 be positioned in described first grid structure 210, and described second grid structure 211 exceeds described Semiconductor substrate 20;
Be positioned at the sidewall structure 23 of described grid structure 21 both sides, described sidewall structure 23 exceeds Semiconductor substrate 20;
Source and drain extension 22, is arranged in the Semiconductor substrate 20 of described grid structure 21 both sides; And
Source-drain area 24, is arranged in the Semiconductor substrate 20 of described sidewall structure 23 both sides.
In the above-mentioned MOS transistor 2 provided, source and drain extension 22 is only present in the both sides of grid structure 21, thus, even if the junction depth of source and drain extension 22 is deep to obtain less series resistance, the channel width formed is also by wide for the width (i.e. the thickness of grid structure 21 horizontal direction) at least than grid structure 21, well can control the problem of short-channel effect, achieve the series resistance controlling short-channel effect simultaneously preferably and obtain less source and drain extension area.
In the present embodiment, the thickness of described first grid structure 210 is 200 dust ~ 1500 dusts, the average injection ion depth of described source and drain extension 22 is 200 dust ~ 1000 dusts, certainly, in other embodiments of the invention, the thickness of described first grid structure 210 and described source and drain extension 22 also can be thicker or thinner.In addition, described grid structure 21 is made up of high K dielectric and metal material, and high K dielectric has higher dielectric constant and better field effect characteristic, can manufacture more high performance transistor by forming grid structure by high K dielectric and metal material.
Further, described MOS transistor 2 also comprises: metal silicide layer 25, and described metal silicide layer 25 is positioned at described sidewall structure 23 both sides, and is positioned at the surface of described source and drain extension 22 and described Semiconductor substrate 20.Source-drain area 24, ohmic contact between source and drain extension 22 and other structures (contact plunger etc. of follow-up formation) can be improved by described metal silicide layer 25.
Embodiment two
Please refer to Fig. 3, it is the structural representation of the MOS transistor of the embodiment of the present invention two.As shown in Figure 3, MOS transistor 3 comprises:
Semiconductor substrate 30;
Grid structure 31, comprises the first grid structure 310 being arranged in described Semiconductor substrate 30 and the second grid structure 311 be positioned in described first grid structure 310, and described second grid structure 311 exceeds described Semiconductor substrate 30;
Be positioned at the sidewall structure 33 of described grid structure 31 both sides, described sidewall structure 33 exceeds described Semiconductor substrate 30;
Source and drain extension 32, the second source and drain extension 321 of the first source and drain extension 320 comprising the Semiconductor substrate 30 be arranged in immediately below grid structure 31 and the Semiconductor substrate 30 being arranged in grid structure 31 both sides;
Source-drain area 34, is arranged in the Semiconductor substrate 30 of described sidewall structure 33 both sides.
The difference of the present embodiment and embodiment one is, in the present embodiment, the source and drain extension of the part of still old light dope formation immediately below described grid structure 31, but the MOS transistor that the present embodiment provides reasonablely can realize the series resistance controlling short-channel effect preferably and obtain less source and drain extension area equally simultaneously.
Concrete, known, due to the characteristic of ion implantation, namely the closer to the surface of Semiconductor substrate 30, then more be easy to carry out ion implantation, its ion concentration injected is also denseer, thus, carrying out light dope technique to be formed in the process of source and drain extension, diffusion effect the closer to the light doping section on Semiconductor substrate 30 surface is also more serious, namely the closer to Semiconductor substrate 30 surface, the light doping section immediately below grid structure 31 is larger, and it also determines the length of raceway groove.Therefore, in the present embodiment, although still have the first source and drain extension 320 immediately below grid structure 31, but near Semiconductor substrate 30 surface, short-channel effect is more significantly eliminated part light doping section, thus, when junction depth is identical, short-channel effect can be reduced better, reduce the series resistance of source and drain extension.
Embodiment three
Present embodiments provide the manufacture method of MOS transistor, comprising:
Semiconductor substrate is provided, described Semiconductor substrate is formed with dummy gate;
With described dummy gate for mask, carry out ion implantation technology and form light doping section, described light doping section comprises the first light doping section and the second light doping section, described first light doping section is arranged in the Semiconductor substrate immediately below described dummy gate, and described second light doping section is arranged in the Semiconductor substrate of described dummy gate both sides;
Form sidewall structure in described dummy gate both sides, described sidewall structure exceeds Semiconductor substrate;
With described dummy gate and sidewall structure for mask, carry out ion implantation technology and form source-drain area;
Remove described dummy gate, expose described Semiconductor substrate and the first light doping section;
Remove the Semiconductor substrate exposed of segment thickness and the first light doping section of full depth, form source and drain extension, described source and drain extension comprises the second light doping section;
Grid structure is formed in the position of described dummy gate, described grid structure comprises the first grid structure that is arranged in described Semiconductor substrate and is positioned at the structural second grid structure of described first grid, and described second grid structure exceeds described Semiconductor substrate.
Concrete, please refer to Fig. 4 a ~ 4n, it is the generalized section of the manufacture method of the MOS transistor of the embodiment of the present invention three.
As shown in fig. 4 a, first, provide Semiconductor substrate 40, described Semiconductor substrate 40 is such as silicon substrate;
As shown in Figure 4 b, then, described Semiconductor substrate 40 is formed polysilicon layer 4110 and silicon dioxide layer 4111, the thickness of described polysilicon layer 4110 can be 500 dust ~ 2000 dusts, the thickness of described silicon dioxide layer 4111 can be 50 dust ~ 500 dusts, in the present embodiment, chemical vapor deposition method can be utilized to form above-mentioned each layer;
As illustrated in fig. 4 c, etch described silicon dioxide layer 4111 and polysilicon layer 4110 successively, form dummy gate 4112;
As shown in figure 4d, described dummy gate 4112 is utilized to be mask, light dope ion implantation technology is carried out to described Semiconductor substrate 40, thus form light doping section 42, described light doping section 42 comprises: the first light doping section 420, described first light doping section 420 is positioned at immediately below described dummy gate 4112 and (namely refers to that the projection of dummy gate 4112 in Semiconductor substrate 40 can cover the first projection of light doping section 420 in Semiconductor substrate 40), and is arranged in described Semiconductor substrate 40; Second light doping section 421, described second light doping section 421 is positioned at described dummy gate 4112 both sides, and is arranged in described Semiconductor substrate 40;
In the present embodiment, the ion implantation degree of depth of described light doping section 42 is 100 dust ~ 500 dusts, and ion implantation energy is 1KeV ~ 5KeV, and ion implantation dosage is 5E14/cm
2~ 2E15/cm
2, certainly, in other embodiments of the invention, namely the described ion implantation degree of depth, ion implantation energy, ion implantation dosage also in above-mentioned scope, can not be greater than or less than the numerical value in above-mentioned scope.
As shown in fig 4e, form sidewall structure 43 in described dummy gate 4112 both sides, described sidewall structure 43 exceeds described Semiconductor substrate 40, certainly, the adjacent described dummy gate 4112 of described sidewall structure 43, described sidewall structure 43 can be silicon nitride, and its thickness can be 100 dust ~ 700 dusts;
As shown in fig. 4f, with described dummy gate 4112 and sidewall structure 43 for mask, form source-drain area 44 in described sidewall structure 43 both sides, described source-drain area 44 is arranged in described Semiconductor substrate 40;
As shown in figure 4g, utilize self-registered technology, metal silicide layer 45 is formed in described sidewall structure 43 both sides, described metal silicide layer 45 is positioned at the surface of described source and drain extension 42 and Semiconductor substrate 40, can improve source-drain area 44, ohmic contact between source and drain extension 42 and other structures (contact plunger etc. of follow-up formation) by described metal silicide layer 45, described metal silicide layer 45 can be the metal silicide of titanium or cobalt;
As shown in figure 4h, form interlayer dielectric layer 4113, described interlayer dielectric layer 4113 covers described metal silicide layer 45, sidewall structure 43 and dummy gate 4112;
As shown in figure 4i, utilize chemical mechanical milling tech removal unit to divide interlayer dielectric layer, expose dummy gate 4112;
As shown in figure 4j, remove described dummy gate 4112, expose Semiconductor substrate 40 and the first light doping section 420, at this, protect described metal silicide layer 45 and sidewall structure 43 by remaining interlayer dielectric layer 4113 ';
As shown in fig. 4k, remove the Semiconductor substrate 40 exposed of segment thickness and the first light doping section 420 of full depth, form source and drain extension 42 ', certainly, described source and drain extension 42 ' namely comprises the second light doping section 421;
As shown in Fig. 4 l, form high-K dielectric layer 4114, the part semiconductor substrate 40 that described high-K dielectric layer 4114 covers remaining interlayer dielectric layer 4113 ', sidewall structure 43 and exposes;
As shown in Fig. 4 m, described high-K dielectric layer 4114 forms metal level 4115;
Finally, as shown in Fig. 4 n, utilize chemical mechanical milling tech to remove partial metal layers, form grid structure 41, described grid structure 41 is made up of high-K dielectric layer and metal material.
The grid structure 41 formed by said method, being comprised: first grid structure 410, and described first grid structure 410 is arranged in described Semiconductor substrate 40; Second grid structure 411, described second grid structure 411 is positioned in described first grid structure 410, and exceeds described Semiconductor substrate 40.Thus the MOS transistor formed can realize the series resistance controlling short-channel effect preferably and obtain less source and drain extension area simultaneously.
Embodiment four
Semiconductor substrate is provided, described Semiconductor substrate is formed with dummy gate;
With described dummy gate for mask, carry out ion implantation technology and form light doping section, described light doping section comprises the first light doping section and the second light doping section, described first light doping section is arranged in the Semiconductor substrate immediately below described dummy gate, and described second light doping section is arranged in the Semiconductor substrate of described dummy gate both sides;
Form sidewall structure in described dummy gate both sides, described sidewall structure exceeds Semiconductor substrate;
With described dummy gate and sidewall structure for mask, carry out ion implantation technology and form source-drain area in described sidewall structure both sides;
Remove described dummy gate, expose described Semiconductor substrate and the first light doping section;
Remove the Semiconductor substrate exposed of segment thickness and the first light doping section of segment thickness, form source and drain extension, described source and drain extension comprises the second light doping section and remaining first light doping section;
Grid structure is formed in the position of described dummy gate, described grid structure comprises the first grid structure that is arranged in described Semiconductor substrate and is positioned at the structural second grid structure of described first grid, and described second grid structure exceeds in described Semiconductor substrate.
The difference of the present embodiment and embodiment three is, when performing the step of Fig. 4 k in corresponding embodiment three, in the present embodiment, eliminate the Semiconductor substrate exposed of segment thickness and the first light doping section of segment thickness, form source and drain extension, namely formed source and drain extension comprises the second light doping section and remaining part first light doping section, same, the MOS transistor formed can realize the series resistance controlling short-channel effect simultaneously preferably and obtain less source and drain extension area.
Foregoing description is only the description to present pre-ferred embodiments, any restriction not to the scope of the invention, and any change that the those of ordinary skill in field of the present invention does according to above-mentioned disclosure, modification, all belong to the protection range of claims.
Claims (1)
1. a manufacture method for MOS transistor, is characterized in that, comprising:
Semiconductor substrate is provided, described Semiconductor substrate is formed with dummy gate;
With described dummy gate for mask, carry out ion implantation technology and form light doping section, described light doping section comprises the first light doping section and the second light doping section, described first light doping section is arranged in the Semiconductor substrate immediately below described dummy gate, and described second light doping section is arranged in the Semiconductor substrate of described dummy gate both sides;
Form sidewall structure in described dummy gate both sides, described sidewall structure exceeds Semiconductor substrate;
With described dummy gate and sidewall structure for mask, carry out ion implantation technology and form source-drain area in described sidewall structure both sides;
Remove described dummy gate, expose described Semiconductor substrate and the first light doping section;
Remove the Semiconductor substrate exposed of segment thickness and the first light doping section of segment thickness, form source and drain extension, described source and drain extension comprises the second light doping section and remaining first light doping section;
Grid structure is formed in the position of described dummy gate, described grid structure comprises the first grid structure that is arranged in described Semiconductor substrate and is positioned at the structural second grid structure of described first grid, and the second light doping section of described source and drain extension is separated by described first grid structure, described second grid structure exceeds in described Semiconductor substrate.
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| CN102931235B true CN102931235B (en) | 2016-02-17 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1551311A (en) * | 2003-05-14 | 2004-12-01 | ���ǵ�����ʽ���� | MOS transistor with elevated source/drain structure and method of fabricating the same |
| CN101030602A (en) * | 2007-04-06 | 2007-09-05 | 上海集成电路研发中心有限公司 | MOS transistor for decreasing short channel and its production |
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| JP5640379B2 (en) * | 2009-12-28 | 2014-12-17 | ソニー株式会社 | Manufacturing method of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1551311A (en) * | 2003-05-14 | 2004-12-01 | ���ǵ�����ʽ���� | MOS transistor with elevated source/drain structure and method of fabricating the same |
| CN101030602A (en) * | 2007-04-06 | 2007-09-05 | 上海集成电路研发中心有限公司 | MOS transistor for decreasing short channel and its production |
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