CN102931093B - N-channel depletion type power MOSFET device and manufacture method - Google Patents
N-channel depletion type power MOSFET device and manufacture method Download PDFInfo
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Abstract
The present invention provides a kind of N-channel depletion type power MOSFET device and manufacture method, described manufacture method includes, and carries out ion implanting and annealing process, to form P type trap zone in the active area between described grid, and carrying out between ion implanting and the step of annealing process, carrying out oxidation technology；And carry out Electron irradiation technology, to form depletion layer between two source regions mutually closed in two adjacent P type trap zone, by Electron irradiation technology, the electronics being produced by electron irradiation forms electronic conduction raceway groove in the silicon face of device, form depletion layer, also the MOSFET element making formation has shorter reverse recovery time, and then improves the performance of product；Meanwhile, the method increasing Electron irradiation technology is mutually compatible with the manufacturing process of ordinary power MOSFET element, does not need to increase single version to carry out Channeling implantation technique, and then saves processing step, and improve production efficiency reduces production cost.
Description
Technical field
The present invention relates to a kind of semiconductor device and its manufacture method, more particularly, to a kind of N-channel depletion type power
MOSFET element and manufacture method.
Background technology
MOSFET (mos field effect transistor) can be divided into enhancement mode and depletion type, wherein enhancement mode
Refer to that pipe is in cut-off state, and after plus suitable VGS, majority carrier is attracted to when VGS (gate source voltage) is 0
Grid, so that the carrier under polycrystalline grid strengthens, forms conducting channel, this metal-oxide-semiconductor is referred to as enhancement mode metal-oxide-semiconductor.Exhaust
Type refers to as VGS=0, that is, there is raceway groove, when adding suitable VGS, majority carrier can be made to flow out raceway groove, carrier depletion
Pipe turns to cut-off.In VGS=0, the raceway groove between drain-source has existed N-channel depletion type power MOSFET, as long as so adding
Upper VDS (drain-source voltage), just has ID (electric current) to circulate.If increasing positive gate source voltage VGS, the electric field between grid and substrate
To make to sense more electronics in raceway groove, raceway groove is thickening, the conductance of raceway groove increases.If in grid plus negative voltage, i.e. VGS ＜ 0,
Positive charge will be induced in corresponding device surface, these positive charges offset the electronics in N-channel, thus producing in substrate surface
A raw depletion layer, makes raceway groove narrow, and channel conduction reduces.When minus gate voltage increases to a certain voltage Vp, depletion region expands to
Whole raceway groove, raceway groove, completely by pinch off (exhausting), even if at this moment VDS still suffers from, also will not produce drain current, i.e. ID=0.
Then Vp is referred to as pinch-off voltage or threshold voltage, and its value is generally between -1V～-10V.General making depletion type MOS FET technique side
Method is individually to carry out primary ions in channel region to inject to form raceway groove.
The performance how improving MOSFET element further becomes the problem of industry concern.
Content of the invention
It is an object of the invention to provide a kind of, that N-channel depletion type power MOSFET device can be made to have is shorter reversely extensive
The structure of multiple time and manufacture method.
The present invention provides a kind of manufacture method of N-channel depletion type power MOSFET device, including：
Semiconductor substrate is provided, and forms epitaxial layer on the semiconductor substrate, described epitaxial layer includes partial pressure annular
Become area and active area；
Carry out ion field injection technology and annealing process in described active area, to form ion field injection region；
Grid is formed on described active area；
Carry out ion implanting and annealing process, to form P type trap zone in the active area between described grid, and entering
Between row ion implanting and the step of annealing process, carry out oxidation technology；
Form p-type contact area and the N+ source region on p-type contact area side in described P type trap zone；And
Electron irradiation technology is carried out to described Semiconductor substrate, with two N+ mutually closing in two adjacent P type trap zone
Form depletion layer between source region.
Further, described Semiconductor substrate and described epitaxial layer are N-type.
Further, carry out in ion field injection technology and the step of annealing process in described active area, carry out phosphorus from
The field injection technology of son, to form phosphonium ion field injection region, Implantation Energy is 60～180KEV.
Further, carry out in ion field injection technology and the step of annealing process in described active area, described annealing
The annealing temperature of technique is 1100 DEG C～1200 DEG C, and annealing time is 60～180 minutes.
Further, the step forming grid on described active area includes：Gate oxide is formed on described active area；
Deposit polycrystalline silicon layer on described gate oxide；Photoetching and etching are carried out to described polysilicon layer, to form grid conductive layer.
Further, the thickness of described gate oxide is 4000 angstroms～8000 angstroms.
Further, in formation of deposits polysilicon layer and the step forming grid conductive layer between, also include, to described polycrystalline
Silicon layer carries out ion doping.
Further, in the step that ion doping is carried out to described polysilicon layer, using phosphorus oxychloride diffusion or phosphorus from
Son injection.
Further, in the step forming P type trap zone, using boron ion injection, Implantation Energy is 60～180KEV, note
Entering dosage is 1.0E12～5.0E13.
Further, in the step forming P type trap zone, the oxidizing temperature of described oxidation technology is 1000 DEG C～1100
DEG C, oxidization time is 60～180 minutes.
Further, in the step forming P type trap zone, described annealing process is in 1000 DEG C～1150 DEG C of nitrogen atmosphere
In annealed, annealing time be 60～180 minutes.
Further, the forming step of described p-type contact area includes：Carry out boron ion injection, Implantation Energy be 60～
150KEV, implantation dosage is 1E15～1E16；Carry out annealing process, annealing temperature is 800 DEG C～1000 DEG C, annealing time is 30
～180 minutes.
Further, the forming process of described N+ source region includes：Carry out arsenic ion injection, Implantation Energy be 60～
150KEV, implantation dosage is 1E15～2E16；Carry out annealing process, 800 DEG C～1000 DEG C, annealing time is 30～180 minutes.
Further, in the step carrying out Electron irradiation technology, irradiation energy is 1MeV～10MeV, and dosage is 1Mrad
~50Mrad.
Further, formed between p-type contact area, the step of N+ source region and the processing step carrying out electron irradiation, also
Including blanket dielectric layer on said epitaxial layer there；Form fairlead window in described dielectric layer；Described dielectric layer is carried out
Front metal metallization processes, to form front metal lead.
Further, the material of described dielectric layer is boron-phosphorosilicate glass.
Further, after carrying out the step of Electron irradiation technology, also include, the back side is carried out to described Semiconductor substrate
Thinning and back side metallization technology, and annealed in vacuum alloying furnace, wherein annealing temperature is 250 DEG C～360 DEG C, annealing
Time is 30～90 minutes.
The present invention also provides a kind of N-channel depletion type power MOSFET device, including：Semiconductor substrate and being located at thereon
Epitaxial layer, described epitaxial layer includes potential dividing ring and forms area and active area；Grid, is formed on described active area；P type trap zone, shape
Cheng Yu is in the active area between described grid；P-type contact area and the N+ source region on p-type contact area side, are both formed in described p-type trap
Qu Zhong；Also include depletion layer, described depletion layer is formed between the two N+ source regions mutually close in adjacent two P type trap zone.
Further, described Semiconductor substrate and described epitaxial layer are N-type.
Further, described grid includes：Gate oxide, is formed on described active area；Grid conductive layer, is formed at described
On gate oxide.
Further, the thickness of described gate oxide is 4000 angstroms～8000 angstroms.
Further, N-channel depletion type power MOSFET device also includes, dielectric layer, is covered on described epitaxial layer；Draw
String holes window, is formed in described dielectric layer；Front metal lead, is formed on described dielectric layer.
Further, the material of described dielectric layer is boron-phosphorosilicate glass.
Further, described N-channel depletion type power MOSFET device also includes, metal layer on back, described back metal
Layer is formed at relative with described epitaxial layer one side in described Semiconductor substrate.
In sum, the manufacture method of N-channel depletion type power MOSFET device of the present invention, by power
During MOSFET processing technology, in the active area between described grid formed P type trap zone during, and carry out from
Between son injection and the step of annealing process, carry out oxidation technology, described oxidation technology makes epi-layer surface form silicon dioxide
With the interface of silicon, thus in the step subsequently carrying out Electron irradiation technology, make the boundary of silicon dioxide in device and silicon
Produce defect and trap in face and its neighbouring silicon dioxide layer, by suitable Electron irradiation technology, produced by electron irradiation
Electronics device silicon face formed electronic conduction raceway groove, that is, formed depletion layer so that hole depletion produce N-channel consumption
Type power MOSFET device to the greatest extent, makes the MOSFET element of formation have shorter reverse recovery time, and then improves product
Performance.
Simultaneously because adopting Electron irradiation technology, the structure cell forming process of N-channel depletion type power MOSFET device
Consistent with conventional process it is not necessary to individually increase version to adjust channel dopant dosage, meanwhile, the method that increases Electron irradiation technology
Mutually compatible with the manufacturing process of ordinary power MOSFET element, and then increased technological flexibility, save technological process and life
Produce cost.
The structure of N-channel depletion type power MOSFET device of the present invention is passed through to form depletion layer, described depletion layer shape
Become between the two N+ source regions mutually closed in adjacent two P type trap zone, so that the MOSFET element of formation is had shorter reverse
Recovery time, and then improve the performance of product.
Brief description
Fig. 1 is the schematic flow sheet of the manufacture method of N-channel depletion type power MOSFET device in one embodiment of the invention.
Fig. 2～Fig. 7 is that the structure of the manufacture process of N-channel depletion type power MOSFET device in one embodiment of the invention is shown
It is intended to.
Specific embodiment
For making present disclosure more clear understandable, below in conjunction with Figure of description, present disclosure is made into one
Step explanation.Certainly the invention is not limited in this specific embodiment, the general replacement known to those skilled in the art
Cover within the scope of the present invention.
Secondly, the present invention has carried out detailed statement using schematic diagram, when describing present example in detail, for the ease of saying
Bright, schematic diagram, should not be in this, as limitation of the invention not according to general ratio partial enlargement.
Fig. 1 is the schematic flow sheet of the manufacture method of N-channel depletion type power MOSFET device in one embodiment of the invention.
The present invention provides a kind of manufacture method of N-channel depletion type power MOSFET device, comprises the following steps：
Step S101：Semiconductor substrate is provided, and forms epitaxial layer on the semiconductor substrate, described epitaxial layer includes
Potential dividing ring forms area and active area；
Step S102：Carry out ion field injection technology and annealing process in described active area, to reduce conducting resistance；
Step S103：Grid is formed on described active area；
Step S104：Carry out ion implanting and annealing process, to form p-type trap in the active area between described grid
Area, and carrying out between ion implanting and the step of annealing process, carry out oxidation technology；
Step S105：Form p-type contact area and the N+ source region on p-type contact area side in described P type trap zone；And
Step S106：Carry out Electron irradiation technology, between the two N+ source regions mutually closed in two adjacent P type trap zone
Form depletion layer.
Fig. 2～Fig. 7 is that the structure of the manufacture process of N-channel depletion type power MOSFET device in one embodiment of the invention is shown
It is intended to.Below in conjunction with Fig. 1～Fig. 7, describe the manufacture method of N-channel depletion type power MOSFET device of the present invention in detail.
As shown in Fig. 2 in step S101, described Semiconductor substrate 10 and described epitaxial layer 12 are N-type.Wherein preferably
Select heavily doped N-type<100>The Semiconductor substrate 100 in crystal orientation direction, grows the outer of one layer of N-type in described Semiconductor substrate 100
Prolong layer 12, concrete epitaxial layer 12 thickness and resistivity specification are pressure and conducting resistance specification is specifically selected according to product.Described outer
Prolong floor 12 and include potential dividing ring formation area 100 and active area 200, then formed in area 100 in described potential dividing ring and form p-type ring 1-1,
And form formation field oxide 1-2 in area 100 in the potential dividing ring around described p-type ring 1-1.
Then, as shown in figure 3, in step s 102, ion field injection technology and annealing are carried out in described active area 200
Technique, forms in order to reduce the field injection region 3 of conducting resistance, specifically, carries out the field injection technology of phosphonium ion, preferably inject
Energy is 60～180KEV, and described phosphonium ion field injection region 3 can reduce the conducting resistance of device further, improves the property of device
Energy.In preferred embodiment, carry out in described active area 200 in ion field injection technology and the step of annealing process, institute
The annealing temperature stating annealing process is 1100 DEG C～1200 DEG C, and annealing time is 60～180 minutes.
Then as shown in figure 4, in step s 103, grid 4 is formed on described active area 200, described grid 4 includes grid
Oxide layer 4-1 and grid conductive layer 4-2, the step forming grid 4 on described active area 200 specifically includes：In described active area
Form gate oxide 4-1 on 200；Deposit polycrystalline silicon layer (in figure does not indicate) on described gate oxide 4-1；To described polysilicon
Layer carries out photoetching and etching, to form grid conductive layer 4-2.Wherein, described gate oxide 4-1 preferably thickness be 4000 angstroms～
8000 angstroms.Formation of deposits polysilicon layer and formed grid conductive layer step between, also include described polysilicon layer is carried out from
Son doping, carries out, to polysilicon layer, the performance that ion doping can improve the grid conductive layer being subsequently formed.Wherein, preferably trichlorine
Oxygen phosphorus (POCL3) diffusion or phosphonium ion injection.
In conjunction with Fig. 5, in step S104, carry out ion implanting and annealing process, with the active area between described grid
Form P type trap zone 5 in 200, and carrying out between ion implanting and the step of annealing process, carry out oxidation technology, wherein exist
Formed in the step of P type trap zone 5, can be using boron ion injection, Implantation Energy is 60～180KEV, and implantation dosage is 1.0E12
～5.0E13.Further, in the step forming P type trap zone 5, the oxidizing temperature of described oxidation technology is 1000 DEG C～1100
DEG C, oxidization time is 60～180 minutes.Further, in the step forming P type trap zone 5, described annealing process is at 1000 DEG C
Annealed in～1150 DEG C of nitrogen atmosphere, annealing time is 60～180 minutes.
With continued reference to Fig. 5, in step S105, formed by p-type contact area 6 and p-type contact area 6 in described P type trap zone 5
N+ source region 7, described N+ source region 7 be N-type heavy doping source region.Further, the forming step of described p-type contact area 6 includes：
Carry out boron ion injection, Implantation Energy is 60～150KEV, implantation dosage is 1E15～1E16；Then carry out annealing process, move back
Fiery temperature is 800 DEG C～1000 DEG C, and annealing time is 30～180 minutes.And the forming process of described N+ source region 7 includes：Carry out
Arsenic ion injects, and Implantation Energy is 60～150KEV, and implantation dosage is 1E15～2E16；Then carry out annealing process, 800 DEG C～
1000 DEG C, annealing time is 30～180 minutes.
As shown in fig. 6, carrying out electricity in the formation p-type contact area 6 of step S105, the step of N+ source region 7 and step S106
Between the processing step of sub- irradiation, also include, blanket dielectric layer 8 on described epitaxial layer 12；Then, in described dielectric layer 8
Form fairlead window；Described dielectric layer 8 carries out front-side metallization technique, to form front metal lead 9, described metal
Described p-type contact area 6 is drawn by lead 9 by fairlead window.The material of described dielectric layer is preferably boron-phosphorosilicate glass.
With continued reference to Fig. 6, in step s 106, carry out Electron irradiation technology, with phase in two adjacent P type trap zone 7
Form depletion layer 13 between the two N+ source regions closed on.Further, in the step carrying out Electron irradiation technology, irradiation energy is
1MeV～10MeV, dosage is 1Mrad～50Mrad (Megarad).Electron irradiation (Electron irradiation) is exactly to adopt
Irradiate material with high-power electron beam, to improve a kind of technology of material property.In microelectric technique, electron irradiation is use
High energy electron irradiates quasiconductor to realize controlling the purpose of minority carrier lifetime.Because high-energy electron irradiation can cause crystal former
Sub- displacement and produce the complex centre of deep energy level, therefore electron irradiation can be used to control carrier lifetime.For example, electron irradiation can
Produce two energy levels in silicon, one is acceptor type energy level in the above 0.4eV of top of valence band, and another is below conduction band bottom
The donor-type energy level of 0.36eV.
Thereafter, as shown in fig. 7, after the step carrying out Electron irradiation technology of step S106, also including, to described half
Conductor substrate 10 carries out thinning back side and back side metallization technology, with the back side in described Semiconductor substrate, and in vacuum alloy
Annealed in stove, wherein annealing temperature be 250 DEG C～360 DEG C, annealing time be 30～90 minutes, that is, with described epitaxial layer
Form metal layer on back 14 in the relative one side that is located.
In sum, the manufacture method of N-channel depletion type power MOSFET device of the present invention, by power
During MOSFET processing technology, in the active area between described grid formed P type trap zone during, and carry out from
Between son injection and the step of annealing process, carry out oxidation technology, described oxidation technology makes epi-layer surface form silicon dioxide
With the interface of silicon, thus in the step subsequently carrying out Electron irradiation technology, make the boundary of silicon dioxide in device and silicon
Defect and trap is produced, Electron irradiation technology can inspire electronics in silica in face and its neighbouring silicon dioxide layer
Hole pair, electronics migrates out silicon dioxide quickly and enters silicon face, and a hole part is also migrated out silicon dioxide, and a part of
Positive electric charge is become by the hole trap capture in silicon dioxide.By suitable Electron irradiation technology, produced by electron irradiation
Electronics device silicon face formed electronic conduction raceway groove, i.e. depletion layer, so that hole depletion produces N-channel depletion type
Power MOSFET device, and combine oxidation technology, can further improve the combination of depletion layer, so that formed
MOSFET element has shorter reverse recovery time, and then improves the performance of product.
Simultaneously because adopting Electron irradiation technology, the structure cell forming process of N-channel depletion type power MOSFET device
Consistent with conventional process it is not necessary to individually increase version to adjust channel dopant dosage, meanwhile, the method that increases Electron irradiation technology
Mutually compatible with the manufacturing process of ordinary power MOSFET element, and then increased technological flexibility, save technological process and life
Produce cost.
In conjunction with Fig. 7, the present invention also provides a kind of N-channel depletion type power MOSFET device, including：Semiconductor substrate 10 He
It is located at epitaxial layer 12 thereon, described epitaxial layer 12 includes potential dividing ring and forms area 100 and active area 200；Grid 4, is formed at institute
State on active area 200；P type trap zone 5, is formed in the active area 200 between described grid 4；P-type contact area 6 contacts with p-type
The other N+ source region 7 in area 6, is both formed in described P type trap zone 5；Also include depletion layer 13, described depletion layer 13 is formed at adjacent
Between the two N+ source regions 7 mutually closed in two P type trap zone 5.
The structure of described N-channel depletion type power MOSFET device is passed through to form depletion layer, and described depletion layer is formed at phase
Between the two N+ source regions 7 mutually closed in two adjacent P type trap zone, when making the MOSFET element of formation have shorter Reverse recovery
Between, and then improve the performance of product.
In preferred embodiment, described Semiconductor substrate 10 and described epitaxial layer 12 are N-type.Described grid 4 includes：Grid
Oxide layer 4-1, is formed on described active area 200；Grid conductive layer 4-2, is formed on described gate oxide 4-1.Further,
Described gate oxide 4-1 preferably thickness is 4000 angstroms～8000 angstroms.In preferred embodiment, described N-channel depletion type work(
Rate MOSFET element also includes, dielectric layer 8, fairlead window and front metal lead 9, and described dielectric layer 8 is covered in described outer
Prolong on layer；Described fairlead window is formed in described dielectric layer 8；Described front metal lead 9 is formed at described dielectric layer 8
On.Wherein said dielectric layer 8 preferably material is boron-phosphorosilicate glass.N-channel depletion type power MOSFET device of the present invention
Can be formed using previous building methods.
In preferred embodiment, metal layer on back 14, described metal layer on back 14 is formed at described Semiconductor substrate 10
The upper one side relative with described epitaxial layer 12.The signal that described metal layer on back 14 is used for Semiconductor substrate 10 back side is drawn.
Although the present invention is disclosed above with preferred embodiment, so it is not limited to the present invention, any affiliated technology
Has usually intellectual, without departing from the spirit and scope of the present invention, when a little change and retouching can be made, therefore in field
Protection scope of the present invention ought be defined depending on those as defined in claim.
Claims (24)
1. a kind of manufacture method of N-channel depletion type power MOSFET device, including：
Semiconductor substrate is provided, and forms epitaxial layer on the semiconductor substrate, described epitaxial layer includes potential dividing ring and forms area
And active area；
Carry out ion field injection technology and annealing process in described active area, to form ion field injection region；
Grid is formed on described active area；
Carry out ion implanting and annealing process, to form P type trap zone in the ion field injection region between described grid, and
Carry out between ion implanting and the step of annealing process, carry out oxidation technology；
Form p-type contact area and the N+ source region on p-type contact area side in described P type trap zone；
Electron irradiation technology is carried out to described Semiconductor substrate, with the two N+ source regions mutually closed in two adjacent P type trap zone
Between ion field injection region in formed depletion layer.
2. the manufacture method of N-channel depletion type power MOSFET device as claimed in claim 1 is it is characterised in that described half
Conductor substrate and described epitaxial layer are N-type.
3. the manufacture method of N-channel depletion type power MOSFET device as claimed in claim 1 is it is characterised in that described
Carry out in active area carrying out the field injection technology of phosphonium ion in ion field injection technology and the step of annealing process, to form phosphorus
Ion field injection region, Implantation Energy is 60～180KEV.
4. the manufacture method of N-channel depletion type power MOSFET device as claimed in claim 1 is it is characterised in that described
Carry out in ion field injection technology and the step of annealing process in active area, the annealing temperature of described annealing process is 1100 DEG C～
1200 DEG C, annealing time is 60～180 minutes.
5. the manufacture method of N-channel depletion type power MOSFET device as claimed in claim 1 is it is characterised in that described
The step forming grid on active area includes：
Gate oxide is formed on described active area；
Deposit polycrystalline silicon layer on described gate oxide；
Photoetching and etching are carried out to described polysilicon layer, to form grid conductive layer.
6. the manufacture method of N-channel depletion type power MOSFET device as claimed in claim 5 is it is characterised in that described grid
The thickness of oxide layer is 4000 angstroms～8000 angstroms.
7. the manufacture method of N-channel depletion type power MOSFET device as claimed in claim 6 is it is characterised in that depositing
Formed between polysilicon layer and the step forming grid conductive layer, also include, ion doping is carried out to described polysilicon layer.
8. the manufacture method of N-channel depletion type power MOSFET device as claimed in claim 7 is it is characterised in that to institute
State in the step that polysilicon layer carries out ion doping, using phosphorus oxychloride diffusion or phosphonium ion injection.
9. the manufacture method of N-channel depletion type power MOSFET device as claimed in claim 1 is it is characterised in that forming P
In the step of type well region, using boron ion injection, Implantation Energy is 60～180KEV, and implantation dosage is 1.0E12～5.0E13.
10. the manufacture method of N-channel depletion type power MOSFET device as claimed in claim 1 is it is characterised in that forming
In the step of P type trap zone, the oxidizing temperature of described oxidation technology is 1000 DEG C～1100 DEG C, and oxidization time is 60～180 minutes.
The manufacture method of 11. N-channel depletion type power MOSFET device as claimed in claim 1 is it is characterised in that forming
In the step of P type trap zone, described annealing process is annealed in 1000 DEG C～1150 DEG C of nitrogen atmosphere, and annealing time is 60
～180 minutes.
The manufacture method of 12. N-channel depletion type power MOSFET device as claimed in claim 1 is it is characterised in that described P
The forming step of type contact area includes：
Carry out boron ion injection, Implantation Energy is 60～150KEV, implantation dosage is 1E15～1E16；
Carry out annealing process, annealing temperature is 800 DEG C～1000 DEG C, annealing time is 30～180 minutes.
The manufacture method of 13. N-channel depletion type power MOSFET device as claimed in claim 1 is it is characterised in that described N+
The forming process of source region includes：
Carry out arsenic ion injection, Implantation Energy is 60～150KEV, implantation dosage is 1E15～2E16；
Carry out annealing process, 800 DEG C～1000 DEG C, annealing time is 0～180 minute.
The manufacture method of 14. N-channel depletion type power MOSFET device as claimed in claim 1 is it is characterised in that carrying out
In the step of Electron irradiation technology, irradiation energy is 1MeV～10MeV, and dosage is 1Mrad～50Mrad.
The manufacture method of 15. N-channel depletion type power MOSFET device as claimed in claim 1 is it is characterised in that forming
Between p-type contact area, the step of N+ source region and the processing step carrying out electron irradiation, also include,
Blanket dielectric layer on said epitaxial layer there；
Form fairlead window in described dielectric layer；
Front-side metallization technique is carried out on described dielectric layer, to form front metal lead.
The manufacture method of 16. N-channel depletion type power MOSFET device as claimed in claim 15 is it is characterised in that described
The material of dielectric layer is boron-phosphorosilicate glass.
The manufacture method of 17. N-channel depletion type power MOSFET device as claimed in claim 1 is it is characterised in that carrying out
After the step of Electron irradiation technology, also include,
Thinning back side and back side metallization technology are carried out to described Semiconductor substrate, and is annealed in vacuum alloying furnace, its
Middle annealing temperature is 250 DEG C～360 DEG C, and annealing time is 30～90 minutes.
A kind of 18. N-channel depletion type power MOSFET device, are formed using the method for claim 1, including：
Semiconductor substrate and be located at epitaxial layer thereon, described epitaxial layer includes potential dividing ring and forms area and active area；
Grid, is formed on described active area；
P type trap zone, is formed in the active area between described grid；
P-type contact area and the source region on p-type contact area side, are both formed in described P type trap zone；It is characterized in that, also include
Depletion layer, described depletion layer is formed between the two N+ source regions mutually close in adjacent two P type trap zone.
19. N-channel depletion type power MOSFET device as claimed in claim 18 are it is characterised in that described Semiconductor substrate
It is N-type with described epitaxial layer.
20. N-channel depletion type power MOSFET device as claimed in claim 18 are it is characterised in that described grid includes：
Gate oxide, is formed on described active area；
Grid conductive layer, is formed on described gate oxide.
21. N-channel depletion type power MOSFET device as claimed in claim 20 are it is characterised in that described gate oxide
Thickness is 4000 angstroms～8000 angstroms.
22. N-channel depletion type power MOSFET device as claimed in claim 18 it is characterised in that also including,
Dielectric layer, is covered on described epitaxial layer；
Fairlead window, is formed in described dielectric layer；
Front metal lead, is formed on described dielectric layer.
23. N-channel depletion type power MOSFET device as claimed in claim 22 are it is characterised in that the material of described dielectric layer
Matter is boron-phosphorosilicate glass.
24. N-channel depletion type power MOSFET device as claimed in claim 22 it is characterised in that also including,
Metal layer on back, described metal layer on back is formed at relative with described epitaxial layer one side in described Semiconductor substrate.
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| CN107887287B (en) * | 2016-09-30 | 2020-03-13 | 中芯国际集成电路制造(上海)有限公司 | Test method |
| CN108074966A (en) * | 2017-12-27 | 2018-05-25 | 电子科技大学 | Constant current device and its manufacturing method |
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| CN102074663A (en) * | 2010-12-31 | 2011-05-25 | 东莞市龙行航空科技有限公司 | Conveniently-extracted battery |
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