CN102901905A - Parallel bus testing device and method - Google Patents
Parallel bus testing device and method Download PDFInfo
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- CN102901905A CN102901905A CN2012104513661A CN201210451366A CN102901905A CN 102901905 A CN102901905 A CN 102901905A CN 2012104513661 A CN2012104513661 A CN 2012104513661A CN 201210451366 A CN201210451366 A CN 201210451366A CN 102901905 A CN102901905 A CN 102901905A
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Abstract
The invention discloses a parallel bus testing device which comprises a controller, a data acquisition card and a signal distributor, wherein the controller is connected with the data acquisition card; the data acquisition card is connected with the signal port of the signal distributor; the first test port and the second test port of the signal distributor are respectively connected with the input end and the output end of a bus back board; the controller comprises an application module, a recording module and a determining module, wherein the application module is used for applying high-level signals to a selected input pin in a signal port through the data acquisition card and setting all input pins except the selected input pin into a high-resistance state; the recording module is used for acquiring the level states of all output pins of the signal port, which are acquired by the data acquisition card; and the determining module is used for determining a first circuit state of a bus corresponding to the selected pin and a second circuit state between the corresponding bus and any other bus according to the level states of all the output pins. The invention also discloses a parallel bus testing method.
Description
Technical field
The present invention relates to the bus test technical field, relate in particular to a kind of parallel bus proving installation and method.
Background technology
Parallel bus is the passage that transmits data between parallel interface and the computer equipment, parallel bus generally comprises address bus, data bus and control bus three classes, generally, can be with a plurality of controllers or control module on the parallel bus, and these controllers or control module all are independently, and they interknit by parallel bus.Parallel bus form physically is generally a backboard, a plurality of controllers or control module can be linked together by this backboard, forms a parallel bus system.Owing to comprised parallel bus on this backboard, usually claimed this backboard to be " bus backplane ".
Parallel bus on the bus backplane is the connection bridge of each control assembly in the system, and is most important in system.If generating, occurring in the process of the described bus backplane of processing such as: rosin joint open circuit or dripping the fault such as weldering short circuit and check out not that in test in case flow into on-the-spot the use, gently then produce the data error code, system works is undesired; Heavy then produce short circuit, damage the accidents such as control system or system be on fire.So the bus backplane that newly processes must can come into operation by on off test.Yet, a general bus backplane has 40 to 80 lines, 8～16 electric connecting points on the connector are arranged on the every line, like this with regard to an electric connecting point that has more than 300, need to test the electric connecting point on the bus backplane, open fault occurred in order to definite any root bus, and short trouble occurred between which root bus, thereby further faulty line has been repaired.
On production line, the producer that has is the method for using manual test, namely manually utilize multimeter that per two electric connecting points are carried out break-make and measure, but this method workload is huge, efficient is extremely low and comprised people's subjective factor, test or mistake test often occur omitting.And the producer that has utilizes the LED lamp to come test bus, namely add a LED at the two ends of a bus, give voltage of bus, cable is logical if LED is bright, otherwise then obstructed, obviously, this equipment needs a large amount of LED and not directly perceived, the more important thing is, short circuit when between bus, occurs, just can't test in this way.
Summary of the invention
In view of this, fundamental purpose of the present invention is to provide a kind of parallel bus proving installation and method, with realize can be accurately, the purpose of whole circuits of quick, comprehensive test bus backboard.
For achieving the above object, the invention provides a kind of parallel bus proving installation, described device comprises: controller, data collecting card, signal distributor, described controller is connected with described data collecting card, described data collecting card is connected with the signal port of described signal distributor, the first test port of described signal distributor be connected test port and be connected with output terminal with the input end of bus backplane respectively, all be in series with current-limiting resistance between every connecting line of described signal port and described the first test port, all be in series with pull down resistor between every connecting line of described signal port and described the second test port and the ground wire, described controller comprises:
Apply module, be used for applying high level signal in a selected input pin of described signal port through described data collecting card, and other all input pins except described selected input pin all are set to high-impedance state;
Logging modle is used for obtaining the level state of all output pins of the described signal port that described data collecting card collects;
Determination module is used for determining the First Line line state of the corresponding bus of described selected pin and the second line status between described corresponding bus and other bus according to the level state of described all output pins.
Preferably, in said apparatus, described determination module comprises:
Detecting unit is for detection of the level state of described all output pins;
The first decision of normal states unit is used for determining that the line status of the corresponding bus of described selected input pin is for normal when the level state that described detecting unit detects output pin corresponding to the described selected input pin that obtains is high level;
The second decision of normal states unit, be used for when there is low level in the level state that described detecting unit detects other all output pins except output pin corresponding to described selected input pin that obtain, determine that level state is that the line status of bus corresponding to low level output pin is normally;
The open-circuit condition determining unit is used for determining that the line status of the corresponding bus of described selected input pin is open circuit when the level state that described detecting unit detects output pin corresponding to the described selected input pin that obtains is low level;
The short-circuit condition determining unit, be used for when there is high level in the level state that described detecting unit detects other all output pins except output pin corresponding to described selected input pin that obtain, determine that level state be bus corresponding to the output pin of high level with line status between the corresponding bus of described selected input pin is short circuit.
Preferably, in said apparatus, determine successively the First Line line state of the corresponding bus of each selected input pin and the second line status between described corresponding bus and other bus according to pin numbering.
Preferably, said apparatus also comprises: with the input end of described bus backplane as output terminal, and with the output terminal of described bus backplane as input end, determine the First Line line state of the corresponding bus of described selected input pin and the second line status between described corresponding bus and other bus according to the level state of all output pins in the described signal port.
Preferably, in said apparatus, the connecting interface between described data collecting card and described controller adopts pci interface or ISA interface or USB interface or Ethernet interface.
The present invention also provides a kind of parallel bus method of testing, described method is applied to the parallel bus proving installation, described proving installation comprises: controller, data collecting card, signal distributor, described controller is connected with described data collecting card, described data collecting card is connected with the signal port of described signal distributor, the first test port of described signal distributor be connected test port and be connected with output terminal with the input end of bus backplane respectively, all be in series with current-limiting resistance between every connecting line of described signal port and described the first test port, all be in series with pull down resistor between every connecting line of described signal port and described the second test port and the ground wire; Described controller is realized test to parallel bus according to following steps:
Apply the selected input pin of high level signal in described signal port through described data collecting card, and other all input pins except described selected input pin all are set to high-impedance state;
Obtain the level state of all output pins of the described signal port that described data collecting card collects;
Determine the First Line line state of the corresponding bus of described selected pin and the second line status between described corresponding bus and other bus according to the level state of described all output pins.
Preferably, in said method, described level state according to described all output pins determines that the First Line line state of the corresponding bus of described selected pin and the second line status between described corresponding bus and other bus comprise:
Detect the level state of described all output pins;
If the level state of the output pin that described selected input pin is corresponding is high level, determine that then the line status of the corresponding bus of described selected input pin is normal;
If have low level in the level state of other all output pins beyond output pin corresponding to described selected input pin, determine that then level state is that the line status of bus corresponding to low level output pin is for normal;
If the level state of the output pin that described selected input pin is corresponding is low level, determine that then the line status of the corresponding bus of described selected input pin is open circuit;
If have high level in the level state of other all output pins beyond output pin corresponding to described selected input pin, determine that then level state be bus corresponding to the output pin of high level with line status between the corresponding bus of described selected input pin is short circuit.
Preferably, in said method, determine successively the First Line line state of the corresponding bus of each selected input pin and the second line status between described corresponding bus and other bus according to pin numbering.
Preferably, said method also comprises: with the input end of described bus backplane as output terminal, and with the output terminal of described bus backplane as input end, determine the First Line line state of the corresponding bus of described selected input pin and the second line status between described corresponding bus and other bus according to the level state of all output pins in the described signal port.
Preferably, in said method, the connecting interface between described data collecting card and described controller adopts pci interface or ISA interface or USB interface or Ethernet interface.
As seen, parallel bus proving installation of the present invention and method, by described high level signal is put on a selected input pin of signal distributor signal port through data collecting card, and other all input pins except described selected input pin all are set to high-impedance state; Obtain the level state of all output pins of the described signal port that described data collecting card collects; Determine according to the level state of described all output pins whether the corresponding bus of selected pin open circuit occurred at last, and should select between the corresponding bus of pin and other bus short circuit whether occurred, thereby can obtain the line status of each bus on the bus backplane itself and the line status between bus, the present invention can accurately, fast, comprehensively test the situation of parallel bus open circuit, short circuit, and can realize the test of any one bus backplane.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art, apparently, accompanying drawing in the following describes is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the structural representation of parallel bus proving installation of the present invention;
Fig. 2 is signal distributor internal circuit diagram of the present invention;
Fig. 3 is the structural representation of determining unit in the parallel bus proving installation of the present invention;
Fig. 4 is line fault pattern diagram of the present invention;
Fig. 5 is pin status of the present invention and line status table;
Fig. 6 is the schematic flow sheet of parallel bus method of testing of the present invention.
Embodiment
For the purpose, technical scheme and the advantage that make the embodiment of the invention clearer, below in conjunction with the accompanying drawing in the embodiment of the invention, technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
The line status of bus comprises normally, short circuit, these three kinds of situations of opening a way, and short-circuit condition comprises two line short circuits or multi-thread short circuit; Open-circuit condition comprises single line open circuit or multi-thread open circuit.The present invention not only can judge bus backplane and short circuit occur and can locate concrete which root bus producing short circuit, can also judge bus backplane appearance open circuit and can locate concrete which root bus generation open circuit, this has very large directive significance to reprocessing after testing.
Adopt the present invention that parallel bus is tested, mainly be to utilize controller (can be computing machine or industrial control computer) control data collecting card to electric signal of a certain transmission of bus one end, then monitor the state of all buses and record all quantity of states at the other end, to obtain first group of Monitoring Data; In like manner, send an electric signal for again another root of bus one end, then monitor the state of all buses and record all quantity of states at the other end, to obtain second group of Monitoring Data; The like, all buses are all tested once, there are how many root buses just can how much be organized data, just can obtain at last the line status of whole bus backplane by these data of computer program analysis.
Referring to shown in Figure 1, Fig. 1 is the structural representation of parallel bus proving installation provided by the invention, described device comprises: controller 1, data collecting card 2, signal distributor 3, described controller 1 is connected with described data collecting card 2, described data collecting card 2 is connected with the signal port XP3 of described signal distributor 3, the first test port XP1 of described signal distributor 3 be connected test port XP2 and be connected with output terminal with the input end of bus backplane 4 respectively, all be in series with current-limiting resistance between every connecting line of described signal port XP3 and described the first test port XP1, all be in series with pull down resistor between every connecting line of described signal port XP3 and described the second test port XP2 and the ground wire, described controller 1 comprises:
Apply module 11, be used for applying high level signal in a selected input pin of described signal port through described data collecting card, and other all input pins except described selected input pin all are set to high-impedance state;
Logging modle 12 is used for obtaining the level state of all output pins of the described signal port XP3 that described data collecting card 2 collects.
Determination module 13 is used for determining the First Line line state of the corresponding bus of described selected pin and the second line status between described corresponding bus and other bus according to the level state of described all output pins.
Wherein, described First Line line state is normal or open circuit, and described the second line status is normal or short circuit.
For the ease of understanding, the below at first specifically introduces the inner structure of signal distributor 3.Signal distributor internal circuit diagram referring to shown in Figure 2 has identical connected mode based on every bus, for convenience of explanation, has only provided two bus connections in this circuit diagram.This signal distributor internal circuit comprises two electron-like components and parts:
1), connector plug (XP1～XP3)
XP1 is connected for the plug that connects bus backplane with XP2, plug can be inserted into during test on two corresponding on the bus backplane sockets, if take the bus of 40 cores as example (16 of address buss, 16 of data buss, 8 of control buss), need choose the plug that XP1 and XP2 are 40 cores, and the plug model will with bus backplane to be measured on socket supporting; XP3 is the plug for the connection data capture card, its model needs and the socket of data collecting card mates, wherein, the XP3 plug is divided into input pin part (such as XP3:1) and output pin partly (such as XP3:101), and the number of pins of every part is all identical with bus number in the bus backplane.
2), resistance
If still take the bus of 40 cores as example, need to connect current-limiting resistance R1～R40 in the circuit, its effect is to prevent bus short circuit and the data capture card is impacted; And need connection pull down resistor R101～R140, its effect is to prevent the bus open circuit and bus signals is played pendulum.
In the time of need to testing, first plug XP1 and XP2 are inserted into respectively on two sockets of bus backplane.Bus between XP1:1 (No. 1 pin of plug XP1), XP2:1 (No. 1 pin of plug XP2) and pin XP1:1 and XP2:1 has just linked together like this, and in like manner, other pin and bus have also linked together.During test, test first pin No. 1, be about to plug XP3:1 (No. 1 pin of plug XP3) and be set to high level, (XP3:2～XP3:40) is set to high-impedance state to other pin, and keep, (state of XP3:101～XP3:140), state is divided into: high level or low level to gather afterwards all output pins again.In like manner, the test process of No. 2 pins and other all pins is with No. 1 pin.
In addition, in parallel bus proving installation shown in Figure 1, data collecting card is the capture card with digital I/O mouth, and the interface of it and controller is numerous, and data collecting card is connected with controller by the form of pci interface or ISA interface or USB interface or Ethernet interface, when bus is tested, the transmit control signal I/O mouth of driving data capture card of controller, wherein, I/O mouth output state has: high level (1), low level (0), high resistant (∞); I/O mouth input state has: high level (1), low level (0).
Referring to the structural representation of determining unit in the parallel bus proving installation shown in Figure 3, described determination module 13 comprises:
Detecting unit 131 is for detection of the level state of described all output pins;
The first decision of normal states unit 132, when being high level for the level state that detects the output pin (such as XP3:101) of described selected input pin (such as the XP3:1) correspondence that obtains at described detecting unit 131, determine that the line status of the corresponding bus of described selected input pin (such as XP3:1) (No. 1 bus) is for normal;
The second decision of normal states unit 133, be used for when there is low level in the level state that described detecting unit 131 detects other all output pins except output pin (such as XP3:101) corresponding to described selected input pin (such as XP3:1) that obtain, determine that level state is that the line status of bus (No. 2 buses) corresponding to low level output pin (such as XP3:102) is for normally;
Open-circuit condition determining unit 134, when being low level for the level state that detects the output pin (such as XP3:101) of described selected input pin (such as the XP3:1) correspondence that obtains at described detecting unit 131, determine that the line status of the described corresponding bus of selected input pin (No. 1 bus) is for opening a way;
Short-circuit condition determining unit 135, be used for when there is high level in the level state that described detecting unit 131 detects other all output pins except output pin (such as XP3:101) corresponding to described selected input pin (such as XP3:1) that obtain, determine level state be high level output pin (such as XP3:102) correspondence bus (No. 2 buses) with as described in line status between bus (No. 1 bus) corresponding to selected input pin be short circuit.
In addition, can according to pin numbering choose successively input pin and with the described pin of choosing as described selected input pin, in order to determine successively the First Line line state of each selected input pin correspondence bus and the second line status between described corresponding bus and other bus.
In addition, said apparatus also comprises: the connectivity port of transposing bus backplane, be about to the input end of described bus backplane as output terminal, and with the output terminal of described bus backplane as input end, retest according to the method described above, determine the First Line line state of the corresponding bus of described selected input pin and the second line status between described corresponding bus and other bus according to the level state of all output pins in the described signal port at last.
Content for a more clear understanding of the present invention, the below illustrates, the line fault pattern diagram that parameter is shown in Figure 4, three kinds of fault modes have been provided among this figure, choose two buses on the bus backplane, the bus that definition port one and port one are 01 is No. 1 bus, same, the bus that definition port 2 and port one are 02 is No. 2 buses, apply high level signal at No. 1 signal port input pin XP3:1 corresponding to bus, and No. 2 signal port input pin XP3:2 corresponding to bus are placed high-impedance state, the below describes with regard to following three kinds of fault modes:
Referring to first kind fault mode, with port one and 2 as input end, with port one 01 and 102 during as output terminal, occur in the situation of open circuit (open circuit point 1) and No. 1 bus and No. 2 bus short circuits near input end 1 place No. 1 bus, the equal output low level signal of the output pin of output terminal 101 and output terminal 102 correspondences, only can judge the bus open circuit this moment No. 1, but but can not judge between No. 1 bus and No. 2 buses short circuit whether occurred.Take to test in the other direction, be about to port one 01 and 102 as input end, simultaneously with port one and 2 as output terminal, at this moment, output terminal 1 corresponding output pin output low level signal but output terminal 2 corresponding output pins are exported high level signal, not only can judge No. 1 bus open circuit this moment, can also judge No. 1 bus and No. 2 bus short circuits (namely having open circuit point 1).
Referring to the Equations of The Second Kind fault mode, with port one and 2 as input end, with port one 01 and 102 during as output terminal, occur in the situation of open circuit (open circuit point 2) and No. 1 bus and No. 2 bus short circuits near output terminal 101 places No. 1 bus, output terminal 101 corresponding output pin output low level signals but output terminal 102 corresponding output pins are exported high level signal can be judged No. 1 bus open circuit and No. 1 bus and No. 2 bus short circuits (namely having open circuit point 2) this moment.Take to test in the other direction, just can not judge between No. 1 bus and No. 2 buses whether short circuit occurred.
Referring to the 3rd class fault mode, with port one and 2 as input end, with port one 01 and 102 during as output terminal, open circuit (open circuit point 1) occurs, occur near output terminal 101 places in the situation of open circuit (open circuit point 2) and No. 1 bus and No. 2 bus short circuits near input end 1 place No. 1 bus, output terminal 101 and output terminal 102 equal output low level signals only can be judged the bus open circuit this moment No. 1; If but after taking above-mentioned opposite direction to test, as the port one and 2 of output terminal also equal output low level signals, be to judge all the time short-circuit condition between No. 1 bus and No. 2 buses in this case.
Certainly, be not limited only to above-mentioned three class fault modes but the present invention includes, the fault mode of other class of deriving is content of the present invention.
Based on above-mentioned fault mode, can adopt method of the present invention successively every on bus backplane bus to be carried out first round test, can judge by said method and to learn open circuit has appearred in which circuit in all circuits, but but may not all judge the short trouble (for example the 3rd class fault mode) between circuit, therefore, after first round test can to obtain to faulty line repair, and then carry out second according to method provided by the invention, the third round test, in order to line fault is got rid of one by one, can repair all trouble spots the most at last.
Referring to pin status shown in Figure 5 and line status table, for convenience of description, only provide the test result of No. 1 pin herein, analyze the situation of 3 buses, equally, No. 2, test, also can collect similar results when No. 3 pins and other any pin, can do same analysis, all will obtain test result with form or other mode for every bus, last, comprehensively all test results can judge whole bus backplane, finally drawing which bar circuit occurs short circuit occurring between which circuit of open circuit, reprocess in order to carry out fault according to this result, repeat again above-mentioned test after reprocessing, repair the most at last all trouble spots.
Parallel bus proving installation of the present invention by described high level signal is put on a selected input pin of signal distributor signal port through data collecting card, and all is set to high-impedance state with other all input pins except described selected input pin; Obtain the level state of all output pins of the described signal port that described data collecting card collects; Determine according to the level state of described all output pins whether the corresponding bus of selected pin open circuit occurred at last, and should select between the corresponding bus of pin and other bus short circuit whether occurred, thereby can obtain the line status of each bus on the bus backplane itself and the line status between bus, the present invention can accurately, fast, comprehensively test the situation of parallel bus open circuit, short circuit, and can realize the test of any one bus backplane.
Referring to shown in Figure 6, Fig. 6 is the schematic flow sheet of a kind of parallel bus method of testing provided by the invention, described method is applied to the parallel bus proving installation, described proving installation comprises: controller, data collecting card, signal distributor, described controller is connected with described data collecting card, described data collecting card is connected with the signal port of described signal distributor, the first test port of described signal distributor be connected test port and be connected with output terminal with the input end of bus backplane respectively, all be in series with current-limiting resistance between every connecting line of described signal port and described the first test port, all be in series with pull down resistor between every connecting line of described signal port and described the second test port and the ground wire; Described controller is realized test to parallel bus according to following steps:
Step 601: apply the selected input pin of high level signal in described signal port through described data collecting card, and other all input pins except described selected input pin all are set to high-impedance state;
Step 602: the level state that obtains all output pins of the described signal port that described data collecting card collects;
Step 603: determine the First Line line state of the corresponding bus of described selected pin and the second line status between described corresponding bus and other bus according to the level state of described all output pins.
Wherein, described First Line line state is normal or open circuit, and described the second line status is normal or short circuit.
Performing step 103 in accordance with the following methods: at first, detect the level state of described all output pins; If the level state of the output pin that described selected input pin is corresponding is high level, determine that then the line status of the corresponding bus of described selected input pin is normal; If have low level in the level state of other all output pins beyond output pin corresponding to described selected input pin, determine that then level state is that the line status of bus corresponding to low level output pin is for normal; If the level state of the output pin that described selected input pin is corresponding is low level, determine that then the line status of the corresponding bus of described selected input pin is open circuit; If have high level in the level state of other all output pins beyond output pin corresponding to described selected input pin, determine that then level state be bus corresponding to the output pin of high level with line status between the corresponding bus of described selected input pin is short circuit.
In addition, determine successively the First Line line state of the corresponding bus of each selected input pin and the second line status between described corresponding bus and other bus according to pin numbering.
In addition, said method also comprises: with the input end of described bus backplane as output terminal, and with the output terminal of described bus backplane as input end, determine the First Line line state of the corresponding bus of described selected input pin and the second line status between described corresponding bus and other bus according to the level state of all output pins in the described signal port.
Connecting interface between described data collecting card and described controller adopts pci interface or ISA interface or USB interface or Ethernet interface.
Parallel bus method of testing of the present invention by described high level signal is put on a selected input pin of signal distributor signal port through data collecting card, and all is set to high-impedance state with other all input pins except described selected input pin; Obtain the level state of all output pins of the described signal port that described data collecting card collects; Determine according to the level state of described all output pins whether the corresponding bus of selected pin open circuit occurred at last, and should select between the corresponding bus of pin and other bus short circuit whether occurred, thereby can obtain the line status of each bus on the bus backplane itself and the line status between bus, the present invention can accurately, fast, comprehensively test the situation of parallel bus open circuit, short circuit, and can realize the test of any one bus backplane.
Also need to prove, in this article, relational terms such as the first and second grades only is used for an entity or operation are made a distinction with another entity or operation, and not necessarily requires or hint and have the relation of any this reality or sequentially between these entities or the operation.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thereby not only comprise those key elements so that comprise process, method, article or the equipment of a series of key elements, but also comprise other key elements of clearly not listing, or also be included as the intrinsic key element of this process, method, article or equipment.Do not having in the situation of more restrictions, the key element that is limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment that comprises described key element and also have other identical element.
To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the present invention.Multiple modification to these embodiment will be apparent concerning those skilled in the art, and General Principle as defined herein can in the situation that does not break away from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention will can not be restricted to these embodiment shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (10)
1. parallel bus proving installation, it is characterized in that, described device comprises: controller, data collecting card, signal distributor, described controller is connected with described data collecting card, described data collecting card is connected with the signal port of described signal distributor, the first test port of described signal distributor be connected test port and be connected with output terminal with the input end of bus backplane respectively, all be in series with current-limiting resistance between every connecting line of described signal port and described the first test port, all be in series with pull down resistor between every connecting line of described signal port and described the second test port and the ground wire, described controller comprises:
Apply module, be used for applying high level signal in a selected input pin of described signal port through described data collecting card, and other all input pins except described selected input pin all are set to high-impedance state;
Logging modle is used for obtaining the level state of all output pins of the described signal port that described data collecting card collects;
Determination module is used for determining the First Line line state of the corresponding bus of described selected pin and the second line status between described corresponding bus and other bus according to the level state of described all output pins.
2. device according to claim 1 is characterized in that, described determination module comprises:
Detecting unit is for detection of the level state of described all output pins;
The first decision of normal states unit is used for determining that the line status of the corresponding bus of described selected input pin is for normal when the level state that described detecting unit detects output pin corresponding to the described selected input pin that obtains is high level;
The second decision of normal states unit, be used for when there is low level in the level state that described detecting unit detects other all output pins except output pin corresponding to described selected input pin that obtain, determine that level state is that the line status of bus corresponding to low level output pin is normally;
The open-circuit condition determining unit is used for determining that the line status of the corresponding bus of described selected input pin is open circuit when the level state that described detecting unit detects output pin corresponding to the described selected input pin that obtains is low level;
The short-circuit condition determining unit, be used for when there is high level in the level state that described detecting unit detects other all output pins except output pin corresponding to described selected input pin that obtain, determine that level state be bus corresponding to the output pin of high level with line status between the corresponding bus of described selected input pin is short circuit.
3. according to claim 1 to 2 each described devices, it is characterized in that, determine successively the First Line line state of the corresponding bus of each selected input pin and the second line status between described corresponding bus and other bus according to pin numbering.
4. device according to claim 3, it is characterized in that, described device also comprises: with the input end of described bus backplane as output terminal, and with the output terminal of described bus backplane as input end, determine the First Line line state of the corresponding bus of described selected input pin and the second line status between described corresponding bus and other bus according to the level state of all output pins in the described signal port.
5. according to claim 1 to 4 each described devices, it is characterized in that the connecting interface between described data collecting card and described controller adopts pci interface or ISA interface or USB interface or Ethernet interface.
6. parallel bus method of testing, it is characterized in that, described method is applied to the parallel bus proving installation, described proving installation comprises: controller, data collecting card, signal distributor, described controller is connected with described data collecting card, described data collecting card is connected with the signal port of described signal distributor, the first test port of described signal distributor be connected test port and be connected with output terminal with the input end of bus backplane respectively, all be in series with current-limiting resistance between every connecting line of described signal port and described the first test port, all be in series with pull down resistor between every connecting line of described signal port and described the second test port and the ground wire; Described controller is realized test to parallel bus according to following steps:
Apply the selected input pin of high level signal in described signal port through described data collecting card, and other all input pins except described selected input pin all are set to high-impedance state;
Obtain the level state of all output pins of the described signal port that described data collecting card collects;
Determine the First Line line state of the corresponding bus of described selected pin and the second line status between described corresponding bus and other bus according to the level state of described all output pins.
7. method according to claim 6 is characterized in that, described level state according to described all output pins determines that the First Line line state of the corresponding bus of described selected pin and the second line status between described corresponding bus and other bus comprise:
Detect the level state of described all output pins;
If the level state of the output pin that described selected input pin is corresponding is high level, determine that then the line status of the corresponding bus of described selected input pin is normal;
If have low level in the level state of other all output pins beyond output pin corresponding to described selected input pin, determine that then level state is that the line status of bus corresponding to low level output pin is for normal;
If the level state of the output pin that described selected input pin is corresponding is low level, determine that then the line status of the corresponding bus of described selected input pin is open circuit;
If have high level in the level state of other all output pins beyond output pin corresponding to described selected input pin, determine that then level state be bus corresponding to the output pin of high level with line status between the corresponding bus of described selected input pin is short circuit.
8. according to claim 6 to 7 each described methods, it is characterized in that, determine successively the First Line line state of the corresponding bus of each selected input pin and the second line status between described corresponding bus and other bus according to pin numbering.
9. method according to claim 8, it is characterized in that, described method also comprises: with the input end of described bus backplane as output terminal, and with the output terminal of described bus backplane as input end, determine the First Line line state of the corresponding bus of described selected input pin and the second line status between described corresponding bus and other bus according to the level state of all output pins in the described signal port.
10. according to claim 6 to 9 each described methods, it is characterized in that the connecting interface between described data collecting card and described controller adopts pci interface or ISA interface or USB interface or Ethernet interface.
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