CN102891080A - Forming method of dielectric layer - Google Patents
Forming method of dielectric layer Download PDFInfo
- Publication number
- CN102891080A CN102891080A CN201110201313XA CN201110201313A CN102891080A CN 102891080 A CN102891080 A CN 102891080A CN 201110201313X A CN201110201313X A CN 201110201313XA CN 201110201313 A CN201110201313 A CN 201110201313A CN 102891080 A CN102891080 A CN 102891080A
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- layer
- carbon
- dielectric
- ultralow
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A forming method of a dielectric layer comprises the following steps of: providing a semiconductor substrate; forming the dielectric layer on the semiconductor substrate, wherein the dielectric layer is formed by at least twice depositions, and a preset thickness is deposited every time; and carrying out carbon treatment on the dielectric layer after each deposition. According to the invention, k value drift and great capacitance change of the ultralow-k dielectric layer are effectively prevented, and stability and reliability of a semiconductor device are guaranteed.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly a kind of formation method of dielectric layer.
Background technology
At present in the last part technology that semiconductor is made, consist of integrated circuit in order to connect all parts, usually use have relative high conductivity metal material for example copper connect up metal line namely.And for the conductive plunger that is generally that connects between the metal line.The structure that couples together for active area and other integrated circuit with semiconductor device is generally conductive plunger.Existing conductive plunger forms by via process or dual-damascene technics.
In the process of the wiring of existing formation copper or conductive plunger, form groove or through hole, then filled conductive material in groove or through hole by the etching dielectric layer.Yet, when characteristic size reaches the following technique of deep-submicron, when making copper wiring or conductive plunger, for preventing the RC effect, the dielectric material that must use ultralow dielectric (Ultra low k) is as dielectric layer (described ultralow k as dielectric constant less than or equal to 2.6).In U.S. Patent application US11/556306, disclose and a kind ofly adopted ultralow k dielectric material as the technical scheme of dielectric layer.
In the back segment manufacturing process of semiconductor device, in making the copper metal line process, adopt the technique of ultralow k dielectric layer as shown in Figures 1 to 4, with reference to figure 1, Semiconductor substrate 10 is provided, be formed with such as structures such as transistor, capacitor, conductive plungers on the described Semiconductor substrate 10; Form ultralow k dielectric layer 20 in Semiconductor substrate 10; Form anti-reflecting layer (BARC) 30 at ultralow k dielectric layer 20, be used for photoetching process and prevent that light from carrying out next rete and affecting the character of rete; Apply photoresist layer 40 at anti-reflecting layer 30; Through exposure imaging technique, define the pattern of opening at photoresist layer 40.
As shown in Figure 2, take photoresist layer 40 as mask, along the ultralow k dielectric layer 20 of the pattern etch of opening to exposing Semiconductor substrate 10, form groove 50.
As shown in Figure 3, remove photoresist layer and anti-reflecting layer; Form copper metal layer 60 with sputtering process at ultralow k dielectric layer 20, and described copper metal layer 60 is filled in the full groove.
As shown in Figure 4, adopt chemical mechanical milling method (CMP) planarization metal layer to exposing ultralow k dielectric layer 20, form metal wiring layer 60a.
When prior art forms metal line or conductive plunger in ultralow k dielectric layer, the dielectric constant k value of ultralow k dielectric layer can drift about (k value become large), thereby cause ultralow k dielectric layer capacitance to change, make the stability of semiconductor device and reliability produce serious problems.
Summary of the invention
The problem that the present invention solves provides a kind of formation method of dielectric layer, prevents that the dielectric constant k value of ultralow k dielectric layer is drifted about, and causes stability and the integrity problem of semiconductor device when making metal wiring layer or conductive plunger.
For addressing the above problem, the embodiment of the invention provides a kind of formation method of dielectric layer, comprising: Semiconductor substrate is provided; Form dielectric layer in described Semiconductor substrate, described dielectric layer deposits formation at least at twice, deposits predetermined thickness at every turn; All carrying out carbon after each deposition processes.
Optionally, described carbon is treated to carbon-containing plasma and processes.
Optionally, described carbon-containing plasma is processed to adopt and is comprised C
XH
YGas, content is 400～800sccm.
Optionally, the gas that described carbon-containing plasma is processed also comprises helium, and content is 2000～3000sccm.
Optionally, it is 350 ℃～400 ℃ that described carbon-containing plasma is processed the temperature that adopts, and the time is 1～2 minute, and radio-frequency power is 800～1200W.
Optionally, described predetermined thickness is 800 dusts～1000 dusts.
Optionally, described dielectric layer is ultralow k dielectric layer, and dielectric constant is less than or equal to 2.6.
Optionally, the material of described ultralow k dielectric layer is SiCOH.
Optionally, the method for formation dielectric layer is chemical vapour deposition technique.
Compared with prior art, technical solution of the present invention has the following advantages: form dielectric layer in described Semiconductor substrate, described dielectric layer deposits formation at least at twice, deposits predetermined thickness at every turn; All carrying out carbon after each deposition processes.Follow-up photoresist layer peel off with etching dielectric layer process in carbon content is had consumption, owing to increased the carbon content in the dielectric layer, make the carbon content in the dielectric layer keep stable, avoided the impact on the dielectric constant of ultralow k dielectric layer of lacking of carbon content, effectively prevent the significantly variation of k value drift and the electric capacity of ultralow k dielectric layer, guaranteed stability and the reliability of semiconductor device.
Further, deposition several times deposits at every turn and carries out carbon behind 800 dusts～1000 dusts and process, and carbon ion is uniformly distributed in the porous material of dielectric layer; Preventing from only carrying out on the dielectric layer surface carbon processes, the follow-up photoresist layer that dielectric layer surface is caused with the carbon ion skewness of dielectric layer inside peel off with etching dielectric layer process in too much to the carbon content consumption of dielectric layer inside, avoided the impact on the dielectric constant of ultralow k dielectric layer of lacking of carbon content, effectively prevent the significantly variation of k value drift and the electric capacity of ultralow k dielectric layer, guaranteed stability and the reliability of semiconductor device.
Description of drawings
Fig. 1 to Fig. 4 is the schematic diagram that prior art forms the metal line that comprises ultralow k dielectric layer;
Fig. 5 is the embodiment schematic flow sheet that the present invention forms dielectric layer;
Fig. 6 to Figure 11 is the first embodiment schematic diagram that the present invention forms the semiconductor device that comprises ultralow k dielectric layer;
Figure 12 to Figure 19 is for forming the second embodiment schematic diagram of the semiconductor device that comprises ultralow k dielectric layer in the present invention;
Figure 20 is that the dielectric layer of prior art and technique of the present invention formation is through the variation comparison diagram of k value behind the etching technics.
Embodiment
Technique below deep-submicron, when making metal wiring layer or conduction are inserted in last part technology, adopt ultralow k dielectric material as in the dielectric layer process, the inventor finds because ultralow k dielectric layer is porous material (Fig. 1 is to shown in Figure 4), therefore form through hole or groove in etching, and remove in the photoresist layer process, can be etched gas or podzolic gas of carbon ion in the dielectric layer taken away, cause the dielectric constant k value of ultralow k dielectric layer skew to occur and then can cause ultralow k dielectric layer electric capacity to change, thereby the insulation effect variation that causes ultralow k dielectric layer, the stability of the semiconductor device of follow-up formation and integrity problem.
The inventor is for above-mentioned technical problem, through the analysis to reason, constantly research is found can cause dielectric layer dielectric constant k value to be offset in the carbon ion disappearance, the content that increases equably so carbon ion in dielectric layer can avoid subsequent etching technique and photoresist divesting technology on the impact of the dielectric constant of ultralow k dielectric layer, effectively prevent the significantly variation of k value drift and the electric capacity of ultralow k dielectric layer, guaranteed stability and the reliability of semiconductor device.
Fig. 5 is the embodiment schematic flow sheet that the present invention forms dielectric layer, and as shown in Figure 5, execution in step S11 provides Semiconductor substrate; Execution in step S12 forms dielectric layer in described Semiconductor substrate, and described dielectric layer deposits formation at least at twice, deposits predetermined thickness at every turn; Execution in step S13 all carries out carbon and processes after each deposition.
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
The first embodiment
Fig. 6 to Figure 11 is the first embodiment schematic diagram (to form metal wiring layer as example) that the present invention forms the semiconductor device that comprises ultralow k dielectric layer.As shown in Figure 6, provide Semiconductor substrate 100, usually be formed with such as structures such as transistor, capacitor, metal wiring layers through FEOL on the described Semiconductor substrate 100.
Because in the making metal line technique of present embodiment, the thickness of dielectric layers that needs to form is 2400 dusts～3000 dusts.Therefore, adopt the method for present embodiment, form ground floor dielectric material 200a with chemical vapour deposition technique first on Semiconductor substrate 100, the thickness of described ground floor dielectric material 200a is 800 dusts～1000 dusts.Then, ground floor dielectric material 200a is carried out carbon processing first time 300a, carbon ion is infiltrated through among the ground floor dielectric material 200a.
Carry out carbon and process behind the dielectric material of deposition 800 dusts～1000 dusts, carbon ion can infiltrate among the whole layer ground floor dielectric material 200a fully under this thickness.
In the present embodiment, described carbon processing first time 300a is that carbon-containing plasma is processed.Described carbon-containing plasma is processed and is comprised the body C of institute
XH
YAnd helium, wherein C
XH
YContent is 400～800sccm, and helium content is 2000～3000sccm.It is 350 ℃～400 ℃ that described carbon-containing plasma is processed the temperature that adopts, and the time is 1～2 minute, and radio-frequency power is 800～1200W.
As shown in Figure 7, be the second layer layer of dielectric material 200b of 800 dusts～1000 dusts in the upper formation of the ground floor dielectric material 200a that processes through carbon thickness, the method that forms described second layer layer of dielectric material 200b is chemical vapour deposition technique; Then, second layer dielectric material 200b is carried out carbon processing second time 300b, carbon ion is infiltrated through among the second layer dielectric material 200b.
In the present embodiment, described carbon processing second time 300b is that carbon-containing plasma is processed.Described carbon-containing plasma is processed and is comprised the body C of institute
XH
YAnd helium, wherein C
XH
YContent is 400～800sccm, and helium content is 2000～3000sccm.It is 350 ℃～400 ℃ that described carbon-containing plasma is processed the temperature that adopts, and the time is 1～2 minute, and radio-frequency power is 800～1200W.
As shown in Figure 8, be the 3rd layer of layer of dielectric material 200c of 800 dusts～1000 dusts in the upper formation of the second layer dielectric material 200b that processes through carbon thickness, the method that forms described the 3rd layer of layer of dielectric material 200c is chemical vapour deposition technique; Then, the 3rd layer of dielectric material 200c carried out for the third time carbon processing 300c, carbon ion is infiltrated through among the 3rd layer of dielectric material 200c.
In the present embodiment, it is that carbon-containing plasma is processed that described for the third time carbon is processed 300c.Described carbon-containing plasma is processed and is comprised the body C of institute
XH
YAnd helium, wherein C
XH
YContent is 400～800sccm, and helium content is 2000～3000sccm.It is 350 ℃～400 ℃ that described carbon-containing plasma is processed the temperature that adopts, and the time is 1～2 minute, and radio-frequency power is 800～1200W.
In the present embodiment, through deposition, ground floor dielectric material 200a, second layer dielectric material 200b and the 3rd layer of layer of dielectric material 200c consist of dielectric layer 200; Process through carbon, the carbon ion content of whole dielectric layer 200 evenly increases.Described dielectric layer 200 is ultralow k dielectric layer, and dielectric constant is less than or equal to 2.6, and ultralow k dielectric layer is porous material; The material of described ultralow k dielectric layer is SiCOH, and the interval is comparatively sparse between the atom of described SiCOH.
As shown in Figure 9, at described dielectric layer 200 surperficial spin coating photoresist layers 400; Then, photoresist layer 400 is exposed and development treatment, form opening figure.
As shown in figure 10, take photoresist layer 400 as mask, along opening figure with dry etching method etching dielectric layer 200 to exposing Semiconductor substrate 100, form groove 500, described groove 500 forms metal wiring layer in order to follow-up filling.
As shown in figure 11, remove photoresist layer with ashing method; On described dielectric layer 200, form metal level with sputtering method, and described metal level is filled full groove; Then use chemical mechanical polishing method (CMP) planarization metal layer to exposing dielectric layer 200, form metal wiring layer 600.
In the present embodiment, the material of described metal wiring layer 600 when being copper, before forming metal wiring layer 600, channel bottom also the Applied Physics vapour deposition process form the layer of copper inculating crystal layer, make metal wiring layer 600 around its growth.
In the present embodiment, minutes three times deposition forms dielectric layers 200, deposits to carry out carbon behind 800 dusts～1000 dust dielectric materials and process at every turn, and carbon ion is uniformly distributed in the porous material of dielectric layer 200; Preventing from only carrying out on dielectric layer 200 surfaces carbon processes, the follow-up photoresist layers that dielectric layer 200 surface is caused with the carbon ion skewness of dielectric layer 200 inside peel off with etching dielectric layer process in too much to the carbon content consumption of dielectric layer inside, avoided the impact on the dielectric constant of ultralow k dielectric layer of lacking of carbon content, effectively prevent the significantly variation of k value drift and the electric capacity of ultralow k dielectric layer, guaranteed stability and the reliability of semiconductor device.
The second embodiment
Figure 12 to Figure 19 is for forming semiconductor device the second embodiment schematic diagram comprise ultralow k dielectric layer (take the conductive plunger that forms dual-damascene structure as example) in the present invention.As shown in figure 12, provide Semiconductor substrate 1000, usually be formed with such as structures such as transistor, capacitor, metal wiring layers through FEOL on the described Semiconductor substrate 1000;
Because in the conductive plunger technique of the making dual-damascene structure of present embodiment, the thickness of dielectric layers that needs to form is 3200 dusts～4000 dusts.Therefore, adopt the method for present embodiment, form ground floor dielectric material 2000a with chemical vapour deposition technique first on Semiconductor substrate 1000, the thickness of described ground floor dielectric material 2000a is 800 dusts～1000 dusts.Then, ground floor dielectric material 2000a is carried out carbon processing first time 3000a, carbon ion is infiltrated through among the ground floor dielectric material 2000a.
Carry out carbon and process behind the dielectric material of deposition 800 dusts～1000 dusts, carbon ion can infiltrate among the whole layer ground floor dielectric material 2000a fully under this thickness.
In the present embodiment, described carbon processing first time 3000a is that carbon-containing plasma is processed.Described carbon-containing plasma is processed and is comprised the body C of institute
XH
YAnd helium, wherein C
XH
YContent is 400～800sccm, and helium content is 2000～3000sccm.It is 350 ℃～400 ℃ that described carbon-containing plasma is processed the temperature that adopts, and the time is 1～2 minute, and radio-frequency power is 800～1200W.
As shown in figure 13, be the second layer layer of dielectric material 2000b of 800 dusts～1000 dusts in the upper formation of the ground floor dielectric material 2000a that processes through carbon thickness, the method that forms described second layer layer of dielectric material 2000b is chemical vapour deposition technique; Then, second layer dielectric material 2000b is carried out carbon processing second time 3000b, carbon ion is infiltrated through among the second layer dielectric material 2000b.
In the present embodiment, described carbon processing second time 3000b is that carbon-containing plasma is processed.Described carbon-containing plasma is processed and is comprised the body C of institute
XH
YAnd helium, wherein C
XH
YContent is 400～800sccm, and helium content is 2000～3000sccm.It is 350 ℃～400 ℃ that described carbon-containing plasma is processed the temperature that adopts, and the time is 1～2 minute, and radio-frequency power is 800～1200W.
As shown in figure 14, be the 3rd layer of layer of dielectric material 2000c of 800 dusts～1000 dusts in the upper formation of the second layer dielectric material 2000b that processes through carbon thickness, the method that forms described the 3rd layer of layer of dielectric material 2000c is chemical vapour deposition technique; Then, the 3rd layer of dielectric material 2000c carried out for the third time carbon processing 3000c, carbon ion is infiltrated through among the 3rd layer of dielectric material 2000c.
In the present embodiment, it is that carbon-containing plasma is processed that described for the third time carbon is processed 3000c.Described carbon-containing plasma is processed and is comprised the body C of institute
XH
YAnd helium, wherein C
XH
YContent is 400～800sccm, and helium content is 2000～3000sccm.It is 350 ℃～400 ℃ that described carbon-containing plasma is processed the temperature that adopts, and the time is 1～2 minute, and radio-frequency power is 800～1200W.
As shown in figure 15, be the 4th layer of layer of dielectric material 2000d of 800 dusts～1000 dusts in the upper formation of the 3rd layer of dielectric material 2000c that processes through carbon thickness, the method that forms described the 4th layer of layer of dielectric material 2000d is chemical vapour deposition technique; Then, the 4th layer of dielectric material 2000d carried out the 4th carbon process 3000d, carbon ion is infiltrated through among the 4th layer of dielectric material 2000d.
In the present embodiment, it is that carbon-containing plasma is processed that described the 4th carbon is processed 3000d.Described carbon-containing plasma is processed and is comprised the body C of institute
XH
YAnd helium, wherein C
XH
YContent is 400～800sccm, and helium content is 2000～3000sccm.It is 350 ℃～400 ℃ that described carbon-containing plasma is processed the temperature that adopts, and the time is 1～2 minute, and radio-frequency power is 800～1200W.
In the present embodiment, through deposition, ground floor dielectric material 2000a, second layer dielectric material 2000b, the 3rd layer of layer of dielectric material 2000c and the 4th layer of dielectric material 2000d consist of dielectric layer 2000; Process through carbon, the carbon ion content of whole dielectric layer 2000 evenly increases.Described dielectric layer 2000 is ultralow k dielectric layer, and dielectric constant is less than or equal to 2.6, and ultralow k dielectric layer is porous material; The material of described ultralow k dielectric layer is SiCOH, and the interval is comparatively sparse between the atom of described SiCOH.
As shown in figure 16, at described dielectric layer 2000 surperficial spin coating the first photoresist layers 4000; Then, the first photoresist layer 4000 is exposed and development treatment, form via hole image.
As shown in figure 17, take the first photoresist layer 4000 as mask, along via hole image with dry etching method etching dielectric layer 2000 to exposing Semiconductor substrate 1000, form through hole 5000.
As shown in figure 18, remove the first photoresist layer 4000; Form the second photoresist layer 6000 at described dielectric layer 2000 and Semiconductor substrate 1000, the second photoresist layer 6000 is carried out graphically defining groove figure; Then, take the second photoresist layer 6000 as mask, with dry etching method etching dielectric layer 2000, form groove 7000 along groove figure, described groove 7000 is communicated with through hole 5000, consists of dual-damascene structure.
As shown in figure 19, remove the second photoresist layer; Form metal level with chemical vapour deposition technique at described dielectric layer 2000, and described metal level is filled full dual-damascene structure; Then with the chemico-mechanical polishing metal level to exposing dielectric layer 2000, form conductive plunger 8000.
In the present embodiment, the material of described metal level is aluminium or copper or tungsten.Before filling metal level, form diffusion impervious layer in sidewall and the bottom of through hole and groove, prevent that the metal in the dual-damascene structure from diffusing in the dielectric layer 2000.
In the present embodiment, minutes four times deposition forms dielectric layers 2000, deposits to carry out carbon behind 800 dusts～1000 dust dielectric materials and process at every turn, and carbon ion is uniformly distributed in the porous material of dielectric layer 2000; Preventing from only carrying out on dielectric layer 2000 surfaces carbon processes, the follow-up photoresist layers that dielectric layer 2000 surface is caused with the carbon ion skewness of dielectric layer 2000 inside peel off with etching dielectric layer process in too much to the carbon content consumption of dielectric layer inside, avoided the impact on the dielectric constant of ultralow k dielectric layer of lacking of carbon content, effectively prevent the significantly variation of k value drift and the electric capacity of ultralow k dielectric layer, guaranteed stability and the reliability of semiconductor device.
Except above-mentioned two embodiment, according to technique and requirement on devices, during the dielectric layer of deposition different-thickness, be benchmark according to each deposition 800 dusts～1000 dusts, select different frequency of depositing to form dielectric layer.
Figure 20 is that the dielectric layer of prior art and technique of the present invention formation is through the variation comparison diagram of k value behind the etching technics.As shown in figure 20, existing technique forms in through hole or groove and the removal photoresist layer process at the ultralow k dielectric layer of etching, can be etched gas or podzolic gas of carbon ion in the ultralow k dielectric layer taken away, and causes the dielectric constant k value of ultralow k dielectric layer can be offset 10%～15%.And the present invention divides at least twice deposition to form dielectric layer, all carries out carbon after each deposition and processes, and carbon ion is uniformly distributed in the porous material of dielectric layer; Follow-up photoresist layer peel off with etching dielectric layer process in although the carbon content in the dielectric layer is had consumption, but can not cause the very few of carbon content and the dielectric constant of ultralow k dielectric layer is exerted an influence, the dielectric layer that adopts as can be seen from Figure 20 method of the present invention to form, after over etching and photoresist lift off, dielectric constant k value can be by skew less than 5%, effectively prevent the significantly variation of k value drift and the electric capacity of ultralow k dielectric layer, guaranteed stability and the reliability of semiconductor device.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (9)
1. the formation method of a dielectric layer is characterized in that, comprises step:
Semiconductor substrate is provided;
Form dielectric layer in described Semiconductor substrate, described dielectric layer deposits formation at least at twice, deposits predetermined thickness at every turn;
All carrying out carbon after each deposition processes.
2. formation method according to claim 1 is characterized in that: described carbon is treated to carbon-containing plasma and processes.
3. formation method according to claim 2 is characterized in that: described carbon-containing plasma is processed to adopt and is comprised C
XH
YGas, content is 400～800sccm.
4. formation method according to claim 3 is characterized in that: the gas that described carbon-containing plasma is processed also comprises helium, and content is 2000～3000sccm.
5. formation method according to claim 4 is characterized in that: it is 350 ℃～400 ℃ that described carbon-containing plasma is processed the temperature that adopts, and the time is 1～2 minute, and radio-frequency power is 800～1200W.
6. formation method according to claim 1, it is characterized in that: described predetermined thickness is 800 dusts～1000 dusts.
7. formation method according to claim 1, it is characterized in that: described dielectric layer is ultralow k dielectric layer, and dielectric constant is 2.2～2.6.
8. formation method according to claim 7, it is characterized in that: the material of described ultralow k dielectric layer is SiCOH.
9. formation method according to claim 1 is characterized in that: the method that forms dielectric layer is chemical vapour deposition technique.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110201313.XA CN102891080B (en) | 2011-07-18 | 2011-07-18 | The formation method of dielectric layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110201313.XA CN102891080B (en) | 2011-07-18 | 2011-07-18 | The formation method of dielectric layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102891080A true CN102891080A (en) | 2013-01-23 |
| CN102891080B CN102891080B (en) | 2015-10-14 |
Family
ID=47534545
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110201313.XA Active CN102891080B (en) | 2011-07-18 | 2011-07-18 | The formation method of dielectric layer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102891080B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6528423B1 (en) * | 2001-10-26 | 2003-03-04 | Lsi Logic Corporation | Process for forming composite of barrier layers of dielectric material to inhibit migration of copper from copper metal interconnect of integrated circuit structure into adjacent layer of low k dielectric material |
| CN1755902A (en) * | 2004-09-30 | 2006-04-05 | 台湾积体电路制造股份有限公司 | Method for treating low-K dielectrics |
| US20080254631A1 (en) * | 2006-03-15 | 2008-10-16 | Tsutomu Shimayama | Method for fabrication of semiconductor device |
| CN101548375A (en) * | 2006-12-28 | 2009-09-30 | 东京毅力科创株式会社 | Semiconductor device and method for manufacturing the same |
| US20100304566A1 (en) * | 2009-05-29 | 2010-12-02 | Daniel Fischer | Establishing a hydrophobic surface of sensitive low-k dielectrics of microstructure devices by in situ plasma treatment |
-
2011
- 2011-07-18 CN CN201110201313.XA patent/CN102891080B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6528423B1 (en) * | 2001-10-26 | 2003-03-04 | Lsi Logic Corporation | Process for forming composite of barrier layers of dielectric material to inhibit migration of copper from copper metal interconnect of integrated circuit structure into adjacent layer of low k dielectric material |
| CN1755902A (en) * | 2004-09-30 | 2006-04-05 | 台湾积体电路制造股份有限公司 | Method for treating low-K dielectrics |
| US20080254631A1 (en) * | 2006-03-15 | 2008-10-16 | Tsutomu Shimayama | Method for fabrication of semiconductor device |
| CN101548375A (en) * | 2006-12-28 | 2009-09-30 | 东京毅力科创株式会社 | Semiconductor device and method for manufacturing the same |
| US20100304566A1 (en) * | 2009-05-29 | 2010-12-02 | Daniel Fischer | Establishing a hydrophobic surface of sensitive low-k dielectrics of microstructure devices by in situ plasma treatment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102891080B (en) | 2015-10-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20190252204A1 (en) | Spacer-damage-free etching | |
| US10276504B2 (en) | Preclean and deposition methodology for superconductor interconnects | |
| KR102284308B1 (en) | Precleaning Methods for Fabricating Superconductor Interconnects | |
| US8895323B2 (en) | Method of forming a magnetoresistive random-access memory device | |
| US10950444B2 (en) | Metal hard mask layers for processing of microelectronic workpieces | |
| US10002773B2 (en) | Method for selectively etching silicon oxide with respect to an organic mask | |
| CN102891080B (en) | The formation method of dielectric layer | |
| TWI559403B (en) | Mitigation of silicide formation on wafer bevel | |
| EP1425789A2 (en) | Method for controlling etch bias of carbon doped oxide films | |
| CN102800622B (en) | Method for forming dielectric layer | |
| CN102903620B (en) | The formation method of dielectric layer | |
| TWI747931B (en) | Method for forming film | |
| US20040261714A1 (en) | Plasma processing apparatus | |
| KR20150095593A (en) | Contact formation in ge-containing semiconductor devices | |
| CN105633011B (en) | The production method of interconnection structure | |
| JPH11354633A (en) | Manufacture of semiconductor device | |
| KR100520140B1 (en) | Method for forming capacitor of semiconductor device | |
| CN102479748B (en) | Forming method of semiconductor device | |
| KR100617044B1 (en) | method for forming metal line of semiconductor device | |
| KR20070069450A (en) | Method for fabricating metal-insulator-metal capacitor in semiconductor device | |
| CN104051322A (en) | Method for manufacturing semiconductor device | |
| KR20040031131A (en) | Method for forming inter-metal dielectric layer in semiconductor | |
| JPS63253645A (en) | Semiconductor device and manufacture thereof | |
| CN104658965A (en) | Semiconductor device and manufacturing method thereof | |
| KR20110078184A (en) | Pattern formation method of photoregist |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |