CN102867742B - Plasma etching method for eliminating morphologic deformation - Google Patents
Plasma etching method for eliminating morphologic deformation Download PDFInfo
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- CN102867742B CN102867742B CN201210343466.2A CN201210343466A CN102867742B CN 102867742 B CN102867742 B CN 102867742B CN 201210343466 A CN201210343466 A CN 201210343466A CN 102867742 B CN102867742 B CN 102867742B
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Abstract
The invention relates to a polysilicon etching method, and particularly relates to a plasma etching method for eliminating morphologic deformation. According to the plasma etching method for eliminating morphologic deformation, a high-selection-ratio polysilicon gate etching process based on oxide is adopted prior to polysilicon gate etching, so that residual anti-reflection coating is completely removed, thereby enabling the morphology of the etched polysilicon to be smooth and complete and ensuring that the process and the equipment performance are improved.
Description
Technical field
The present invention relates to a kind of method of etch polysilicon, particularly relate to a kind of plasma etching method eliminating pattern distortion.
Background technology
In semiconductor fabrication process, the manufacture of polysilicon gate is very crucial, also very large on the impact of device.Wherein particularly important to the control of etching polysilicon pattern, generally require etching surface vertical smooth, not distortion.
Because the size of polysilicon gate constantly reduces, original single-layer lithography glue is limited to the characteristic such as thickness, reflectivity control, etch resistance of photoresist self as etching barrier layer, can not meet integrated requirement.The polysilicon gate construction of the barrier newly developed at present, as shown in Figure 1a, this structure composition is mainly from the bottom up deposition substrate silicon chip 5, oxide 4, polysilicon gate 3, agraphitic carbon 2, antireflecting coating 1, photoresist (not shown) successively.When etching the polysilicon gate construction of this barrier, existing lithographic method first etches antireflecting coating 1, then etch amorphous carbon 2, then etches polycrystalline silicon gate 3.
But due to before etching polysilicon gate step, antireflecting coating 1 still has a certain amount of residual, as shown in Figure 1a, polysilicon gate construction etching incipient stage be as etching barrier layer using antireflecting coating 1, after etching a period of time, agraphitic carbon 2 is just as etching barrier layer, thus forms the situation having two kinds of etching barrier layers to coexist in polysilicon gate construction etching process.But the Main Ingredients and Appearance of antireflecting coating 1 is SiO
2agraphitic carbon 2 Main Ingredients and Appearance is carbon; this obviously has an impact for the formation of the polymer protective layer in etching process, in general, when antireflecting coating 1 is less as polymer during etching barrier layer; when agraphitic carbon 2 is more as polymer during etching barrier layer; thus make polysilicon form obvious boundary, pattern is out of shape, as shown in Figure 1 b; polysilicon gate 3 pattern is unsmooth, finally affects technique and device performance control.
Summary of the invention
For above-mentioned Problems existing, object of the present invention provides a kind of plasma etching method eliminating pattern distortion, by increasing the etching technics of oxidation step thing to polysilicon gate high selectivity before etching polysilicon gate, remove residual antireflecting coating completely, make the polysilicon profile after etching smooth complete, guarantee that technique and device performance promote.
The object of the invention is to be achieved through the following technical solutions:
Eliminate a plasma etching method for pattern distortion, wherein, comprise the following steps:
Step 1: polysilicon gate construction is deposition oxide, polysilicon gate, agraphitic carbon, antireflecting coating, photoresist successively from the bottom up on a silicon substrate;
Step 2: described polysilicon gate construction is put into reaction chamber;
Step 3: with described photoresist for mask, etches the upper surface of the described antireflecting coating outside the covering of described photoresist to described agraphitic carbon;
Step 4: to continue with remaining described antireflecting coating as mask, etches the upper surface of described agraphitic carbon to described polysilicon gate;
Step 5: utilize wafer to remove the described antireflecting coating of described agraphitic carbon surface residual completely;
Step 6: utilize described wafer to continue to etch the upper surface of oxide described in the described polysilicon gate best outside the covering of described agraphitic carbon, remove remaining described agraphitic carbon.
The plasma etching method of above-mentioned elimination pattern distortion, wherein, each step of described plasma etching method all adopts dry plasma etch technique.
The plasma etching method of above-mentioned elimination pattern distortion, wherein, oxide described in step 1 is to the Selection radio > 7 of described polysilicon gate.
The plasma etching method of above-mentioned elimination pattern distortion, wherein, antireflecting coating described in step 1 adopts SiO2 class inorganic anti-reflective coating.
The plasma etching method of above-mentioned elimination pattern distortion, wherein, the etching process of step 3 uses CF4 for main etching gas.
The plasma etching method of above-mentioned elimination pattern distortion, wherein, the etching process of step 4 uses O2 for main etching gas.
The plasma etching method of above-mentioned elimination pattern distortion, wherein, the etching process of step 5 controls the loss < 20A of described polysilicon gate.
The plasma etching method of above-mentioned elimination pattern distortion, wherein, the etching process of step 5 uses based on the etching gas of C4F8 or C5F8, C4F8 or C5F8 flow is 5-10sccm simultaneously.
The plasma etching method of above-mentioned elimination pattern distortion, wherein, the etching process of step 5 uses supply voltage and bias power are all more than or equal to 200W and are less than or equal to 300W.
The invention has the beneficial effects as follows by increasing the etching technics of oxidation step thing to polysilicon gate high selectivity before etching polysilicon gate, make the polysilicon profile after etching smooth complete, guarantee that technique and device performance promote, reduce production loss, improve productivity effect.
Accompanying drawing explanation
Fig. 1 a-1b is the etching schematic flow sheet of existing polysilicon gate construction;
Fig. 2 a-2d is a kind of schematic flow sheet eliminating the plasma etching method of pattern distortion of the present invention.
Embodiment
Below in conjunction with schematic diagram and concrete operations preferred version, the invention will be further described.
Shown in composition graphs 2a-2d, a kind of plasma etching method eliminating pattern distortion, wherein, comprises the following steps:
As shown in Figure 2 a, step 1: polysilicon gate construction is deposition oxide 22, polysilicon gate 23, agraphitic carbon 24, antireflecting coating 25, photoresist 26 successively from the bottom up on a silicon substrate 21;
In a preferred version of the present invention, each step of plasma etching method of the present invention all adopts dry plasma etch technique, the Selection radio > 7 of oxide 22 pairs of polysilicon gates 23;
Further, antireflecting coating 25 adopts SiO
2class inorganic anti-reflective coating.
Step 2: polysilicon gate construction is put into reaction chamber;
On technique scheme basis, further, following steps can be integrated into same reaction chamber and complete, and also can select to complete respectively at different reaction chambers.
As shown in Figure 2 b, step 3: with photoresist 26 for mask, the upper surface of antireflecting coating 25 to the agraphitic carbon 24 outside etching photoresist 26 covers;
Further, in this step, etching process uses CF
4it is main etching gas.
As shown in Figure 2 c, step 4: continue with remaining antireflecting coating 25 for mask, the upper surface of etch amorphous carbon 24 to polysilicon gate 23;
Further, in this step, etching process uses O
2it is main etching gas.
Step 5: utilize plasma process to remove the antireflecting coating 25 of agraphitic carbon 24 surface residual completely;
Further, in this step, etching process controls the loss < 20A of polysilicon gate 23;
In a preferred version of the present invention, in this step etching process can choice for use based on the etching gas of C4F8 or C5F8, C4F8 or C5F8 flow is 5-10sccm simultaneously, meanwhile, uses supply voltage and bias power are all more than or equal to 200W and are less than or equal to 300W.
As shown in Figure 2 d, step 6: utilize wafer to continue the upper surface of polysilicon gate 23 to the oxide 22 outside etch amorphous carbon 24 covering, remove remaining agraphitic carbon 24.
Polysilicon profile after etching is smooth complete, guarantees that technique and device performance promote.
Be described in detail concrete preferred version of the present invention above, but the present invention is not restricted to concrete preferred version described above, it is just as example.To those skilled in the art, any equivalent modifications and substitute also all among category of the present invention.Therefore, equalization conversion done without departing from the spirit and scope of the invention and amendment, all should contain within the scope of the invention.
Claims (6)
1. eliminate a plasma etching method for pattern distortion, it is characterized in that, comprise the following steps:
Step 1: polysilicon gate construction is deposition oxide, polysilicon gate, agraphitic carbon, antireflecting coating, photoresist successively from the bottom up on a silicon substrate;
Step 2: described polysilicon gate construction is put into reaction chamber;
Step 3: with described photoresist for mask, etches the upper surface of the described antireflecting coating outside the covering of described photoresist to described agraphitic carbon;
Step 4: to continue with remaining described antireflecting coating as mask, etches the upper surface of described agraphitic carbon to described polysilicon gate;
Step 5: adopt flow to be the C of 5-10sccm
4f
8or C
5f
8etching gas, etching removes the described antireflecting coating of described agraphitic carbon surface residual, uses supply voltage and bias power are all more than or equal to 200W and are less than or equal to 300W in described etching process;
Step 6: the upper surface continuing oxide described in the described polysilicon gate best outside the described agraphitic carbon covering of etching, removes remaining described agraphitic carbon;
Wherein, antireflecting coating described in step 1 adopts SiO
2class inorganic anti-reflective coating.
2. the plasma etching method of elimination pattern distortion according to claim 1, it is characterized in that, each step of described plasma etching method all adopts dry plasma etch technique.
3. the plasma etching method of elimination pattern distortion according to claim 1, it is characterized in that, oxide described in step 1 is to the Selection radio > 7 of described polysilicon gate.
4. the plasma etching method of elimination pattern distortion according to claim 1, is characterized in that, the etching process of step 3 uses CF
4it is main etching gas.
5. the plasma etching method of elimination pattern distortion according to claim 1, is characterized in that, the etching process of step 4 uses O
2it is main etching gas.
6. the plasma etching method of elimination pattern distortion according to claim 1, it is characterized in that, the etching process of step 5 controls the loss < 20A of described polysilicon gate.
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| CN102881597A (en) * | 2012-10-12 | 2013-01-16 | 上海华力微电子有限公司 | Method for manufacturing transistor |
| CN108133887B (en) * | 2017-12-04 | 2019-07-02 | 扬州国宇电子有限公司 | Flattening method based on deep etching |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6797552B1 (en) * | 2002-11-19 | 2004-09-28 | Advanced Micro Devices, Inc. | Method for defect reduction and enhanced control over critical dimensions and profiles in semiconductor devices |
| US6989332B1 (en) * | 2002-08-13 | 2006-01-24 | Advanced Micro Devices, Inc. | Ion implantation to modulate amorphous carbon stress |
| CN1809916A (en) * | 2003-07-28 | 2006-07-26 | 飞思卡尔半导体公司 | A semiconductor device having an organic anti-reflective coating (ARC) and method therefor |
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| JP2011049360A (en) * | 2009-08-27 | 2011-03-10 | Tokyo Electron Ltd | Plasma etching method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6989332B1 (en) * | 2002-08-13 | 2006-01-24 | Advanced Micro Devices, Inc. | Ion implantation to modulate amorphous carbon stress |
| US6797552B1 (en) * | 2002-11-19 | 2004-09-28 | Advanced Micro Devices, Inc. | Method for defect reduction and enhanced control over critical dimensions and profiles in semiconductor devices |
| CN1809916A (en) * | 2003-07-28 | 2006-07-26 | 飞思卡尔半导体公司 | A semiconductor device having an organic anti-reflective coating (ARC) and method therefor |
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