CN102855172A - Method for recording network card receiving time at high precision - Google Patents
Method for recording network card receiving time at high precision Download PDFInfo
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- CN102855172A CN102855172A CN2012102580638A CN201210258063A CN102855172A CN 102855172 A CN102855172 A CN 102855172A CN 2012102580638 A CN2012102580638 A CN 2012102580638A CN 201210258063 A CN201210258063 A CN 201210258063A CN 102855172 A CN102855172 A CN 102855172A
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Abstract
The invention provides a method for recording network card receiving time at high precision. The method comprises the following steps of: jumping data reception interruption from a low level to a high level when the network card receives a data packet, and capturing rising edge signal and outputting a single-pulse trigger signal through a shaping circuit; triggering a time recorder in a time generator through the single-pulse trigger signal, immediately recording the current time of the time recorder as time mark information through the time recorder, and transmitting the time mark information to a first-in first-out (FIFO) buffer area; and finally, reading the content of the data packet through a bus by a central processing unit (CPU), accessing the FIFO buffer area through the bus by the CPU, reading the time mark information, acquiring the time of the network card for receiving the data packet, namely acquiring the time mark information corresponding to the data packet. According to the method, when the network card generates the data reception interruption, the time mark which corresponds to the interruption is immediately recorded, the time recording precision is high, and the CPU occupancy rate is reduced.
Description
[technical field]
The present invention relates to a kind of method of high precision record network interface card time of reception.
[background technology]
Existing network interface card packet receiving measurement of time method adopts the mode of CPU supple-settlement, and be specially: after network card chip is received packet, can produce interruption, CPU has no progeny in response, judges whether the packet of receiving is correct, and the time when recording the CPU response and interrupting.This response time is from the time of the timer in CPU inside.Interrupt being left in the basket to the time between these two actions of CPU response terminal from network interface card, it is very large that this time value is affected by cpu load, changes with the variation of cpu load rate, when CPU operation burden is heavy, the large problem of deviation writing time occurs easily, and the Measuring Time value is at random.If CPU is the CPU of ARM type, this time can reach tens to the hundreds of microsecond, if the CPU of DSP type, then the time also can reach a few to tens of microseconds.Only have the situation of hundreds of microsecond interval time for packet, error tens microseconds are difficult to tolerate.
[summary of the invention]
The technical problem to be solved in the present invention is to provide a kind of high precision to record the method for network interface card time of reception.
The present invention is achieved in that
The method of high precision record network interface card time of reception comprises the steps:
Step 1, network interface card are when receiving packet, and data receiver interrupts from the low transition to the high level, and a shaping circuit is caught this rising edge signal and exported a monopulse trigger pip;
Step 2, described monopulse trigger pip trigger the time regulator in the time generator, and described time regulator is recorded as a markers information with the current time of described time generator immediately, and then described time scale information is sent to fifo buffer; Described time scale information is accurate to microsecond;
Step 3, CPU pass through the content of bus read data packet, and CPU reads described time scale information by the described fifo buffer of bus access simultaneously, obtain the time that network interface card receives described packet, namely obtain the time scale information of corresponding described packet.
Further, described time generator is the time of 0.1 microsecond by a date Hour Minute Second counter and one 0.1 microsecond counters generation precision; The current time of date Hour Minute Second counter is disposed by a configuration register in the described time generator, and CPU is by the described configuration register configuration current time of bus access; Simultaneously, the driving clock of described date Hour Minute Second counter and 0.1 microsecond counter shakes or outside pps pulse per second signal from the active clock in inside, and the source that drives clock is set by described configuration register: inner active clock shakes or outside pps pulse per second signal.
Further, when the driving clock of described date Hour Minute Second counter and 0.1 microsecond counter shakes from the active clock in inside, the driving clock of described 0.1 microsecond counter is the shake signal of the 10MHz that produces through the first frequency divider of the active clock in described inside, and the driving clock of described date Hour Minute Second counter is the inside pps pulse per second signal that the active clock in described inside shakes and produces through the second frequency divider; When inner pps pulse per second signal arrives, described 0.1 microsecond counter O reset.
Further, the driving clock of described date Hour Minute Second counter and 0.1 microsecond counter is during from outside pps pulse per second signal, the driving clock of described 0.1 microsecond counter is the successively 10Mhz signal through producing behind pulse width counter and the compensation frequency multiplier of described outside pps pulse per second signal, and the driving clock of described date Hour Minute Second counter is directly provided by outside pps pulse per second signal.
Further, described bus is 16 bit parallel buses.
The present invention has following advantage:
When network interface card produces the data receiver interruption, immediate record should be interrupted corresponding markers, this markers comprises year, month, day, hour, min, second, microsecond information, send into fifo buffer, even like this CPU this interruption that do not make an immediate response, this interrupts complete recording of corresponding markers.CPU is when response is interrupted, and the read data packet content reads the precise time label that the inner FIFO of time regulator can obtain the corresponding data bag simultaneously, and this markers precision is better than 0.1 microsecond (16.67 nanoseconds of resolution).
The present invention records the network interface card time of reception and no longer relies on CPU, so the adjustment of CPU code changes the not impact of measuring accuracy on reality.Even originally used the very poor ARM CPU of real-time, after adopting recording method of the present invention, can obtain very high time precision equally, and CPU no longer needs the overhead time variable, and can automatically upgrade, reduced CPU usage, so CPU needs no longer also timer of expense to obtain the information of microsecond magnitude.
[description of drawings]
The present invention is further illustrated in conjunction with the embodiments with reference to the accompanying drawings.
Fig. 1 is the synoptic diagram of the method for high precision record network interface card time of reception of the present invention.
Fig. 2 is the schematic flow sheet of the method for high precision record network interface card time of reception of the present invention.
[embodiment]
See also illustrated in figures 1 and 2ly, the present invention will be described in detail.
The method of high precision record network interface card time of reception comprises the steps:
Step 1, network interface card are when receiving packet, and data receiver interrupts from the low transition to the high level, and a shaping circuit is caught this rising edge signal and exported a monopulse trigger pip; When the active clock in inside shakes when shaking for the 60MHz clock, the width of described pulse signal was 16.67 nanoseconds;
Step 2, described monopulse trigger pip trigger the time regulator in the time generator, and described time regulator is recorded as a markers information with the current time of described time generator immediately, and then described time scale information is sent to fifo buffer; Described time scale information is accurate to microsecond; Described time regulator can become the time scale information framing markers of 4 words (double byte), the first word is low 16 microsecond information, the second word most-significant byte microsecond information and year information, and the 3rd word is second and minute information, the 4th word is a month date and time information, and described framing mode can customize.Described fifo buffer can be 1Kbyte FIFO, can store 250 time scale informations;
Step 3, CPU pass through the content of bus read data packet, and CPU reads described time scale information by the described fifo buffer of bus access simultaneously, obtain the time that network interface card receives described packet, namely obtain the time scale information of corresponding described packet.Described bus can be 16 buses, when CPU and described fifo buffer adopt the mode of 16 bit parallel buses to carry out communication, comprising 10 bit address lines, 16 position datawires, 1 chip select line, 1 write enable, 1 read enable signal.The time scale information CPU of 4 words only need to can obtain by four fifo buffers of bus access.CPU also by bus from the network interface card read data packet, then the time of integral data bag content and network interface card receive data bag, pass to system.
In the present embodiment, described time generator is the time of 0.1 microsecond by a date Hour Minute Second counter and one 0.1 microsecond counters generation precision.Described date Hour Minute Second counter can count down to from 0: 0: 0 on the 1st January in 2000 on Dec 31,23: 59: 59 in 2099, comprise a plurality of 60 systems and 24 system Counters, can automatically identify the leap year on the described Counter Design, if be the leap year, then automatically increase February 29.The current time of date Hour Minute Second counter is disposed by a configuration register in the described time generator, and CPU can be by the described configuration register configuration current time of bus access.Simultaneously, the driving clock of described date Hour Minute Second counter and 0.1 microsecond counter can shake or outside pps pulse per second signal from the active clock in inside, and the source that drives clock is set by described configuration register: inner active clock shakes or outside pps pulse per second signal.
Now active clock shakes and is example as the high stability clock of 60MHz shakes take inside, and its precision is 0.5PPM, is equivalent to the time in 1 second, maximum deviation 0.5 microseconds, and active clock shakes self because the drift that environmental factor is brought is very little.
When the driving clock of described date Hour Minute Second counter and 0.1 microsecond counter shook from the active clock in inside: the driving clock of described 0.1 microsecond counter was the shake signal of the 10MHz that produces through the first frequency divider of the active clock in described inside, when the active clock in described inside shakes clock for 60MHz when shaking, described the first frequency divider is six frequency dividers, and the signal of described 10MHz is so that count value corresponding 0.1 microsecond just in time; The driving clock of described date Hour Minute Second counter is the inside pps pulse per second signal that the active clock in described inside shakes and produces through the second frequency divider, and described the second frequency divider is 60000000 frequency dividers, is about to the 60MHz clock and becomes the 1Hz clock, be i.e. inner pps pulse per second signal.After the current time of described date Hour Minute Second counter arranges successfully, automatic New count more under inner pulse per second (PPS) drives.When inner pps pulse per second signal arrives, described 0.1 microsecond counter O reset.
When the driving clock of described date Hour Minute Second counter and 0.1 microsecond counter during from outside pps pulse per second signal: the driving clock of described 0.1 microsecond counter is the 10Mhz signal that described outside pps pulse per second signal produces after successively through pulse width counter and compensation frequency multiplier; Described pulse width counter is obtained the count value of interval time (being the pulse per second (PPS) time width) under the 60MHz clock drives between two rising edges of outside pps pulse per second signal.If outside pps pulse per second signal is consistent with inner pps pulse per second signal, then count value is 60000000; If wide 1 microsecond of the inner pulse per second (PPS) width of outside pulse per second (PPS) Width, 1/0.01667=60, then count value is 60000060; If narrow 1 microsecond of the inner pulse per second (PPS) width of outside pulse per second (PPS) Width, then count value is 59999940.Described compensation frequency multiplier, according to the value of pulse width counter, with outside pps pulse per second signal, the compensation frequency multiplication becomes the 10MHz signal.If count value just is 60000000, then frequency multiplier behind the Auto-counting to 6, is just exported a pulse under the 60MHz clock drives, and therefore a corresponding second, 10000000 pulses is arranged.If count value is 60000060, this value is 6.000006 divided by 10000000 values that obtain, and is not integer, can not process by common mode.Therefore when compensating 1000000 countings in the every interval of frequency multiplier, just the counting width is made into 7, other the time still use width 6, a final like this second still to export 1000000 pulse per second (PPS)s.Therefore, the output of described compensation frequency multiplier is a recurrent interval (time width of a upper pulse and next pulse) adjustable 10MHz signal, calculates by outside pulse per second (PPS) width to restore.
After the current time of described date Hour Minute Second counter arranges successfully, automatic New count more under inner pps pulse per second signal or outside pulse per second (PPS) drive.When inner arteries and veins rushed signal or outside pps pulse per second signal second and arrives, described date Hour Minute Second counter was skipped clock 1 second, and with described 0.1 microsecond counter O reset, since 0 microsecond timing.
Need to prove, before the invention process, need to carry out initial work, at first by CPU access bus configuration register is configured, configuration register will be configured to described date Hour Minute Second counter again the current time, then the source of driving time is set by configuration register, opens at last described date Hour Minute Second counter and 0.1 microsecond counter.For network interface card, at first want initialization network interface card register, then clear described fifo buffer opens the network interface card receive interruption again.
The present invention is when network interface card produces the data receiver interruption, immediate record should be interrupted corresponding markers, this markers comprises year, month, day, hour, min, second, microsecond information, send into fifo buffer, even like this CPU this interruption that do not make an immediate response, this interrupts complete recording of corresponding markers.CPU is when response is interrupted, and the read data packet content reads the precise time label that the inner FIFO of time regulator can obtain the corresponding data bag simultaneously, and this markers precision is better than 0.1 microsecond (16.67 nanoseconds of resolution)
The present invention records the network interface card time of reception and no longer relies on CPU, so the adjustment of CPU code changes the not impact of measuring accuracy on reality.Even originally used the very poor ARM CPU of real-time, after adopting recording method of the present invention, can obtain very high time precision equally, and CPU no longer needs the overhead time variable, and can automatically upgrade, reduced CPU usage, so CPU needs no longer also timer of expense to obtain the information of microsecond magnitude.
Although more than described the specific embodiment of the present invention; but being familiar with those skilled in the art is to be understood that; our described specific embodiment is illustrative; rather than for the restriction to scope of the present invention; those of ordinary skill in the art are in modification and the variation of the equivalence of doing according to spirit of the present invention, all should be encompassed in the scope that claim of the present invention protects.
Claims (5)
1. the method for high precision record network interface card time of reception is characterized in that: comprise the steps:
Step 1, network interface card are when receiving packet, and data receiver interrupts from the low transition to the high level, and a shaping circuit is caught this rising edge signal and exported a monopulse trigger pip;
Step 2, described monopulse trigger pip trigger the time regulator in the time generator, and described time regulator is recorded as a markers information with the current time of described time generator immediately, and then described time scale information is sent to fifo buffer; Described time scale information is accurate to microsecond;
Step 3, CPU pass through the content of bus read data packet, and CPU reads described time scale information by the described fifo buffer of bus access simultaneously, obtain the time that network interface card receives described packet, namely obtain the time scale information of corresponding described packet.
2. high precision according to claim 1 records the method for network interface card time of reception, it is characterized in that: it is the time of 0.1 microsecond that described time generator produces precision by a date Hour Minute Second counter and one 0.1 microsecond counters; The current time of date Hour Minute Second counter is disposed by a configuration register in the described time generator, and CPU is by the described configuration register configuration current time of bus access; Simultaneously, the driving clock of described date Hour Minute Second counter and 0.1 microsecond counter shakes or outside pps pulse per second signal from the active clock in inside, and the source that drives clock is set by described configuration register: inner active clock shakes or outside pps pulse per second signal.
3. high precision according to claim 2 records the method for network interface card time of reception, it is characterized in that: when the driving clock of described date Hour Minute Second counter and 0.1 microsecond counter shakes from the active clock in inside, the driving clock of described 0.1 microsecond counter is the shake signal of the 10MHz that produces through the first frequency divider of the active clock in described inside, and the driving clock of described date Hour Minute Second counter is the inside pps pulse per second signal that the active clock in described inside shakes and produces through the second frequency divider; When inner pps pulse per second signal arrives, described 0.1 microsecond counter O reset.
4. high precision according to claim 2 records the method for network interface card time of reception, it is characterized in that: the driving clock of described date Hour Minute Second counter and 0.1 microsecond counter is during from outside pps pulse per second signal, the driving clock of described 0.1 microsecond counter is the successively 10MHz signal through producing behind pulse width counter and the compensation frequency multiplier of described outside pps pulse per second signal, and the driving clock of described date Hour Minute Second counter is directly provided by outside pps pulse per second signal.
5. high precision according to claim 1 records the method for network interface card time of reception, and it is characterized in that: described bus is 16 bit parallel buses.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103955255A (en) * | 2014-04-28 | 2014-07-30 | 国家电网公司 | Accurate measurement system based on FPG binary input event, and method thereof |
| CN106557019A (en) * | 2015-09-16 | 2017-04-05 | 精工爱普生株式会社 | Time set and clocking method and electronic equipment |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101388741A (en) * | 2008-10-24 | 2009-03-18 | 中国科学院计算技术研究所 | Highly precised time synchronization device, system and method for computer network |
| US20090310572A1 (en) * | 2008-06-17 | 2009-12-17 | Shu Wang | MAC layer timestamping approach for emerging wireless sensor platform and communication architecture |
-
2012
- 2012-07-24 CN CN201210258063.8A patent/CN102855172B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090310572A1 (en) * | 2008-06-17 | 2009-12-17 | Shu Wang | MAC layer timestamping approach for emerging wireless sensor platform and communication architecture |
| CN101388741A (en) * | 2008-10-24 | 2009-03-18 | 中国科学院计算技术研究所 | Highly precised time synchronization device, system and method for computer network |
Non-Patent Citations (1)
| Title |
|---|
| 黎文伟等: "基于通用PC架构的高精度网络时延测量方法", 《软件学报》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103955255A (en) * | 2014-04-28 | 2014-07-30 | 国家电网公司 | Accurate measurement system based on FPG binary input event, and method thereof |
| CN106557019A (en) * | 2015-09-16 | 2017-04-05 | 精工爱普生株式会社 | Time set and clocking method and electronic equipment |
| CN106557019B (en) * | 2015-09-16 | 2020-05-12 | 精工爱普生株式会社 | Timing device and timing method and electronic equipment |
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