CN102842662B - Self-assembly preparation method for nano-pillar array compound semiconductor device - Google Patents
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Abstract
A self-assembly preparation method for a nano-pillar array compound semiconductor device comprises the following steps: (1) pumping a layer of metal source reactant into the surface of a conductive substrate in advance; (2) annealing to form metal island particles; (3) pumping in III and V reactants for epitaxial growth of a semiconductor nano-pillar array; (4) accelerating lateral growth of semiconductor nano-pillars and doping an N-type impurity into a source substance to form a semiconductor nano-pillar array of which the surface is N-type; (5) depositing an insulating layer on the surfaces of the nano-pillars and the exposed surface of the conductive substrate among the nano-pillars and etching the insulating layer on the side walls of the nano-pillars through an etching liquid; (6) forming nano-pillar array devices on the surfaces of the nano-pillars; (7) filling a conductive substance among the nano-pillar arrays to form an electrode layer; and (8) manufacturing P-type electrodes in the electrode layer and manufacturing N-type electrodes on the conductive substrate.
Description
Technical field
The present invention relates to a kind of preparation of nano column array compound semiconductor device, be specifically related to a kind of method of vapor phase epitaxial growth high-quality gallium nitride light-emitting diode and gallium nitride lasers.
Background technology
With the wide-band gap material that gallium nitride (GaN) is representative, be the third generation semi-conducting material after Si and GaAs, be used for making the electronic devices such as light-emitting diode, laser, detector, high-frequency high-power transistor.
Owing to can't obtain high-quality commercial bulk GaN crystal at present, the general foreign substrate that adopts carrys out extension acquisition GaN film.But have larger lattice mismatch between GaN and Sapphire Substrate (or Si substrate), cause epitaxial loayer to produce dislocation, this dislocation can be expanded and pass whole epitaxial loayer, limits the raising of GaN device performance.For less bits dislocation density, improve the quality of semiconductive thin film, improving one's methods of the multiple raising epitaxial material quality that now grown up, as low temperature buffer layer technology, insert layer technology, horizontal extension technology (ELOG) etc.
Traditional two-step method low temperature growth buffer layer technology be pass into source reactant low-temperature epitaxy skim after, carry out high annealing, make low temperature buffer layer become low-density nucleus.Traditional two-step method low temperature growth buffer layer technology effectively can be lowered into cuclear density, and its nucleation density can reach 2.0 × 10
8cm
-2.When merging as nuclear island, dislocation can produce from the interface merged, and extends to whole body material.Therefore dislocation density and nucleation density have very large relevance, and its corresponding relation linearly changes, and the dislocation density of two-step method growing gallium nitride epitaxial film can reach 8 × 10
9cm
-2.Be lowered into cuclear density so that dislocation density in order to lower, insert layer and horizontal extension technology are introduced into epitaxial growth.Insert layer technology plays very large effect being lowered in cuclear density and dislocation density, but the degree that nucleation density reduces is large not, and its epitaxial loayer dislocation density is still very large.And horizontal extension technology also exists some defects in reduction dislocation density process: window and mask dimensions belong to micron level, merge the time long, cost is higher; Window region and mask regions epitaxial layer quality different, cause device performance uneven, be difficult to large-area applications; Technics comparing is complicated.
Because body crystalline quality of material is poor, defect concentration is large, result in the shortcomings such as the light extraction efficiency of gallium nitride based LED is low.Again because the gallium nitride of C surface sapphire growth has stronger polarity, growth in GaN polar surface causes GaN device piezoelectric effect in polar surface obvious, cause band curvature obvious, significantly limit the combined efficiency in electronics and hole, device performance is subject to very large constraint.In addition, in polar surface, growing InGaN also limit mixing of In, makes green glow lower to the device efficiency of gold-tinted section, defines green glow band gap.In addition, gallium nitride based Refractive Index of Material is higher than normally used substrate or chip encapsulation material, and this causes the light extraction comparison difficulty of device.The existence of these problems, makes device performance degradation above, the lost of life, and luminous efficiency reduces, and light extraction efficiency is low, constrains fast development and the application of gallium nitride based material.
In sum, there is following problem in traditional method preparing semiconductor device all more or less: (1) defect concentration is higher, easily forms non-radiative recombination center, reduces the internal quantum efficiency of device; (2) semiconductor device in polar surface easily introduces stress, causes band curvature, and electron hole greatly reduces at the combined efficiency in district of having chance with; (3) the manufacture method light of conventional semiconductor devices easily forms total reflection at media interior, causes light extraction efficiency to decline; (4) light-emitting area of traditional surface light-emitting device is only the surface area size of device, and light-emitting area is less.
Summary of the invention
The object of the invention is to overcome above-mentioned traditional existing methods defect, the problem that the dislocation density produced in solution conventional method growing semiconductor device process is excessive.Reducing on the basis of dislocation density largely, preparing nano column array semiconductor device, the general defect of device is reduced, improving the internal quantum efficiency of device.By the device growth on nano column array non-polar plane, avoid the generation due to compression in polar surface, improve the efficiency of the compound of device inside charge carrier.In addition, the device layout of nano column array can solve the too little defect of semiconductor device light-emitting area, improves the utilance of light.Further, nano column array itself is similar to rough surface or photon crystal device, has greatly improved to the extraction efficiency of light.
The present invention realizes in the following manner:
(1) with reference to accompanying drawing 1, when the surface temperature of conductive substrates 1 is elevated to 500 DEG C ~ 600 DEG C, pass into source metal reactant 3 ~ 5 minutes, source metal reactant is decomposed to form metal level 2 at this temperature.The material of conductive substrates 1 is selected from the one in silicon, carborundum, copper, nickel, chromium.Described source metal reactant should have following properties: 1, enough resolve into metallic atom when high temperature; 2, the fusing point of metal lower (<700 DEG C), boiling point higher (>1700 DEG C); 3, the metal after decomposing in conductive substrates 1 diffusion into the surface, can form metal ball particle.Concerning MOCVD growing GaN, the metal of source metal reactant be selected from Ga, In, Al one or more.
(2) with reference to accompanying drawing 2, reative cell continues to heat up, and carries out annealing in process, metal level 2 is polymerized to be dispersed in the island particle 3 on conductive substrates 1 surface, this island particle 3 using as the catalyst in self-assembled growth process, at low V/III than becoming column to become nuclear island with longitudinal growth under low temperature.The island particle 3 of metal is 1.0 × 10 in the distribution density of conductive substrates 1
6cm
-2~ 3.0 × 10
7cm
-2.
(3) with reference to accompanying drawing 3 and 4, reaction chamber temperature is brought up to 800 ~ 1000 DEG C, passes into III and V race reactant, such as, trimethyl indium or trimethyl gallium can be used as III source, ammonia as group V source, N
2as reaction carrier gas, V/III ratio is set to 50 ~ 200, now metallic island particle 3 carries out chemical reaction as the catalyst of nucleation, surface distributed has the place of metal nucleation point that chemical reaction generation nucleus 4 can occur, and then form semiconductor nano-pillar array 5, and do not have the exposed place of catalyst can not form nucleus 4.Reaction source gas nucleation process is on the surface of a substrate realized by gas-liquid-solid three steps, lower than tradition gas-solid nucleated directly potential barrier, is easy to form nucleus 4.And low V/III is than the longitudinal growth of favors low temperature in nucleus 4, realize accurately controlling by control temperature, time and V/III comparison nucleus 4 diameter, height and density.Diameter 500 ~ the 800nm of semiconductor nano-pillar array 5, height 800 ~ 2000nm, forms the semiconductor nano-pillar array 5 of the intrinsic be fully paved with in conductive substrates.
(4) with reference to accompanying drawing 5, in epitaxial device, continue to raise reaction chamber temperature to 1050 DEG C ~ 1100 DEG C, increase V/III than to 1000 ~ 2000, semiconductor nano-pillar array 5 lateral growth rate is accelerated, and mixes N-type impurity simultaneously, obtains N-type nano column array 6.N-type dopant can be one or more in C, Si, Ge, Sn, Pb, O, S, Se, Te, Po and Be; By to temperature and V/III than the speed controlling lateral growth, and extend growth time, the N-type cover layer of different-thickness can be obtained.In the present invention, Controlling Growth Rate is at 1.5 ~ 4 μm/h, and growth time is 5 ~ 10 minutes, and N-type overburden cover is 300nm ~ 800nm, obtains the N-type nano column array 6 of neat normalizing.
(5) with reference to accompanying drawing 6, reative cell is cooled to room temperature, takes out the conductive substrates 1 with N-type nano column array 6, and uses PEVCD growing silicon oxide (SiO
2) or silicon nitride (Si
xn), conductive substrates 1 exposed surface between N-type nano column array 6 surface and N-type nano column array 6 grows insulating barrier 7.Control growth temperature at 200 ~ 300 DEG C, the silane (SiH of 5%
4) 150 ~ 300 liters/min, laughing gas (N
2o) 900 ~ 1100 liters/min, SiH
4: N
2o=1:5.Growth 3 ~ 5min, obtaining thickness is the insulating barrier 7 that 30 ~ 100nm is thick.After having grown insulating barrier 7, use B.O.E(hydrogen fluoride: ammonium fluoride=1:6) solution rinsing 5 ~ 10 minutes, remove the SiO on N-type nano column array 6 sidewall
2.
(6) with reference to accompanying drawing 7, epitaxial growth is proceeded to the row of the conductive substrates 1 with N-type nano column array 6 having grown insulating barrier 7, is formed by the composite bed 8 formed of quantum well layer, electronic barrier layer and P-type layer.Such as: trimethyl indium or trimethyl gallium can be used as III source, ammonia as group V source, N
2as reaction carrier gas, temperature rises to 650 ~ 800 DEG C, and pressure limit 100 ~ 300 mBar, V/III, than scope 1000 ~ 2000, grow In
xga
yn/GaN(0≤X≤1; 0≤Y≤1) quantum well structure, quantum well structure periodicity is 5 ~ 15; Use trimethyl indium, trimethyl aluminium, trimethyl gallium as III source, ammonia as group V source, N
2and H
2as reaction carrier gas, temperature rises to 800 ~ 1000 DEG C, and pressure limit 100 ~ 300 mBar, V/III, than scope 1000 ~ 2000, grow Al
xga
yn(0≤X≤1; 0≤Y≤1) electronic barrier layer, the thickness of electronic barrier layer is 20 ~ 100nm; Continue to keep temperature 800 ~ 1000 DEG C, pressure limit 100 ~ 300mBar, V/III is than scope 1000 ~ 2000, growing P-type gallium nitride layer, at least one in use Be, Mg, Ca, Sr, Ba and Ra is as doped source, growth 5 ~ 20min, P-type layer thickness is 150 ~ 300nm, thus obtains from N-type, quantum well to the complete nano column array semiconductor device of one, P type.Wherein insulating barrier 7 comes isolated for the side of P type and N-type, in order to avoid N-type P type directly contacts, produces electric leakage.
(7) with reference to accompanying drawing 8, using coating machine evaporation one deck conductive materials on the nano column array semiconductor device grown, such as, can be indium tin oxide (ITO), forms electrode layer 9, the gap of nano column array is all filled up, forms good contact layer.
(8) continue in electrode layer 9, to make P-type electrode 10 with reference to accompanying drawing 8, conductive substrates 1 makes N-type electrode 11, form a complete chip.
The device that above-mentioned technique is formed can be that LED, LD, detector, solar cell, MEMS, HEMT are wherein a kind of, only needs the structure of the composite bed 8 changing nano-pillar surface according to different device feature.
The present invention has following outstanding advantages:
1, the size of metal nucleation point and density accurately can be controlled by the flow and annealing time controlling source metal reactant;
2, the density of nano-pillar semiconductor can be regulated by the thickness and annealing temperature controlling metal;
3, the size of nano-pillar can by regulating temperature and V/III than accurately controlling;
4, large scale nucleus can contribute to lateral growth, and low nucleation density considerably reduces the dislocation produced when nucleus merges, and dislocation density is down to ~ and 10
6cm
-2the order of magnitude, decreases the non-radiative recombination center of nano-pillar device, thus improves the internal quantum efficiency of nano-pillar semiconductor device;
5, simultaneously due to the non-polar character of side direction, the semiconductor device on non-polar plane can be obtained, significantly reduce the band curvature because compression causes, thus improve electronics, hole wave functions plyability, improve electronics, hole-recombination efficiency;
6, for body semiconductor device, nano-pillar semiconductor device drastically increases light-emitting area;
7, because lateral direction light emission erect by nano-pillar semiconductor device, decrease the light lost because of total reflection, drastically increase the extraction efficiency of device;
8, due to the raising of internal quantum efficiency and extraction efficiency, luminous efficiency can be improved significantly;
9, straight-down negative project organization can allow electric current fully extend to each nano-pillar device, improves current injection efficiency, thus improves luminous efficiency;
10, single nano-pillar device directly directly contacts with N-type layer with P-type layer, and device can dispel the heat well, improves the life-span of device.
Accompanying drawing explanation
Accompanying drawing 1 is that in conductive substrates, source metal reactant resolves into thin metal layer schematic diagram.
Accompanying drawing 2 is the metallic particles schematic diagrames formed after annealing.
Accompanying drawing 3 is that nano-pillar forms schematic diagram.
Accompanying drawing 4 is nano-pillar longitudinal growth schematic diagrames.
Accompanying drawing 5 is N-type nano column array growth schematic diagrames.
Accompanying drawing 6 is insulating layer growth schematic diagrames.
Accompanying drawing 7 N-type nano-pillar grows Multiple Quantum Well and P-type layer schematic diagram.
Accompanying drawing 8 is that nano column array semiconductor device makes schematic diagram.
Accompanying drawing reference numerals is as follows: conductive substrates 1 metal level 2 island particle 3 nucleus 4 nano column array 5 N-type nano column array 6 insulating barrier 7 composite bed 8 electrode layer 9 P-type electrode 10 N-type electrode 11.
Embodiment
Elaborate below in conjunction with the embodiment of accompanying drawing to the self-assembly preparation method thereof of a kind of nano column array compound semiconductor device provided by the invention.
Embodiment one, nano column array gallium nitride light-emitting diode self assembly technology of preparing, comprises a few step below:
1, MOCVD reaction chamber temperature rises to 500 DEG C, passes into trimethyl gallium 3 minutes, at Si(0001) there is decomposition reaction in substrate, form the thin metal layer of 10nm.
2, through 3 minutes, temperature is elevated to 900 DEG C, metal condenses becomes bead, and density is 2.3 × 10
6cm
-2, the diameter 400 ~ 600nm of bead, duty ratio is 65%.
3, temperature is maintained 900 DEG C, pass into hydrogen, trimethyl gallium and ammonia 2 minutes, gallium nitride nucleus is formed bottom gold grain, diameter 400 ~ 600nm.
4, temperature is increased to 1000 DEG C, pass into hydrogen, trimethyl gallium (50 liters/min) and ammonia 20 minutes, wherein V/III ratio is 200, the longitudinal formation column structure of growing up of gallium nitride nucleus, nano-pillar average height 1500nm, gallium particle total overall reaction generates gallium nitride, forms intrinsic gallium nitride nano column array.
5, temperature is increased to 1050 DEG C, and pass into hydrogen, trimethyl gallium (40 liters/min) and ammonia 6 minutes, wherein V/III ratio is 1000, and gallium nitride nucleus is laterally grown up, and mixes SiH
4(200ppm), this layer of N-type GaN mix Si amount be 1.0 × 10
19cm
-3, form the N-type nano column array that 300nm is thick.
6, PEVCD is used to grow silicon dioxide (SiO after taking out
2) mask layer, control growth temperature at 200 DEG C, the silane (SiH of 5%
4) 150 liters/min, laughing gas (N
2o) 900 liters/min, SiH
4: N
2o=1:5.Growth 3min, obtaining thickness is the mask layer that 100nm is thick.After having grown mask layer, use B.O.E(hydrogen fluoride: ammonium fluoride=1:6) solution rinsing 5 minutes, remove the SiO on nano-pillar sidewall
2, formed and there is SiO
2the n type gallium nitride nano column array of mask layer.
7, grow 5 cycle InGaN/GaN quantum well package covering layer, the thickness of quantum well is InGaN:2nm; GaN:8nm; The AlGaN electronic barrier layer of long 5 minutes subsequently, wherein Al content is 8%, and this layer thickness is 20nm; Finally grow the P type GaN of 10 minutes, Mg incorporation is 1.0 × 10
20cm
-3, thickness is 150nm.This step terminates the nano column array gallium nitride light-emitting diode defining surface of silicon.
8, between the nano-pillar device grown, insert ITO transparency conducting layer, completely nano-pillar is covered.Simultaneously the Ni/Au electrode of evaporation 10nm on ITO top and conductive substrates, forms P electrode and N electrode, forms straight-down negative gallium nitride nano column array light-emitting diode.
The LED component that above-mentioned technique is formed is of a size of 200 μm ' 380 μm, and make with after epoxy encapsulation after chip, during integrating sphere measurement 20mA, luminous power is 35mW, and luminous efficiency reaches 150lm/W.
Embodiment two, nano column array gallium nitride lasers self assembly technology of preparing, comprises a few step below:
1, MOCVD reaction chamber temperature rises to 550 DEG C, passes into trimethyl gallium 4 minutes, at Si(0001) there is decomposition reaction in substrate, form the thin metal layer of 8nm.
2, through 3 minutes, temperature is elevated to 850 DEG C, metal condenses becomes bead, and density is 2.0 × 10
6cm
-2, the diameter 400 ~ 600nm of bead, duty ratio is 65%.
3, temperature is maintained 900 DEG C, pass into hydrogen, trimethyl gallium and ammonia 2 minutes, gallium nitride nucleus is formed bottom gold grain, diameter 400 ~ 600nm.
4, temperature is increased to 1000 DEG C, pass into hydrogen, trimethyl gallium (50 liters/min) and ammonia 20 minutes, wherein V/III ratio is 200, the longitudinal formation column structure of growing up of gallium nitride nucleus, nano-pillar average height 1200nm, gallium particle total overall reaction generates gallium nitride, forms intrinsic gallium nitride nano column array.
5, temperature is increased to 1100 DEG C, and pass into hydrogen, trimethyl gallium (40 liters/min) and ammonia 6 minutes, wherein V/III ratio is 1800, and gallium nitride nucleus is laterally grown up, and mixes SiH
4(200ppm), this layer of N-type GaN mix Si amount be 1.0 × 10
19cm
-3, form the N-type nano column array that 250nm is thick.
6, take out use PEVCD and grow silicon dioxide (SiO
2) mask layer (not changing), control growth temperature at 280 DEG C, the silane (SiH of 5%
4) 300 liters/min, laughing gas (N
2o) 1050 liters/min, SiH4:N
2o=1:5.Growth 6min, obtaining thickness is the mask layer that 100nm is thick.After having grown mask layer, use B.O.E(hydrogen fluoride: ammonium fluoride=1:6) solution rinsing 10 minutes, remove the SiO on nano-pillar sidewall
2, formed and there is SiO
2the n type gallium nitride nano column array of mask layer.
7, the thick In of 50nm is grown
xga
yn integument, wherein x=0.15, y=0.85, form N-type ducting layer structure; Continued growth 5 cycle InGaN/GaN quantum well package covering layer, the thickness of quantum well is InGaN:2nm; GaN:8nm; The AlGaN electronic barrier layer of long 5 minutes subsequently, wherein Al content is 8%, and this layer thickness is 20nm; And then the thick In of 70nm is grown
xga
yn integument, wherein x=0.15, y=0.85, form P type ducting layer structure; Finally grow the P type GaN of 10 minutes, Mg incorporation is 1.0 × 10
20cm
-3, thickness is 150nm.This step terminates rear SiC substrate defines nano column array gallium nitride lasers.
8, evaporation one deck 10nm silver thin layer on nano-pillar sidewall, forms light wave genetic horizon; Between the nano-pillar device of the complete silver-colored thin layer of evaporation, insert ITO transparency conducting layer, completely nano-pillar is covered.Simultaneously the Ni/Au electrode of evaporation 10nm on ITO top and conductive substrates, forms P electrode and N electrode, forms gallium nitride nano column array laser.
The threshold current 50mA(2.4KA/cm of the gallium nitride nano column array laser that above-mentioned technique is formed
2), threshold voltage is 4.2V.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (9)
1. a self-assembly preparation method thereof for nano column array compound semiconductor device, is characterized in that, comprises the steps:
(1) layer of metal source reactant is passed in advance on conductive substrates surface, in order at conductive substrates forming metal layer on surface;
(2) annealing is implemented to metal level and form metallic island particle;
(3) pass into III and V race reactant, utilize metallic island particle that step (2) is formed as nanocolumn growth catalyst, epitaxial semiconductor nano column array, and be greater than cross growth speed along metal island longitudinal growth speed;
(4) improve temperature, and increase V/III ratio, semiconductor nano-pillar lateral growth is accelerated, and mix N-type impurity in the material of source, form the semiconductor nano-pillar array that surface is N-type;
(5) the conductive substrates exposed surface between nano-pillar surface and nano-pillar deposits a layer insulating, and uses the insulating barrier on etching liquid etching nano-pillar sidewall, the insulating barrier on sidewall is all etched away;
(6) in nano-pillar surface epitaxial growth quantum well layer and P-type layer, nano column array device is formed;
(7) filled conductive material between nano column array, forms electrode layer;
(8) in electrode layer, make P-type electrode, conductive substrates makes N-type electrode, N-type electrode is formed in below conductive substrates, and N-type electrode contacts with the lower surface of conductive substrates.
2. the self-assembly preparation method thereof of nano column array compound semiconductor device according to claim 1, is characterized in that: the metal of the source metal reactant passed in advance in step (1) be selected from Ga, In, Al one or more.
3. the self-assembly preparation method thereof of nano column array compound semiconductor device according to claim 1, is characterized in that: the material of conductive substrates is selected from the one in silicon, carborundum, copper, nickel, chromium.
4. the self-assembly preparation method thereof of nano column array compound semiconductor device according to claim 1, is characterized in that: the metallic island uniform particles in step (2) is distributed in substrate surface.
5. the self-assembly preparation method thereof of nano column array compound semiconductor device according to claim 1, is characterized in that: epitaxial growth equipment adopts metal organic chemical vapor deposition equipment, molecular beam epitaxial device and hydride gas-phase epitaxy equipment one wherein.
6. the self-assembly preparation method thereof of nano column array compound semiconductor device according to claim 1, is characterized in that: the density range of the metallic island particle in step (2) is 1.0 × 10
6cm
-2~ 3.0 × 10
7cm
-2.
7. the self-assembly preparation method thereof of nano column array compound semiconductor device according to claim 1, is characterized in that: the diameter 500 ~ 800nm of the semiconductor nano-pillar array in step (3), height 800 ~ 2000nm.
8. the self-assembly preparation method thereof of nano column array compound semiconductor device according to claim 1, is characterized in that: the insulating layer material in step (5) is selected from the one in silica and silicon nitride.
9. the self-assembly preparation method thereof of nano column array compound semiconductor device according to claim 1, it is characterized in that: the dopant of the P-type layer in described step (6) is selected from least one in Be, Mg, Ca, Sr, Ba and Ra, the N-type dopant in described step (5) is selected from least one in C, Si, Ge, Sn, Pb, O, S, Se, Te, Po and Be.
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| CN103757693B (en) * | 2014-01-09 | 2016-07-13 | 华南师范大学 | A kind of growing method of GaN nano wire |
| NL2014588B1 (en) * | 2015-04-07 | 2017-01-19 | Stichting Energieonderzoek Centrum Nederland | Rechargeable battery and method for manufacturing the same. |
| CN105862122B (en) * | 2016-05-09 | 2018-08-03 | 北京大学 | Indium antimonide nano wire based on multistep Glancing angledeposition is prepared and additive Mn method |
| CN106206870B (en) * | 2016-07-25 | 2018-05-15 | 太原理工大学 | A kind of preparation method of GaN nanometer stick arrays structure |
| CN106384763B (en) * | 2016-10-31 | 2019-01-29 | 华南理工大学 | Nonpolar InGaN/GaN multiple quantum wells nano-pillar and its preparation method |
| CN108231545B (en) * | 2018-01-11 | 2020-09-22 | 华南理工大学 | InN nano-column epitaxial wafer grown on copper foil substrate and preparation method thereof |
| CN114808119B (en) * | 2022-03-14 | 2023-11-07 | 吉林大学 | InN self-assembled nano-column preparation method and product thereof |
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| EP0838865A2 (en) * | 1996-10-28 | 1998-04-29 | Sony Corporation | Quantum wires formed on a substrate, manufacturing method thereof, and device having quantum wires on a substrate |
| CN102037165A (en) * | 2008-03-20 | 2011-04-27 | 综合工科学校 | Method for producing nanostructures on metal oxide substrate, and thin film device |
| CN101593675A (en) * | 2008-05-28 | 2009-12-02 | 中国科学院半导体研究所 | A kind of method of growing active area epitaxial wafer of nanometer folded structure |
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