CN102832903A - Capacitance multiplier - Google Patents

Abstract

The invention provides a capacitance multiplier, which adopts an active device, the area of the active device is smaller than that of a passive device, and the capacitance multiplier only comprises four transistors and one capacitor, and has a simple structure.

Description

A kind of capacity multiplier

Technical field

The present invention relates to technical field of integrated circuits, particularly a kind of capacity multiplier.

Background technology

Capacity multiplier can be applied to the loop filter in the phase-locked loop (PLL, Phase Locked Loop).Traditional loop filter adopts passive capacitive and resistive arrangement circuit, and under the PLL performance demands, the value of electric capacity will be very big.If method design loop filter on the employing sheet, technology decision electric capacity takies very big area, has surpassed 50% of whole PLL area.Along with the technology characteristics size is constantly dwindled, transistorized area also constantly dwindles, but very little to the area effect of passive device, thereby has restricted reducing of chip cost.

In sum, the area of present capacity multiplier is bigger, and the ratio that takies the entire chip area is more, will increase the cost of entire chip like this.Simultaneously, the circuit structure when present capacity multiplier adopts passive device is complicated, therefore, and with the noiseproof feature that influences entire circuit.

Summary of the invention

The technical problem that the present invention will solve provides a kind of capacity multiplier, and is simple in structure, and area is less, can reduce the cost of entire chip, and improves the noiseproof feature of entire circuit.

The embodiment of the invention provides a kind of capacity multiplier, comprising: the first transistor, transistor seconds, the 3rd transistor, the 4th transistor and first electric capacity;

The collector electrode of said the first transistor connects first node, grounded emitter, and base stage connects first bias voltage;

The collector electrode of said transistor seconds connects Section Point, grounded emitter, and base stage connects said first bias voltage;

The said the 3rd transistorized collector electrode connects power supply, and emitter connects said first node, and base stage connects second bias voltage;

The said the 4th transistorized collector electrode connects power supply, and emitter connects said Section Point, and base stage connects said second bias voltage;

One end of said first electric capacity connects said first node, and the other end of said first electric capacity connects said Section Point;

Said Section Point is as the output of this capacity multiplier.

Preferably, said the first transistor and transistor seconds are in the operate in saturation district by said first bias voltage control.

Preferably, said the 3rd transistor and the 4th transistor are in the forward service area by said second bias voltage control.

Preferably, the emitter region area of said transistor seconds be the first transistor the emitter region area N doubly;

The said the 4th transistorized emitter region area is N a times of the 3rd transistorized emitter region area; Said N is an integer.

Compared with prior art, the present invention has the following advantages:

The capacity multiplier that the embodiment of the invention provides adopts active device, and the area of active device itself is just little than passive device, and this capacity multiplier only comprises four transistors and an electric capacity; Simple in structure, therefore, the area of capacity multiplier provided by the invention is less; Can reduce the cost of entire chip; And because device is less, the overall noise that produces is also little, helps to improve the noiseproof feature of entire circuit.

Description of drawings

Fig. 1 is embodiment one circuit diagram of the capacity multiplier that provides of the embodiment of the invention;

Fig. 2 is embodiment two circuit diagrams of the capacity multiplier that provides of the embodiment of the invention.

Embodiment

For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.

Referring to Fig. 1, this figure is the circuit diagram of the capacity multiplier embodiment one that provides of the embodiment of the invention.

The capacity multiplier that present embodiment provides comprises: the first transistor Q1, transistor seconds Q2, the 3rd transistor Q3, the 4th transistor Q4 and first capacitor C 0;

The collector electrode of said the first transistor Q1 connects first node A, grounded emitter, and base stage connects the first bias voltage VB1;

The collector electrode of said transistor seconds Q2 connects Section Point B, grounded emitter, and base stage connects the said first bias voltage VB1;

The collector electrode of said the 3rd transistor Q3 connects power supply, and this power supply is not shown; Emitter connects said first node A, and base stage connects the second bias voltage VB2;

The collector electrode of said the 4th transistor Q4 connects power supply, and emitter connects said Section Point B, and base stage connects the said second bias voltage VB2;

One end of said first capacitor C 0 connects said first node A, and the other end of said first capacitor C 0 connects said Section Point B;

Said Section Point B is as the output OUT of this capacity multiplier.

The capacity multiplier that the embodiment of the invention provides adopts active device, and the area of active device itself is just little than passive device, and this capacity multiplier only comprises four transistors and an electric capacity; Simple in structure, therefore, the area of the capacity multiplier that the application provides is less; Can reduce the cost of entire chip; And because device is less, the overall noise that produces is also little, helps to improve the noiseproof feature of entire circuit.

Introduce the concrete operation principle of the capacity multiplier that the embodiment of the invention provides below.

Said the first transistor Q1 and transistor seconds Q2 are in the saturation region by said first bias voltage VB1 control, and promptly emitter junction and collector junction are forward bias, thereby make its equivalence for voltage source, for capacity multiplier provides power supply.

Said the 3rd transistor Q3 and the 4th transistor Q4 are in the forward service area by said second bias voltage VB2 control, i.e. forward bias is become in emission, and current collection is become reverse bias.These two transistors play the effect of amplifying the capacity multiplier electric current.

The emitter region area of said transistor seconds Q2 be the first transistor Q1 the emitter region area N doubly;

The emitter region area of said the 4th transistor Q4 be the 3rd transistor Q3 the emitter region area N doubly; Said N is an integer.

Need to prove that said Q1, Q2, Q3 and Q4 can be a transistor, the transistor that also can be connected in parallel for a plurality of transistors, as shown in Figure 2 only the signal as embodiment and and not exclusive connected mode.Only show Q1, Q2, Q3 and Q4 among Fig. 2 and be formed in parallel by two transistors respectively, it is understandable that, in order to form the ratio of emitter region area, can be according to actual needs and transistorized individual difference select the transistor of different numbers to carry out parallel connection.

It is understandable that, when above transistor is to be connected in parallel when constituting by a plurality of transistors, the emitter region area of said Q2 be the N of the emitter region area of Q1 doubly be appreciated that into the N of the transistorized emitter region area sum of parallel connection doubly; Perhaps by parallelly connected N times of forming the emitter region area of the transistor of different numbers; For example, the Q2 position is by N transistor parallel connection, and the Q1 position is only by a transistor; And the transistor of each the transistor AND gate Q1 position in the Q2 position is identical.

In a word, if guarantee the transistorized emitter region area sum of Q2 position be the Q1 position transistorized emitter region area sum N doubly, Q4 and Q3 are similar.

The current i of the output OUT of this capacity multiplier _OUTForm by two parts electric current: i ₁And i ₂i ₁Be the collector current sum of the first transistor Q1 and the 3rd transistor Q3, i ₂Collector current sum for transistor seconds Q2 and the 4th transistor Q4.Therefore, the current i of output OUT _OUTCan be expressed as:

i _OUT=i ₁+i ₂=(i _c,Q1+i _c,Q3)+(i _c,Q2+i _c,Q4) （1）

Wherein, i _{C, Q1}, i _{C, Q2}, i _{C, Q3}, i _{C, Q4}Be respectively the collector current of transistor (Q1, Q2, Q3, Q4).

Known by Fig. 1, current i ₁Can be by output voltage v _OUTBe expressed as:

i ₁=sC0/(1+sC0/(g _m,Q1+g _m,Q3))v _OUT （2）

Wherein, g _{M, Q1}, g _{M, Q3}Represent the mutual conductance of the first transistor Q1 and the 3rd transistor Q3 respectively.Pass through i ₂=Ni ₁, the output impedance Z of this capacity multiplier _OUTCan be expressed as:

Z _OUT=(1+sC0/(g _m,Q1+g _m,Q3))/sC0(N+1) （3）

From formula (3), can draw, at bandwidth omega=(g _{M, Q1}+ g _{M, Q3}Under the)/C0, the electric capacity of capacity multiplier be first capacitor C 0 (N+1) doubly.

Can know that by above analysis the capacity multiplier that present embodiment provides has only used Q1, Q2, Q3 and four transistors of Q4 and an electric capacity just can the electric capacity of first capacitor C 0 be increased N doubly, has realized by the purpose that realizes large bulk capacitance than the electric capacity of low capacity.

The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention.Any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the method for above-mentioned announcement capable of using and technology contents are made many possible changes and modification to technical scheme of the present invention, or are revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.

Claims (4)

1. a capacity multiplier is characterized in that, comprising: the first transistor, transistor seconds, the 3rd transistor, the 4th transistor and first electric capacity;

The collector electrode of said the first transistor connects first node, grounded emitter, and base stage connects first bias voltage;

The collector electrode of said transistor seconds connects Section Point, grounded emitter, and base stage connects said first bias voltage;

The said the 3rd transistorized collector electrode connects power supply, and emitter connects said first node, and base stage connects second bias voltage;

The said the 4th transistorized collector electrode connects power supply, and emitter connects said Section Point, and base stage connects said second bias voltage;

One end of said first electric capacity connects said first node, and the other end of said first electric capacity connects said Section Point;

Said Section Point is as the output of this capacity multiplier.

2. capacity multiplier according to claim 1 is characterized in that, said the first transistor and transistor seconds are in the operate in saturation district by said first bias voltage control.

3. capacity multiplier according to claim 1 is characterized in that, said the 3rd transistor and the 4th transistor are in the forward service area by said second bias voltage control.

4. capacity multiplier according to claim 1 is characterized in that, the emitter region area of said transistor seconds be the first transistor the emitter region area N doubly;

The said the 4th transistorized emitter region area is N a times of the 3rd transistorized emitter region area; Said N is an integer.

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