CN102832210B - 低阻衬底上的多表面集成器件 - Google Patents

低阻衬底上的多表面集成器件 Download PDF

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CN102832210B
CN102832210B CN201210313791.4A CN201210313791A CN102832210B CN 102832210 B CN102832210 B CN 102832210B CN 201210313791 A CN201210313791 A CN 201210313791A CN 102832210 B CN102832210 B CN 102832210B
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substrate
conductive component
ohm
resistance value
methods
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CN102832210A (zh
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王若楠
刘燕
何松
王婷婷
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Hong Kong Applied Science and Technology Research Institute ASTRI
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Abstract

本发明涉及其部分置于多个衬底表面上的器件。该器件包括一低阻衬底，其有第一和第二表面，第一导电器件部件置于第一表面上。中间隔电层置于导电部件和低阻衬底之间。第二导电部件置于低阻衬底的第二表面上。在低阻衬底上形成的一个空腔被至少部分地填入一高阻材料。在高阻材料内形成一个或多个导电路线，电连接第一导电部件和第二导电部件，以形成一个器件。示例性的器件包括电感器、电容器、天线、和有源或无源器件。使用该器件可以形成垂直集成的器件***。

Description

低阻衬底上的多表面集成器件
【技术领域】
本发明是关于其器件部分在多个衬底表面上的电子器件，特别涉及包括高品质（高Q因子）集成无源器件在低阻衬底上的电子器件，而且低阻衬底包含高阻材料。
【背景技术】
因为集成电路(IC)在尺寸上越来越小，在功能上越来越多，所以越来越多的器件和越来越高性能的器件就为IC空间带来激烈竞争。集成无源器件（IPD）是集成电路中一种重要的器件，特别是无线网络上的通讯器件。由于一些器件诸如电感器的性能是和器件尺寸相关联的（例如在衬底上的金属线路总长度），因此需要找到新的方式去提高性能但不增加器件的“占地面积”（即是在和其他电子元件共用的衬底上占据的空间量）。
【发明内容】
本发明涉及一个低阻衬底上的器件，其器件部分置于至少两个衬底表面上。示例性的低阻衬底的电阻值大约在0.1欧姆-厘米到10欧姆-厘米，如低阻硅。示例性的器件包括集成无源器件，如电感器、电容器、和天线或其组合；也包括和一个或多个这些器件集成在一起的有源器件。这些器件部分置于衬底的上表面或下表面上，并通过衬底上的导电线路电连接。
特别地，本发明涉及的器件位于电阻值大约在0.1欧姆-厘米到10欧姆-厘米的低阻衬底上。示例性的低阻衬底是非金属的，如半导体和某些低阻/半导体/部分导电陶瓷或聚合物，其有第一和第二表面，第一导电部件置于低阻衬底的第一表面上。在导电部件和低阻衬底之间可以有中间隔电层。第二导电部件置于低阻衬底的第二表面上，之间可选地有中间隔电层。在低阻衬底上形成一空腔，并至少部分地填入一高阻材料，电连接第一导电部件和第二导电部件，形成一个或多个集成无源器件。
【附图说明】
图1描述本发明器件的一个实施例。
图2是图1器件的截面图。
图3A-3E显示形成图2器件的过程。
图4A-4B显示本发明形成的电感器的Q因子的提高。
图5A-5B显示本发明形成的电感器的感应系数的提高。
图6A-6D显示本发明的应用。
图7显示本发明形成的有源器件/无源器件组合。
【具体实施方式】
详细参见附图，图1显示本发明器件100的一个实施例。在该显示的示例性实施例中，器件100是一个集成无源器件如电感器，其有第一线圈110和第二线圈120置于低阻衬底130（为清晰起见，未在图1中显示）上。但是，根据本发明以下的教导，可以制作其他无源和有源器件的组合。
传导路线140提供线圈110和线圈120之间的电连接。如在此使用的，表述“低阻”是指那些传导率/电阻率大约是0.1欧姆-厘米到10欧姆-厘米的材料。这些材料通常是半导体或低阻陶瓷或聚合物。请注意大部分纯金属和金属合金都比上述范围有更低的电阻率，不能用作低阻衬底。
图2是图1中器件的侧视图，比图1显示更多细节。在图2中，第一组成部分如第一电感器线圈110嵌入在隔离材料115之中，其在低阻衬底130之上。隔离材料115可以是电阻材料或其他聚合物材料。在一个典型实施例中，低阻衬底130是低阻硅，当然也可以使用其他材料。有利地，硅可以用CMOS兼容处理技术来处理，但是，并不需要一定使用CMOS兼容技术。
介于电感线圈110和衬底130之间的是高阻材料117，其为电感器和衬底提供隔离。在一个特别实施例中，层117选自高阻聚合物，如BCB（联苯并环丁烯），其有高介电常数。有利地，BCB可以做成光敏的，因此可以使用光刻技术来图案化。通过图案化，对金属化层118可以形成开孔（如为以后形成的焊盘/端点）。在隔离层115的表面上，形成焊盘119以允许器件100和其它器件互连。MIM（金属-绝缘体-金属）电容器116置于部件113上。
在衬底130上形成一空腔160，并填入高阻材料150。通过将在电感线圈110和120区域内的一部分低阻材料130换成高阻材料150，最后器件的Q因子（品质因子）会大大提高。一个示例的高阻材料是聚酰亚胺或SU-8（一种环氧基光阻）。电感线圈120以及焊盘形成在高阻材料上。
为了允许电感线圈110和120互连形成单个、双表面的电感器，形成一个或多个通孔140A。也可以形成另一类型的通孔140B，其与焊盘一起连接到其它器件或集成电路上。
钝化层170形成在第二部分电感线圈120上。可以选择阻焊材料作为钝化层，或者选择使用在电子制造领域已知的其他钝化材料。可图案化的钝化材料就特别合适。
图3A-3E描述本发明形成双表面器件的过程。有利地，在这些图里显示的该方法和CMOS制程技术相兼容，因此形成的器件可以很容易与CMOS器件以及基于CMOS的集成电路集成在一起。在图3A中，在低阻硅衬底130上涂敷第一可图案化的隔离材料层117。在该第一可图案化的隔离材料层117上图案化出孔118，以允许形成焊盘。在此实施例中，隔离材料是光敏BCB。在第一可图案化的隔离材料层117上建立第一金属层，然后图案化形成焊盘122和互连或者集成无源器件（IPDs andinterconnect）110。在此实施例中，该金属是铜。在第一金属层上沉积第二可图案化的隔离材料层115。在第二可图案化的隔离材料层115上图案化出孔121，以允许形成焊盘。然后在第二可图案化的隔离材料层115上建立第二金属层，然后图案化形成焊盘119，其可选地用于焊线连接（wire-bonding）或其他电子连接技术。
在图3B中，一处理衬底200连接在图3A的结构上。因为处理衬底200不会是最终器件结构的一部分，所以可以选择任何与该制程技术兼容且具有足够强健性以促进该制程的材料。示例性的材料包括硅、玻璃、
氧化铝和其他陶瓷等等。在连接处理衬底后，典型地通过化学、机械、或化学机械抛光过程，将低阻衬底材料130薄型化。后者过程就特别适合由低阻硅做成的衬底。衬底130的最后厚度大概在100微米左右。
在图3C中，在衬底130上形成空腔160，然后在后续的过程中填入电阻材料和通孔材料。对于低阻硅衬底130来说，图案化可以由传统的光刻技术来实施，空腔160可以由TMAH（氢氧化四甲铵，一种非等向性蚀刻剂）湿蚀刻来实现。
在图3D中，通常是通过旋转涂布，往空腔160内填入高阻聚合物150。示例性的聚合物包括聚酰亚胺和SU-8。对于那些还包含电连接通孔的空腔，使用光刻技术或其他合适的图案化技术来确定通孔位置，除
去不需要的聚合物而建立通孔142。尽管在图3D中仅显示了一个通孔，但是在此过程中可以建立多个通孔，如图2中最终器件所示。有利地，在聚合物材料150种形成通孔，要比形成硅通孔（TSV）更容易，因为聚合物更容易图案化和去除。
为了形成传导路径，在通孔142中沉积铜，以形成通孔140B。随后使用金属化，以形成其他焊盘220和器件元件/电感线圈120。然后应用钝化材料170以保护器件的第二部分120。示例性的钝化材料可以是防焊膜材料（solder mask material），它能很容易图案化。最后，除去处理衬底，得到最终的双表面器件。
图4A和4B显示对于一个单侧的电感器通过将一部分低阻衬底替换为高阻聚合物而提高Q因子和感应系数。图5A和5B显示在低阻衬底上嵌入高阻材料的双侧电感器的感应系数增加。两组图都是在ISM带宽（在2.4GHz范围）上测量感应系数，许多无线网络都是在该带宽上运行。
图6A-6D显示本发明的多表面器件的各种应用。在图6A中，电感器由元件110和120形成。器件背部的焊球230可以连接到一个母板。在图6B中，焊线焊盘119支持线250用于连接到由公用衬底/母板支撑的其它器件上。在图6C中，多个器件可以通过由焊球230电连接而垂直集成。这些器件都是无源或有源器件，取决于形成的整个电子结构。在图6D中，焊线焊盘119用于连接到表面安装设备（SMD）280。芯片290也是通过焊盘和焊线和器件100互连。这些例子不是限制性的，仅显示了一部分应用，在其中本发明的器件可以和其他部件和集成电路集成在一起。
图7显示本发明器件的另一个应用。在图7中，放大器500和本发明形成的器件100（如电容器和/或电感器）互连。因此本发明适用于有源和无源器件。
请注意器件之间的连接可以是串联或并联，器件可以一起或单独使用。有源和/或无源器件可以垂直集成堆叠。
虽然已经通过各种实施里描述了本发明，但是这些实施例不是限制性的。本领与普通技术人员可以理解各种变化和变更。这些变化和变更将包含在所附权利要求的范围内。

Claims (18)

1.一种器件，其至少一个部件位于多个衬底表面中的一个表面上，该器件包括：
第一衬底，其电阻值在0.1欧姆-厘米到10欧姆-厘米，其有至少第一和第二表面；
第一导电部件，其置于所述第一衬底的第一表面上，其与所述第一表面之间可以有中间隔电层，也可以没有；
第二导电部件，其置于所述第一衬底的第二表面上，；
一空腔，其形成在所述第一衬底上；
第二材料，其电阻值要高于所述第一衬底的电阻值，其被至少部分地填入所述第一衬底的空腔内；
一个或多个导电线路，其形成在所述第二材料内，其电连接所述第一导电部件和所述第二导电部件以形成该器件；
其中所述第一导电部件和所述第二导电部件包括无源的线圈，所述第一导电部件的线圈嵌入在隔离材料之中，并位于所述第二材料之上，所述隔离材料位于所述第一衬底之上。
2.如权利要求1所述的器件，其中所述器件包括电感器。
3.如权利要求1所述的器件，其中所述器件包括电容器。
4.如权利要求1所述的器件，其中所述器件包括天线。
5.如权利要求1所述的器件，还包括集成在一起的第二器件。
6.如权利要求5所述的器件，其中所述器件和所述第二器件串联或并联。
7.如权利要求5所述的器件，其中所述器件和所述第二器件是分开单独使用的。
8.如权利要求1所述的器件，其中所述第二材料的电阻值等于或高于10的12次方欧姆-厘米，低于10的16次方欧姆-厘米。
9.一种垂直集成器件堆叠，包括权利要求1所述的器件。
10.如权利要求9所述的垂直集成器件堆叠，其中所述器件堆叠包括有源器件。
11.一种器件形成方法，其中至少一个部件位于多个衬底表面中的一个表面上，该方法包括：
提供第一衬底，其电阻值在0.1欧姆-厘米到10欧姆-厘米，其有至少第一和第二表面；
形成第一导电部件并将其置于所述第一衬底的第一表面上，其与所述第一表面之间可以有中间隔电层，也可以没有；
形成第二导电部件并其置于所述第一衬底的第二表面上，；
去除一部分所述第一衬底；
将第二材料填入所述第一衬底的所述去除部分，所述第二材料的电阻值要高于所述第一衬底的电阻值；
形成通孔穿过所述第二材料，在所述通孔内形成传导线路，连接到一个或多个第一和第二焊盘；
在所述第二材料内形成一个或多个导电线路，其电连接所述第一导电部件和所述第二导电部件以形成该器件；
其中所述第一导电部件和所述第二导电部件包括无源的线圈，所述第一导电部件的线圈嵌入在隔离材料之中，并位于所述第二材料之上，所述隔离材料位于所述第一衬底之上。
12.如权利要求11所述的方法，其中所述器件是一个集成的无源器件。
13.如权利要求12所述的方法，其中所述集成的无源器件选自一个或多个电感器、电容器、或天线。
14.如权利要求11所述的方法，还包括：在所述第一衬底的第一表面上或第二表面下垂直地集成另一个器件。
15.如权利要求14所述的方法，其中所述另一个器件选自有源或无源器件。
16.如权利要求11所述的方法，其中所述第一衬底是硅。
17.如权利要求11所述的方法，其中所述第二材料是高阻聚合物。
18.如权利要求11所述的方法，其中所述第二材料的电阻值等于或高于10的12次方欧姆-厘米，低于10的16次方欧姆-厘米。
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