CN102818637B

CN102818637B - CTIA (Capacitive Transimpedance Amplifier) structure input stage applicable to readout circuit of IRFPA (Infrared Focus Plane Arrray)

Info

Publication number: CN102818637B
Application number: CN201210273980.3A
Authority: CN
Inventors: 王攀; 陈国强; 高磊; 丁瑞军; 叶振华; 周杰
Original assignee: Shanghai Institute of Technical Physics of CAS
Current assignee: Shanghai Institute of Technical Physics of CAS
Priority date: 2012-08-03
Filing date: 2012-08-03
Publication date: 2014-06-04
Anticipated expiration: 2032-08-03
Also published as: CN102818637A

Abstract

The invention discloses a CTIA (Capacitive Transimpedance Amplifier) structure input stage for collecting and processing weak signals of an IRFPA (Infrared Focus Plane Arrray), relating to an input stage of the CTIA structure operationally amplified by a current source-loaded cascode structure. Operational amplification of the CTIA structure is composed of M1, M2 and M3 CMOS (Complementary Metal Oxide Semiconductors) transistors; three transistors are of current source-loaded cascode structures; the M1 transistor is a current source load; the M2 transistor and the M3 transistor are of cascode structures. An Auxiliary voltage offset module is composed of 6 CMOS transistors (M4-M9) and is used for providing an offset voltage for the operational amplification. M4, M7, M8 and M9 CMOS transistors form a current mirror; M5 and M6 CMOS transistors are of diode connection structures; a reference current flows from an IBIA end; the offset voltage is given to M1 and M2 CMOS transistors by the current mirror. The CTIA structure achieve compromise of area, performance and power consumption, and provides a solution of a readout circuit for the IRFPA with a large area array, a small pixel and a weak signal.

Description

The CTIA structure input stage that short-wave infrared detector array row reading circuit is applicable

Technical field

The present invention relates to mixed-Signal integrate Circuit technology, be specifically related to the applicable CTIA structure input stage of a kind of short-wave infrared detector array row reading circuit, it reads integrated circuit for the high frame frequency with photoelectric weak signal function of short-wave infrared detector array (Infrared Focus Plane Array-IRFPA) system, can realize integration, sampling, amplification and the output of the low light level response signal of short-wave infrared detector.

Background technology

Infrared detector array is the core devices in infrared imaging system.Infrared detector array is generally made up of two parts: infrared detector array and sensing circuit.Infrared eye is receiving after the infrared radiation of incident, produces a photocurrent relevant to incident infrared radiation property, is transferred to corresponding sensing circuit unit.Tradition sensing circuit will carry out integration, amplification, sampling and maintenance to these electric signal, then be cushioned with multiplex system and finally read with analog signal form by output, form image by rear end electronic system.

High performance short-wave infrared detector has that pixel face battle array is large, cellar area is little, photo-signal is faint, output frame frequency high.The loss sensitivity that large face battle array is transmitted on concentric line signal; The less complexity that limits cellular construction of cellar area; Detector photo-signal less (0.1-1pA magnitude), the integration of itself gathers difficulty; High frame frequency application integral time is limited makes the saturation charge on sampling capacitance less than normal; Because signal is little, the nonlinearity that noise is introduced can be very large; Under high frame frequency duty, the data that small-signal obtains loss meeting in transmitting procedure is relatively very large.

Conventional infrared eye sensing circuit is generally divided into unit, is listed as three parts of public, public output stage.In cellular construction, there are the conventional input stage structures such as CTIA, BDI, DI available.Be listed as public be generally one-level sample circuit by a column unit structure sharing, public output stage generally adopt source class follower as output driving be a ranks common structure share.Conventional CTIA structure input stage is all fine in the performance of injection efficiency, noise, but existing complex structure is difficult to realize in limited area.General row common structure is difficult to reach the requirement aspect dynamic range, squelch.The output stage of common source class follower can not meet frame frequency.

Summary of the invention

The invention provides the applicable CTIA structure input stage of a kind of short-wave infrared detector array row reading circuit, it is that the high frame frequency that having in a kind of short-wave infrared detector array system gathers weak signal function is read integrated circuit, after its low light level electric signal integration to short-wave infrared detector, sampling, amplification, export, further strengthen the signal handling capacity of short-wave infrared detector sensing circuit, to promote its development in large face battle array, high resolving power, multispectral direction.The present invention solve problem mainly: the high-level efficiency collection of weak signal; The inhibition of low-frequency noise; Out-put dynamic range expands; The raising of sensing circuit working frame frequency.

The object of the invention is to realize by following technological approaches:

The present invention adopts standard C SMC-6S05DPTM0.5um CMOS integrated circuit technology, at EDA(Electronic Design Automation electric design automation) build circuit in design platform, mainly realize the integration to detector photosignal, correlated-double-sampling, the electric charge amplitude of oscillation is amplified and output.Every grade of node of model configuration is all considered common wire's stray capacitance, has done enough buffer stages and has guaranteed to drive.In row utility module, adopt CDS correlated-double-sampling to eliminate more serious low-frequency noise in sensing circuit.In row utility module, adopt charge amplifier, can will after linear the signal after integration amplification, give final output.Adopt suitable buffering buffer structure to reduce the loss in transmission.On when output stage adopts the symmetrical amplifier structure of complementary type to improve output, push away and pull-down capability.

The present invention has 2 innovations: 1. improved conventional CTIA structure, the cascode structure amplifier that has designed current source load has substituted the excessive telescopic OPAMP of conventional area.The critical nature such as injection efficiency of input stage but also can overcome the excessive shortcoming of original structure area in not only can bonding meta structure.2. the signal link of pair sensing circuit designs, in cellular construction, adopt the CTIA structure input stage described in 1, in row utility module, configured correlated-double-sampling structure and row electric charge structure for amplifying solves respectively noise and dynamic range problem, public output stage structure adopts complementary type export structure to improve output frame frequency.

Technical scheme:

1) sensing circuit pre-amplification circuit adopts electric capacity transimpedance amplifier (CTIA), and this circuit module is responsible for that detector photo-signal is read in to circuit and integration is enlarged into voltage signal.Then cushion, amplify, the voltage signal that the logical circuit in engagement tabs obtains pixel integration reads to offer analog to digital conversion circuit by multiplexing emulation bus according to a certain order.CTIA structure has very high injection efficiency, and integrating capacitor is equivalent to very large electric capacity of input end by Miller effect, obtains most marking currents thereby can shunt, and injection efficiency is higher than 90%.Due to the restriction of area, the CTIA structure in this design can not adopt telescopic or collapsible so complicated multitube structure, and the cascode structure amplifier of current source load can provide enough gains relatively to save again area.Well meet designing requirement.

In accompanying drawing 3, have schematic diagram and the cellular construction figure of CTIA structure, wherein middle M1, M2 of figure (a), tri-metal-oxide-semiconductors of M3 have formed the amplifier of CTIA structure, between Vin and Vout, place integrating capacitor.Three cascode structure that pipe is current source load, M1 pipe is current source load, M2, M3 are cascode structure.This amplifier is the FAMP module of the CTIA structure in figure (b).M4～M9 pipe provides the bias voltage of work for this amplifier.M4, M7, M8, M9 form respectively current mirror, and M5, M6 are diode syndeton, and reference current is flowed into by IBIA end, gives M1, M2 through current mirror by bias voltage.M4, M7 have identical breadth length ratio with M1, and M5 has identical breadth length ratio with M2, and M6, M8, M9 have identical breadth length ratio with M3.For saving area, M4～M9 is placed in row utility module.In right figure, TG is transfer tube, and SF is source class follower, is all common structures.

2) sensing circuit has very serious low-frequency noise impact, as KTC noise, 1/f noise and array noise.In accompanying drawing 4, for the correlated-double-sampling CDS in the present invention, can well reduce the impact of low-frequency noise, the CDS has here selected more rational structure, to meet the requirement of high frame frequency, does not substantially affect work schedule simultaneously.In a signals transmission, just can complete double sampling and subtract each other direct output.And can change the range of signal of exporting by adjusting reference voltage Vcds.S1, S2 closure when on sampling capacitance, signal is effective, S3 disconnects, and A, 2 of B are clamped to respectively Vin1 and Vcds.After clamper completes, S2 disconnects, and the electric charge of the right pole plate of B point C1 does not have path to shift, and is fixed on B point, has just kept the voltage difference delta V=V of C1 electric capacity yet _b1-V _a1=V _cDS-V _in1.S3 closure afterwards, reset C2 electric capacity, A point is pulled down to the initial Vin0 on sampling capacitance, and now B point voltage can be followed and be dropped to V _b2=V _a2+ Δ V=V _cDS+ (V _in0-V _in1), this signal is the value after twice signal subtraction.

3) major function of charge amplifier is to improve dynamic range, will after the amplification of the signal linearity of prime, offer output stage.This grade main considers the linearity, driving force and power consumption to rear class.Concrete structure in accompanying drawing 5, S1, S3 closure when prime signal is effective, S2 disconnects, C1 sampling, C2 resets.Sampled rear S1, S3 disconnects, S2 closure, and it is upper that the electric charge on C1 is transferred to C2, and signal is amplified in the output of Vout end.The amplitude of oscillation is with V _blascentered by threshold voltage of the each loss of bound, threshold value 1.1V～4V, input threshold is also 1.1V～4V.The ratio that designs C1, C2 is carried out the ratio that control signal amplitude is amplified.Its operating voltage range also can be controlled by adjusting reference voltage Vbias.

4) public output stage is the buffer stage of the public last Pad of driving of multichannel.Its serviceability directly has influence on the output frame frequency of circuit.The unity gain amplifier pull-down capability of considering NMOS pipe composition is more weak, on draw ability more intense, otherwise PMOS manage, formed the output stage structure of complementary type in conjunction with both advantages.Be the work of NMOS amplifier at high signal, when low signal, the work of PMOS amplifier, so just can provide good driving force.

5) signal is transferred to the public structure of rear class complete integration and sampling in CTIA construction module after.In row utility module, adopt CDS correlated-double-sampling structure, eliminate more serious low frequency in sensing circuit and make an uproar

The workflow of whole signal chains is such, and the detector array of short-wave infrared detector starts in sensing circuit upper integral after short-wave infrared signal is converted into faint current signal.CTIA structure is by photo-signal integration, and integration completes post-sampling in sampling capacitance, passes to afterwards the correlated-double-sampling structure in row common structure.Correlated-double-sampling structure is done to signal the result that double sampling subtracts each other and is passed to same charge amplifier in row common structure.Charge amplifier will output to rear class after linear prime signal voltage amplification.The signal that complementary type output stage in public output stage is come charge amplifier outputs in last bus successively.

The invention has the advantages that:

1) the CTIA structure of unit has well realized the compromise of area, performance, power consumption, for the short-wave infrared detector device of large face battle array, little pixel, weak signal provides a kind of solution route of sensing circuit.Area 20um × 20um～200um × 200um, power consumption 0.5uW～2uW, injection efficiency is more than 95%.

2) integrated CDS correlated-double-sampling structure in analog signal link, the low-frequency noise that elimination infrared eye sensing circuit is more serious.For short-wave infrared detector device provides technical support in application such as high resolving power.

3) doing good design improving aspect output voltage swing, charge amplifier amplifies the linearity of signal swing and the coordination of signal working ranges at different levels, can significantly improve the dynamic range (2V～4V) of short-wave infrared detector device.

Accompanying drawing explanation

Fig. 1 is whole circuit function module workflow diagram.UGA is unity gain amplifier, and TG is transmission gate, and SF is that source is with structure.

Fig. 2 is 5 pipe unity gain amplifier structures (UGA) general in link.In correlated-double-sampling, charge amplifier and signal path, be useful.

Fig. 3 is the CTIA structure pre-amplification circuit figure that adopts cascode structure (M1, M2, the M3) amplifier of current source load.M4～M9, for amplifier provides bias voltage, is placed in row common structure.Figure a is amplifier and the additional bias structure of CTIA structure, and figure b is the CTIA structural entity schematic diagram in unit.

Fig. 4 is correlated-double-sampling structure, and CDS structure can effectively suppress low-frequency noise, so particularly the noise of cellular construction is placed on greatly row common level.

Fig. 5 is charge amplifier structure.

Embodiment

1) sensing circuit pre-amplification circuit adopts CTIA structure, and inside comprises M1, M2, M3 and integrating capacitor, sampling capacitance.Size is definite voluntarily as required, and recommending breadth length ratio is 1/10,1/5,1/10.

2) unity gain amplifier comprise M1～M5, recommended size is 10/1,10/1,20/1,20/1,20/1.

3) clamp voltage V in correlated-double-sampling structure _cDSget 4～5V, C1 gets 1～2p.

4) in the structure of charge amplifier, C1 is 1pF, and C2 can get 0.4～2pF by magnification ratio.

5) complementary output level structure P-UGA N-UGA all adopt the structure of unity gain amplifier in Fig. 2, recommending breadth length ratio is 200/1,200/1,400/1,400/1,400/1.

The application design proposal of the amplifier CTIA structure of the analog signal link in this invention and the cascode structure of current source load in infrared shortwave detector sensing circuit is rational, feasible.

Claims

1. the CTIA structure input stage for acquisition and processing short-wave infrared detector array weak signal, it is made up of CTIA structure and the boosting voltage biasing module of the cascode structure amplifier of current source load, it is characterized in that: described CTIA structure has been made up of the amplifier of CTIA structure M1, M2, tri-CMOS pipes of M3, the cascode structure that M1, M2, tri-CMOS pipes of M3 are current source load, M1 pipe is current source load, and M2 and M3 are cascode structure; Described boosting voltage biasing module is made up of 6 CMOS pipe M4～M9, for the amplifier of CTIA structure provides the bias voltage of work; M4, M7, M8, M9 form respectively current mirror, and M5 and M6 are diode syndeton, and reference current is flowed into by IBIA end, gives M1, M2 through current mirror by bias voltage.