CN102790655B - Device and method for achieving Turbo coding - Google Patents
Device and method for achieving Turbo coding Download PDFInfo
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- CN102790655B CN102790655B CN201110132522.3A CN201110132522A CN102790655B CN 102790655 B CN102790655 B CN 102790655B CN 201110132522 A CN201110132522 A CN 201110132522A CN 102790655 B CN102790655 B CN 102790655B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0064—Concatenated codes
- H04L1/0066—Parallel concatenated codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0041—Arrangements at the transmitter end
- H04L1/0043—Realisations of complexity reduction techniques, e.g. use of look-up tables
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Abstract
The invention discloses a device and a method for achieving Turbo coding. The device comprises a code block data storage module, an inner mixed processing module and a coding module, wherein the code block data storage module is used for receiving code block data and caching the received code block data alternatively into a ping-pong random access memory (RAM); the inner mixed processing module is used for receiving parameters K representing sizes of the code block data and computing and reading read addresses required by the inner mixed processing of the code block data in a stream-line mode based on the received parameters K; and the coding module is used for reading the code block data in a stream-line mode from the code block data storage module based on the read addresses required by the inner mixed processing, coding the read code block data and then outputting the processed code block data. According to the device and the method for achieving the Turbo coding, processing efficiency of the Turbo coding is improved through the stream-line mode.
Description
Technical field
The present invention relates to communication technical field, particularly relate to a kind of apparatus and method realizing Turbo coding.
Background technology
Turbo coding is widely used assembly in a communications system.Two simple component codes be there is the long code of pseudo-random characteristics by Turbo coding dexterously by pseudo random interleaver parallel cascade, and by two soft enter/softly go out to carry out successive ignition between (SISO) decoder to achieve pseudorandom decoding.Its object is to utilize possible additional control code to reset the information that will send, in this approach, worsen the effect that information source deleteriously affects transmission, can by being compensated in the method for decoder-side complementary decoding.The performance of Turbo coding has very large advantage relative to other coded system.
Current Turbo is coded in 3-G (Generation Three mobile communication system) UMTS 3GPP25212 agreement and is well used.Turbo coding is one and connects convolution code (PCCC), and it is made up of 8 state subgroup encoders and a Turbo code interleaver.The code rate of Turbo code is 1/3.For and the transfer function connecting 8 state subgroup encoders of convolution code (PCCC) be:
wherein: g
0(D)=1+D2+D3; g
1(D)=1+D+D3;
When starting coding input bit, and the initial value connecting the shift register of convolution code (PCCC) encoder will be 0 entirely.
The structure of Turbo encoder as shown in Figure 1.
The output of Turbo encoder: x
1, z
1, z '
1, x
2, z
2, z '
2... .., x
k, z
k, z '
k, wherein, x
1, x
2...., x
kbe be input to the bit of Turbo encoder as first 8 state encoder and Turbo code interleaver, K is bit number; And z
1, z
2...., z
kand z
1', z
2' ...., z
k' be output bit from first and second 8 state subgroup encoders respectively.
The bit of Turbo code interleaver exports and can be expressed as x
1', x
2' ...., x
k', these outputs can be input to second 8 state subgroup encoder.
Turbo coding is applied in the radio communication of various standard at present just widely.At present, in Turbo encoder, the generation of interleaving address mainly concentrates on storage and the calculating of UMTS Turbo encoder interleaving address, computational methods are mainly used in software DSP (Digital Signal Processing, Digital Signal Processing) in, for high speed processing business, speed can not meet corresponding requirement.
Summary of the invention
The invention provides a kind of apparatus and method realizing Turbo coding, the problem of high speed processing business can not be met in order to solve Turbo code rate in prior art.
In order to solve the problems of the technologies described above, the present invention adopts technical scheme as follows:
On the one hand, the invention provides a kind of device realizing Turbo coding, comprising:
Code block data memory module, for received code blocks of data, and is alternately buffered in each code block data received in table tennis random access memory ram;
Interior interleaving treatment module, for receiving the parameter K of presentation code blocks of data size, based on each parameter K received, streamline calculate read interior interleaving treatment needed for each described code block data read address;
Coding module, for reading address based on described interior interleaving treatment, in described code block data memory module, streamline reads code block data, exports after carrying out coded treatment to the code block data read.
Wherein, described interior interleaving treatment module specifically comprises:
Parameter acquisition module, for according to the parameter K received, obtains interior interleaving treatment desired parameters;
Interior interleaving block, for the parameter obtained according to described parameter acquisition module, goes interior, in the ranks interleaving treatment;
Address acquisition module, for the interleaving treatment result according to described interior interleaving block, the address of reading obtaining interior interleaving treatment is T (i) * C+U
t (i)(j);
Wherein, U
t (i)(j) for be expert at interior, in the ranks the position of i capable jth column data bit in original matrix of interleaver matrix is T (i) row U after interleaving treatment
t (i)j () arranges; T (i) is the pattern that in the ranks interweaves; C is the columns of interleaver matrix.
Wherein, described parameter acquisition module specifically comprises:
First parameter acquiring submodule, for according to described parameter K, searches pre-configured coding parameter table, directly obtains line number R, the columns C of interleaver matrix, prime number p and prime number primitive root v;
Second parameter acquiring submodule, for according to described prime number p and prime number primitive root v, calculates intertexture basic sequence S in row;
3rd parameter acquiring submodule, for according to described prime number p, calculates least prime sequence q, and changes sequence to described q sequence and obtain changing sequence Prime sequences r.
Further, described second parameter acquiring submodule, according to described prime number p and prime number primitive root v, in conjunction with S sequence criteria algorithm, calculates described S sequence by iterative manner.
Further, described 3rd parameter acquiring submodule, according to described prime number p, searches the pre-configured ROM recording prime number p and q serial correlation relation and shows, obtain the least prime sequence q corresponding with described prime number p.
Further, device of the present invention also comprises:
Table configuration module, for the span according to the K specified in standard agreement, the R value that coupling is corresponding, is normalized to K/R by unified for K/R
x, and by K/R
xbe converted to multiplying, utilize the K/R after computing
xwith p+1 comparison, determine p value, and based on the incidence relation of p and prime number primitive root v and interleaver matrix columns C, obtain v and C that described p value is corresponding, the coding parameter table that to generate with described K be index; Wherein, described R
xvalue is 5,10 or 20.
Further, in device of the present invention, described coding module, the initial address also for storing based on each code block data, in described code block data memory module, streamline reads each code block data, exports after carrying out coded treatment to each code block data.
On the other hand, the present invention also provides a kind of method realizing Turbo coding, comprising:
Received code blocks of data, and each code block data received alternately is buffered in table tennis random access memory ram;
Receive the parameter K of presentation code blocks of data size, based on each parameter K received, streamline calculate read interior interleaving treatment needed for each code block data read address;
Read address based on described interior interleaving treatment, streamline reads the code block data stored, and exports after carrying out coded treatment to the code block data read.
Wherein, the parameter K of described reception presentation code blocks of data size, based on each parameter K received, the address of reading that streamline calculates the interior interleaving treatment read needed for each code block data specifically comprises:
According to the parameter K received, interleaving treatment desired parameters in obtaining;
According to the described interior interleaving treatment desired parameters of acquisition, go interior, in the ranks interleaving treatment;
According in described row, in the ranks interleaving treatment result, the address of reading obtaining interior interleaving treatment is T (i) * C+U
t (i)(j); Wherein, U
t (i)(j) for be expert at interior, in the ranks the position of i capable jth column data bit in original matrix of interleaver matrix is T (i) row U after interleaving treatment
t (i)j () arranges; T (i) is the pattern that in the ranks interweaves; C is the columns of interleaver matrix.
Wherein, the described parameter K according to receiving, in obtaining, interleaving treatment desired parameters specifically comprises:
According to described parameter K, search pre-configured coding parameter table, directly obtain line number R, the columns C of interleaver matrix, prime number p and prime number primitive root v;
According to described prime number p and prime number primitive root v, calculate S sequence;
According to described prime number p, calculate least prime sequence q, and sequence is changed to described q sequence obtain changing sequence Prime sequences r.
Further, described according to prime number p and prime number primitive root v, calculate S sequence, specifically comprise: according to described prime number p and prime number primitive root v, in conjunction with S sequence criteria algorithm, calculate described S sequence by iterative manner;
Described according to prime number p, calculate least prime sequence q, specifically comprise: according to described prime number p, search the pre-configured ROM recording prime number p and q serial correlation relation and show, obtain the least prime sequence q corresponding with described prime number p.
Further, the method for the invention also comprises: the initial address stored based on each code block data, and in described code block data memory module, streamline reads each code block data, exports after carrying out coded treatment to each code block data.
Beneficial effect of the present invention is as follows:
Method and apparatus provided by the invention, by pipeline system, improves the treatment effeciency of Turbo coding;
The method of the invention and device, also adopt the mode of tabling look-up to calculate line number R, the columns C of interleaver matrix, prime P and prime number primitive root v fast; Have employed the method for iteration, calculate S sequence fast, and utilize the method for tabling look-up to calculate q sequence, what obtain interleaving treatment fast reads address, further increases Turbo coded treatment efficiency.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the structure chart of Turbo encoder in prior art;
The structure drawing of device realizing Turbo coding that Fig. 2 provides for the embodiment of the present invention one;
The structure drawing of device realizing Turbo coding that Fig. 3 provides for the embodiment of the present invention two;
Fig. 4 is coding parameter table manufacture method flow chart in the embodiment of the present invention two;
Fig. 5 is the method flow diagram realizing Turbo coding provided by the invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
The problem of high speed business process can not be met to solve Turbo coded treatment speed in prior art, the invention provides a kind of apparatus and method realizing Turbo coding, adopt digital logic arrangement can realize the process of Turbo encoding pipeline very well, be mainly used at present in the symbol level coding of 3G (Third Generation) Moblie UMTS.Further, by flexible configuration code block data size parameter K, the method for the invention and device are also applicable in the Turbo encoder of other wireless communication fields.
Provide the several preferred embodiment of the present invention according to Fig. 2 ~ Fig. 5 below, and combine the description to embodiment, provide ins and outs of the present invention further.
Embodiment one
As shown in Figure 2, the embodiment of the present invention provides a kind of device realizing Turbo coding, comprising:
Code block data memory module 21, for received code blocks of data, and is alternately buffered in ping-pong ram (random access memory) by each code block data received;
Interior interleaving treatment module 22, for receiving the parameter K of presentation code blocks of data size, based on each parameter K received, streamline calculate read interior interleaving treatment needed for each code block data read address;
Coding module 23, for reading address based on each interior interleaving treatment, in code block data memory module 21, streamline reads each code block data, exports after carrying out coded treatment to the code block data read.
In the embodiment of the present invention, interior interleaving treatment module 22 comprises further:
Parameter acquisition module 221, for the parameter K according to reception, interleaving treatment desired parameters in obtaining, this parameter comprises: intertexture basic sequence S, least prime sequence q and change sequence Prime sequences r in line number R, the columns C of interleaver matrix, prime number p, prime number primitive root v, row;
Interior interleaving block 222, for the parameter obtained according to parameter acquisition module 221, goes interior, in the ranks interleaving treatment;
Address acquisition module 223, for according to interior interleaving block 222 interleaving treatment result, the address of reading obtaining interior interleaving treatment is T (i) * C+U
t (i)(j); Wherein, U
t (i)(j) for be expert at interior, in the ranks the position of i capable jth column data bit in original matrix of interleaver matrix is T (i) row U after interleaving treatment
t (i)j () arranges; T (i) is the pattern that in the ranks interweaves; C is the columns of interleaver matrix.
Wherein, the associative operation that described parameter acquisition module 221, interior interleaving block 222 carry out can carry out relevant treatment according to 3GPP25212 agreement.
Further, in the embodiment of the present invention, after described interior interleaving treatment module 22 receives the parameter K of presentation code blocks of data size, preferably, the each parameter K received continuously is alternately buffered in the ping-pong ram in this module, and based on the parameter K of buffer memory in ping-pong ram, streamline calculate read interior interleaving treatment needed for each code block data read address.
Further, in the embodiment of the present invention, described coding module 23, the initial address also for storing based on each code block data, in code block data memory module 21, streamline reads each code block data, exports after carrying out coded treatment to each code block data.
Specifically, in the embodiment of the present invention, coding module 23 only can carry out coded treatment to the encoding block after intertexture, also namely directly can encode to the code block data of non-interleaving treatment, also encode to the code block data after intertexture.It may occur to persons skilled in the art that, when coding module in the embodiment of the present invention 23 is only encoded to the encoding block after intertexture, the coding for the original code block data of non-interleaving treatment can be undertaken by stipulated form in standard; When coding module in the embodiment of the present invention 23 is encoded respectively to the coded data before and after interweaving, obtain manner for the coded data of non-interleaving treatment can be multiple, such as can directly obtain in data source, certainly, more preferably obtain in code block data memory module 21, when obtaining in code block data memory module 21, can read with the storage initial address of code block data order.Process is read for this order, illustrates as follows:
The present invention, in order to realize streamline coded treatment, have employed ping-pong ram memory encoding blocks of data, supposes to there is code block data 1,2 ..., N, when by each code block data stored in ping-pong ram time, alternately store in turn.And when encoding, according to the storage order of code block data, first from the RAM of ping-pong ram, read address respectively according to the initial address (i.e. code block data store initial address) of this RAM and interleaving treatment, read out two-way code block data and carry out coded treatment, after coding completes, be switched in another RAM again, read two-way code block data according to same mode to encode, carry out in turn, until all code block data have been encoded.
In sum, the device that the embodiment of the present invention provides, data and parameter store and all adopt ping-pong ram structure, may realize the switching between encoding block flexibly, realize the stream treatment of Turbo encoding block.
Embodiment two
As shown in Figure 3, the embodiment of the present invention also provides a kind of device realizing Turbo coding, comprising: code block data memory module 31, interior interleaving treatment module 32, coding module 33;
Further, described interior interleaving treatment module 32 specifically comprises: parameter acquisition module 321, interior interleaving block 322, address acquisition module 323.
The function of above-mentioned each functional module is identical with embodiment one, does not repeat at this;
In the embodiment of the present invention, described parameter acquisition module 321 comprises further:
First parameter acquiring submodule 3211, for according to parameter K, searches pre-configured coding parameter table, directly obtains line number R, the columns C of interleaver matrix, prime number p and prime number primitive root v;
Second parameter acquiring submodule 3212, for according to described prime number p and prime number primitive root v, calculates intertexture basic sequence S sequence in row;
3rd parameter acquiring submodule 3213, for according to described prime number p, calculates least prime sequence q; And sequence is changed to described q sequence obtain changing sequence Prime sequences r.
Wherein, be loaded into after described pre-configured coding parameter table can configure outside device in the device described in the embodiment of the present invention, call for parameter acquisition module; Also can set up a table configuration module in embodiment of the present invention, for configuration codes parameter list, record in this coding parameter table associate one by one with each K value line number R, columns C, prime number p and prime number primitive root v parameter.
Wherein, described table configuration module, specifically for the span according to the K specified in standard agreement, the R value that coupling is corresponding, is normalized to K/R by unified for K/R
x, and by K/R
xbe converted to multiplying, utilize the K/R after computing
xwith p+1 comparison, determine p value, and based on the incidence relation of p and prime number primitive root v and interleaver matrix columns C, obtain v and C that described p value is corresponding, the coding parameter table that to generate with described K be index; Wherein, described R
xvalue is 5,10 or 20.
In order to clearer statement the present invention, in the present embodiment, the table layoutprocedure of building of described coding parameter table is described in detail:
As shown in Figure 4, table-form making method is as follows:
Step S401, each span according to the K specified in 3GPP25212 agreement, obtain interleaver matrix line number R; Described R is 5,10,20 according to the scope value of K.
Step S402, according to K/R≤p+1, determine the value of prime number p;
In this step, in order to realize the quick calculating of K/R, preferably, be K/5 by primary system one normalization of K/R (only retaining a division); : K*8192/5 and K*1638 moves to right 12bit more again the division arithmetic of K/5 to be converted into multiplying, can obtain K/R.
In this step, because the value of R is fixed, namely 5,10,20, when so K/10 and K/20 being normalized, have: K/10 is converted into K/5 and moves to right 1 bit again; K/20 is converted into K/5 and moves to right 2 bits again.
The p that step S403, utilization obtain, searches p-v contingency table, obtains prime number primitive root v corresponding with it;
Step S404, utilize the relational expression of 3GPP25212 agreement midrange C and K, R, p, obtain interleaver matrix columns C.
Step S405, by above-mentioned parameter, take K as compilation of index form.
For the embodiment of the present invention, after interior interleaving treatment module 32 gets parms K, search coding parameter table based on this parameter K, directly get parms R, C, p, v, greatly improves treatment effeciency.
After obtaining parameter R, C, p, v, for S sequence, q sequence and r sequence, then can obtain according to specified standard algorithm in standard agreement further.
In sum, device described in the embodiment of the present invention, adds the treatment effeciency of Turbo coding by streamline and the mode of tabling look-up.
Embodiment three
Continue as shown in Figure 3, the embodiment of the present invention also provides a kind of device realizing Turbo coding fast, comprising: code block data memory module 31, interior interleaving treatment module 32, coding module 33;
Further, described interior interleaving treatment module 32 specifically comprises: parameter acquisition module 321, interior interleaving block 322, address acquisition module 323.The function of above-mentioned each functional module is identical with embodiment one, does not repeat at this;
In the embodiment of the present invention, described parameter acquisition module 321 comprises further:
First parameter acquiring submodule 3211, for according to parameter K, searches pre-configured coding parameter table, directly obtains line number R, the columns C of interleaver matrix, prime number p and prime number primitive root v;
Second parameter acquiring submodule 3212, according to described prime number p and prime number primitive root v, in conjunction with S sequence criteria algorithm, calculates described S sequence by iterative manner.
Wherein, calculate described S sequence by iterative manner to be specially:
For S sequence, its computing formula is s (j)=[v × s (j-1)] mod p, j=1,2 ..., (p-2), s (0)=1;
From 3GPP25212 agreement, known prime number primitive root v value has: 2,3,5,6,7,19 6 kind may, when according to above-mentioned formulae discovery S sequence, according to the different values of v, can following iteration be carried out:
After obtaining v according to lookup table mode:
If during v=2, S sequence can be obtained by 2 v=1 iteration;
If during v=3, first can calculate the S sequence that v=2 is corresponding, then the S corresponding with v=1 carries out iteration, obtain final S sequence;
If during v=5, first can calculate the S sequence that v=2 is corresponding, then calculate S sequence corresponding to v=3 according to the S sequence that v=2 obtains, the S sequence that v=2 and v=3 obtains be carried out iteration, obtains final S sequence;
If during v=6, first can calculate the S sequence that v=2 is corresponding, then calculate S sequence corresponding to v=3 according to the S sequence that v=2 obtains, iteration be carried out to the S sequence of two v=3, obtains the S sequence that v=6 is corresponding;
The rest may be inferred, during for v=7 and 19, all obtains S sequence by iterative manner, can improve computational efficiency greatly.
3rd parameter acquiring submodule 3213, for according to described prime number p, calculates least prime sequence q; And sequence is changed to described q sequence obtain changing sequence Prime sequences r.
Preferably, the 3rd parameter acquiring submodule 3213 obtains least prime sequence q in the following way;
3rd parameter acquiring submodule 3213, according to described prime number p, searches the pre-configured ROM recording prime number p and q serial correlation relation and shows, obtain the least prime sequence q corresponding with described prime number p.
Concrete, specify in 3GPP25212 agreement: q
i, i=0,1 ..., (R-1), wherein q
0=1, q
i> 6, q
i> q
i-1and g.c.d [q
i, p-1]=1;
Known by 3GPP25212 agreement known p sequence, so in the embodiment of the present invention, to each P value in p sequence, determine corresponding optional q sequence data in advance.Due to maximum 21 data of q sequence, so be made into 1 ROM table in the present invention, be 256 by a degree of depth, bit wide is that the ROM of 21 bits stores.
In sum, the device that the embodiment of the present invention provides, by pipeline system, adds the treatment effeciency of Turbo coding; And adopt the mode of tabling look-up to calculate line number R, the columns C of interleaver matrix, prime P and prime number primitive root v fast; Have employed the method for iteration, calculate S sequence fast, and utilize the method for tabling look-up to calculate q sequence, accelerate and calculate the processing speed that interleaving treatment reads address, and then add Turbo coded treatment efficiency.
As shown in Figure 5, the present invention also provides a kind of method realizing Turbo coding, comprising:
Step S501, received code blocks of data, and each code block data received alternately is buffered in table tennis random access memory ram;
Step S502, receive the parameter K of presentation code blocks of data size, based on each parameter K received, streamline calculate read interior interleaving treatment needed for each code block data read address;
Step S503, read address based on described interior interleaving treatment, streamline reads the code block data stored, and exports after carrying out coded treatment to the code block data read.
Preferably, described step S503 is also based on the initial address that each code block data stores, and in described code block data memory module, streamline reads each code block data, exports after carrying out coded treatment to each code block data.
Particularly, this cataloged procedure can be encoded to two-way code block data, when specific implementation, can be realized by two encoders, such as two encoders are respectively encoder 1 and encoder 2, code block data is directly read for encoder 1 encode, export after obtaining the first parity bits; Address reading code block data is read for interleaving treatment within encoder 2 encode, export after obtaining the second parity bits;
In the present invention, in order to realize streamline coded treatment, have employed ping-pong ram memory encoding blocks of data, supposing to there is code block data 1,2 ..., N, when by each code block data stored in ping-pong ram time, alternately store in turn.And when encoding, according to the storage order of code block data, read after two-way code block data carries out coded treatment from a RAM, be switched in another RAM and read, carry out in turn, until all code block data have been encoded.
Further, in the method for the invention, described step S502 specifically comprises:
(1) according to the parameter K received, interleaving treatment desired parameters in obtaining;
(2) according to the described interior interleaving treatment desired parameters obtained, interior, in the ranks interleaving treatment is gone;
(3) according in described row, in the ranks interleaving treatment result, the address of reading obtaining interior interleaving treatment is T (i) * C+U
t (i)(j); Wherein, U
t (i)(j) for be expert at interior, in the ranks the position of i capable jth column data bit in original matrix of interleaver matrix is T (i) row U after interleaving treatment
t (i)j () arranges; T (i) is the pattern that in the ranks interweaves; C is the columns of interleaver matrix.
Preferably, above-mentioned steps (1) can be realized by following manner:
(11) according to parameter K, search pre-configured coding parameter table, directly obtain line number R, the columns C of interleaver matrix, prime number p and prime number primitive root v;
(12) according to described prime number p and prime number primitive root v, S sequence is calculated;
(13) according to described prime number p, least prime sequence q is calculated;
(14) change sequence to described q sequence to obtain changing sequence Prime sequences r.
Preferably, above-mentioned steps (12) can be realized by following manner: according to described prime number p and prime number primitive root v, in conjunction with S sequence criteria algorithm, calculate described S sequence by iterative manner;
Preferably, above-mentioned steps (13) can be realized by following manner: according to described prime number p, searches the pre-configured ROM recording prime number p and q serial correlation relation and shows, obtain the least prime sequence q corresponding with described prime number p.
In sum, the method of the invention optimizes efficient implementation method for Turbo coding provides a kind of, realize based on Digital Logic completely, adopt the pipeline design, by the fast zoom table of parameter, iteration, calculate interleaving address for getting etc. to read fast, effectively raise processing speed, and favorable expandability, be applicable to the Turbo coding of various wireless communication field.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. realize a device for Turbo coding, it is characterized in that, comprising:
Table configuration module, for the span of the parameter K according to the presentation code blocks of data size specified in standard agreement, the interleaver matrix line number R value that coupling is corresponding, is normalized to K/R by unified for K/R
x, and by K/R
xbe converted to multiplying, utilize the K/R after computing
xwith p+1 comparison, determine prime number p value, and based on the incidence relation of p and prime number primitive root v and interleaver matrix columns C, obtain v and C that described p value is corresponding, the coding parameter table that to generate with described K be index; Wherein, described R
xvalue is 5,10 or 20;
Code block data memory module, for received code blocks of data, and is alternately buffered in each code block data received in table tennis random access memory ram;
Interior interleaving treatment module, for receiving the parameter K of presentation code blocks of data size, search described coding parameter table based on each parameter K received, get parms R, C, p, v, and based on each parameter streamline obtained calculate read interleaving treatment in needed for each described code block data read address;
Coding module, for reading address based on described interior interleaving treatment, in described code block data memory module, streamline reads code block data, exports after carrying out coded treatment to the code block data read.
2. device as claimed in claim 1, it is characterized in that, described interior interleaving treatment module specifically comprises:
Parameter acquisition module, for according to the parameter K received, obtains interior interleaving treatment desired parameters;
Interior interleaving block, for the parameter obtained according to described parameter acquisition module, goes interior, in the ranks interleaving treatment;
Address acquisition module, for the interleaving treatment result according to described interior interleaving block, the address of reading obtaining interior interleaving treatment is T (i) * C+U
t (i)(j);
Wherein, U
t (i)(j) for be expert at interior, in the ranks the position of i capable jth column data bit in original matrix of interleaver matrix is T (i) row U after interleaving treatment
t (i)j () arranges; T (i) is the pattern that in the ranks interweaves; C is the columns of interleaver matrix.
3. device as claimed in claim 2, it is characterized in that, described parameter acquisition module specifically comprises:
First parameter acquiring submodule, for according to described parameter K, searches described coding parameter table, directly obtains line number R, the columns C of interleaver matrix, prime number p and prime number primitive root v;
Second parameter acquiring submodule, for according to described prime number p and prime number primitive root v, calculates intertexture basic sequence S in row;
3rd parameter acquiring submodule, for according to described prime number p, calculates least prime sequence q, and changes sequence to described q sequence and obtain changing sequence Prime sequences r.
4. device as claimed in claim 3, is characterized in that,
Described second parameter acquiring submodule, according to described prime number p and prime number primitive root v, in conjunction with S sequence criteria algorithm, calculates described S sequence by iterative manner; And/or,
Described 3rd parameter acquiring submodule, according to described prime number p, searches the pre-configured ROM recording prime number p and q serial correlation relation and shows, obtain the least prime sequence q corresponding with described prime number p.
5. device as claimed in claim 1, is characterized in that,
Described coding module, the initial address also for storing based on each code block data, in described code block data memory module, streamline reads each code block data, exports after carrying out coded treatment to each code block data.
6. realize a method for Turbo coding, it is characterized in that, comprising:
Received code blocks of data, and each code block data received alternately is buffered in table tennis random access memory ram;
Receive the parameter K of presentation code blocks of data size, search coding parameter table based on each parameter K received, get parms R, C, p, v, and based on each parameter streamline obtained calculate read interleaving treatment in needed for each code block data read address; Wherein, the configuration mode of described coding parameter table is: according to the span of the parameter K of the presentation code blocks of data size specified in standard agreement, the interleaver matrix line number R value that coupling is corresponding, is normalized to K/R by unified for K/R
x, and by K/R
xbe converted to multiplying, utilize the K/R after computing
xwith p+1 comparison, determine prime number p value, and based on the incidence relation of p and prime number primitive root v and interleaver matrix columns C, obtain v and C that described p value is corresponding, the coding parameter table that to generate with described K be index; Wherein, described R
xvalue is 5,10 or 20;
Read address based on described interior interleaving treatment, streamline reads the code block data stored, and exports after carrying out coded treatment to the code block data read.
7. method as claimed in claim 6, is characterized in that, the parameter K of described reception presentation code blocks of data size, and based on each parameter K received, the address of reading that streamline calculates the interior interleaving treatment read needed for each code block data specifically comprises:
According to the parameter K received, interleaving treatment desired parameters in obtaining;
According to the described interior interleaving treatment desired parameters of acquisition, go interior, in the ranks interleaving treatment;
According in described row, in the ranks interleaving treatment result, the address of reading obtaining interior interleaving treatment is T (i) * C+U
t (i)(j); Wherein, U
t (i)(j) for be expert at interior, in the ranks the position of i capable jth column data bit in original matrix of interleaver matrix is T (i) row U after interleaving treatment
t (i)j () arranges; T (i) is the pattern that in the ranks interweaves; C is the columns of interleaver matrix.
8. method as claimed in claim 7, is characterized in that, the described parameter K according to receiving, and in obtaining, interleaving treatment desired parameters specifically comprises:
According to described parameter K, search described coding parameter table, directly obtain line number R, the columns C of interleaver matrix, prime number p and prime number primitive root v;
According to described prime number p and prime number primitive root v, calculate S sequence;
According to described prime number p, calculate least prime sequence q, and sequence is changed to described q sequence obtain changing sequence Prime sequences r.
9. method as claimed in claim 8, is characterized in that,
Described according to prime number p and prime number primitive root v, calculate S sequence, specifically comprise: according to described prime number p and prime number primitive root v, in conjunction with S sequence criteria algorithm, calculate described S sequence by iterative manner;
Described according to prime number p, calculate least prime sequence q, specifically comprise: according to described prime number p, search the pre-configured ROM recording prime number p and q serial correlation relation and show, obtain the least prime sequence q corresponding with described prime number p.
10. method as claimed in claim 6, it is characterized in that, described method also comprises:
Based on the initial address that each code block data stores, in described code block data memory module, streamline reads each code block data, exports after carrying out coded treatment to each code block data.
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| CN201110132522.3A CN102790655B (en) | 2011-05-20 | 2011-05-20 | Device and method for achieving Turbo coding |
| PCT/CN2011/080231 WO2012159401A1 (en) | 2011-05-20 | 2011-09-27 | Turbo coding device and method |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7051261B1 (en) * | 2002-10-29 | 2006-05-23 | Lattice Semiconductor Corporation | Turbo encoder with reduced processing delay |
| CN101043284A (en) * | 2007-04-10 | 2007-09-26 | 中兴通讯股份有限公司 | Interleaver of TURBO coder in WCDMA system |
| CN101964692A (en) * | 2009-07-21 | 2011-02-02 | 中兴通讯股份有限公司 | Long term evolution (LTE)-based TURBO coding method and system |
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2011
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- 2011-09-27 WO PCT/CN2011/080231 patent/WO2012159401A1/en active Application Filing
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7051261B1 (en) * | 2002-10-29 | 2006-05-23 | Lattice Semiconductor Corporation | Turbo encoder with reduced processing delay |
| CN101043284A (en) * | 2007-04-10 | 2007-09-26 | 中兴通讯股份有限公司 | Interleaver of TURBO coder in WCDMA system |
| CN101964692A (en) * | 2009-07-21 | 2011-02-02 | 中兴通讯股份有限公司 | Long term evolution (LTE)-based TURBO coding method and system |
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| WO2012159401A1 (en) | 2012-11-29 |
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