CN102201818B - A kind of output intent of Turbo decode results and device - Google Patents
A kind of output intent of Turbo decode results and device Download PDFInfo
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- CN102201818B CN102201818B CN201110122720.1A CN201110122720A CN102201818B CN 102201818 B CN102201818 B CN 102201818B CN 201110122720 A CN201110122720 A CN 201110122720A CN 102201818 B CN102201818 B CN 102201818B
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- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
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Abstract
The invention provides a kind of output intent and device of Turbo decode results, described method comprises: read in parallel shift register by the Turbo decode results stored in units of code block CB; According to the relevant information of described CB, select the tap position of parallel shift register, carry out data splicing; Control the output of splicing result.The output intent of a kind of Turbo decode results provided by the invention and device, the parallel processing to Turbo decode results is achieved by parallel shift register and data splicing control module, can low cost, realize the output of Turbo decode results expeditiously, have that storage overhead is low, processing delay is little and process the features such as simple, improve system processing power, be beneficial to the reduction of cost.
Description
Technical field
The present invention relates to the decoding treatment technology of communication, particularly relate to a kind of output intent and device of Turbo decode results.
Background technology
Two simple component codes be there is the long code of pseudo-random characteristics by Turbo code dexterously by pseudo random interleaver parallel cascade, the performance of Turbo code, considerably beyond other coded systems, is therefore more and more paid close attention to and develops.But, the process more complicated of Turbo decoding, so the throughput in order to improve Turbo decoding, adopt field programmable gate array (FieldProgrammableGateArray in baseband system more, FPGA) or application-specific integrated circuit (ASIC) (ApplicationSpecificIntegratedCircuit, ASIC) carried out Turbo decoding process.
According to third generation partner program (The3rdGenerationPartnershipProject, 3GPP) specify in TS25.212 and TS25.222, as a transmission block (TransportBlock, TB) when length is greater than 5114bit, need to carry out code block (CodeBlock to this TB, CB) split, CB size after segmentation can be the arbitrary value between 40bit ~ 5114bit, and usually add dummy argument in the front end of first CB, to make the size of each CB completely equal.Size due to CB is the arbitrary value between 40bit ~ 5114bit, and additional dummy argument number also has arbitrariness, so the size of the actual valid data of CB is more any equally.
After Turbo decoding, process to obtain actual valid data if do not carry out, and when directly data being outputted to External memory equipment, then decode results is being transferred to central processing unit (CentralProcessingUnit by External memory equipment, or digital signal processing chip (DigitalSignalProcessor CPU), when DSP) carrying out rear class process, CPU or DSP is when using these data, carrying out data access process with regard to needing for the bit position of actual valid data in input data, so can increase intractability.
Here, when no matter CPU or DSP reads and writes data from External memory equipment, all process with least unit, specifically can be different according to the difference of system; Wherein, described least unit is Word, and its width w is respectively 8,16 or 32, can be designated as Word8, Word16 or Word32 respectively.In view of the foregoing, need, when Turbo decoding exports decode results, to complete the Word splicing of CB, to improve the treatment effeciency of total system.
Existingly complete in Word splicing, a kind of conventional method arranges first-in first-out (FirstInFirstOut, FIFO), each CB decode results is sequentially written in FIFO, during output, according to the size of dummy argument number and CB, then order takes out wbit from FIFO at every turn, completes Word splicing.But the method needs to use FIFO, adds storage overhead, realizes cost higher; And can only by bit serial process, process time delay is comparatively large, and efficiency is lower.
Summary of the invention
In view of this, main purpose of the present invention is the output intent and the device that provide a kind of Turbo decode results, can low cost, realize the output of Turbo decode results expeditiously.
For achieving the above object, technical scheme of the present invention is achieved in that
An output intent for Turbo decode results, described method comprises:
The Turbo decode results stored in units of code block CB is read in parallel shift register;
According to the relevant information of described CB, select the tap position of parallel shift register, carry out data splicing;
Control the output of splicing result.
Wherein, the described Turbo decode results stored in units of CB being read in parallel shift register is:
Read first Word of described CB, be input in the first order register of described parallel shift register; Wherein, the width w of described Word is 8,16 or 32;
Read the next Word of described CB, be input in the first order register of described parallel shift register, the former data parallel be stored in first order register is displaced in the second level register of described parallel shift register meanwhile.
Wherein, the described relevant information according to described CB, the tap position of selection parallel shift register is:
When described CB is first CB of Turbo decode results, then the tap position of parallel shift register is selected to be the bitn ~ bit (w-1) of the second level register of parallel shift register and the bit0 ~ bit (n-1) of first order register; Wherein, n is the dummy argument number of described CB;
When described CB is not first CB of Turbo decode results, then according to CB index and the CB size of described CB, obtain the figure place m of the valid data that a CB does not also export, the tap position selecting parallel shift register is bit (the w-m) ~ bit (w-1) of second level register and the bit0 ~ bit (w-m-1) of first order register.
Wherein, carry out data described in be spliced into: the data that the bit0 ~ bit (n-1) splicing the bitn ~ bit (w-1) and first order register that the wbit data that obtain are followed successively by second level register from low bit to higher bit position stores; Or,
The data that the bit0 ~ bit (w-m-1) splicing the wbit data that obtain are followed successively by second level register bit (w-m) ~ bit (w-1) and first order register from low bit to higher bit position stores.
Further, described method also comprises:
Judge whether the figure place of splicing valid data in the data that obtain is w;
If the figure place of described valid data is not w, then whether the CB judging further when pre-treatment is last CB of Turbo decode results.
Wherein, the described output controlling splicing result is:
If when the figure place of valid data is w in the data that described splicing obtains, export described splicing result to external cache;
If the figure place of valid data is not w in the data that described splicing obtains, and when the CB of pre-treatment is last CB, after described valid data, mends 0 or 1, after gathering together enough wbit, export external cache to;
If the figure place of valid data is not w in the data that described splicing obtains, and when the CB of pre-treatment is not last CB, the data that described splicing obtains are moved, described valid data are moved to right to low order end, and be written back into the first order register of parallel shift register, then read first Word of next CB.
An output device for Turbo decode results, described device comprises: input selection module, parallel shift register, data splicing control module, output select module; Wherein,
Input selection module, for reading in described parallel shift register by the Turbo stored in units of CB decode results;
Data splicing control module, for the relevant information according to described CB, selects the tap position of described parallel shift register, carries out data splicing;
Export and select module, for controlling the output of splicing result.
Further, described input selection module, specifically for reading first Word of described CB, is input in the first order register of described parallel shift register; Read the next Word of described CB, be input in described first order register, meanwhile, the former data parallel be stored in described first order register is displaced in the second level register of described parallel shift register; Wherein, the width w of described Word is 8,16 or 32.
Further, described data splicing control module, during specifically for being first CB of Turbo decode results as described CB, then the tap position of parallel shift register is selected to be the bitn ~ bit (w-1) of the second level register of parallel shift register and the bit0 ~ bit (n-1) of first order register; Wherein, n is the dummy argument number of described CB; When described CB is not first CB of Turbo decode results, then according to CB index and the CB size of described CB, obtain the figure place m of the valid data that a CB does not also export, the tap position selecting parallel shift register is bit (the w-m) ~ bit (w-1) of second level register and the bit0 ~ bit (w-m-1) of first order register.
Further, the data that bit0 ~ bit (n-1) that described data splicing control module splices the bitn ~ bit (w-1) and first order register that the wbit data that obtain are followed successively by second level register from low bit to higher bit position stores; Or the data that the bit0 ~ bit (w-m-1) of bit (the w-m) ~ bit (w-1) and first order register that are followed successively by second level register stores.
Further, described data splicing control module, also for judging to splice whether the figure place of valid data in the data that obtain is w; If the figure place of described valid data is not w, then whether the CB judging further when pre-treatment is last CB of Turbo decode results.
Further, module is selected in described output, if when the figure place of valid data is w in the data obtained specifically for described splicing, export described splicing result to external cache; If the figure place of valid data is not w in the data that described splicing obtains, and when the CB of pre-treatment is last CB, after described valid data, mends 0 or 1, after gathering together enough wbit, export external cache to; If the figure place of valid data is not w in the data that described splicing obtains, and when the CB of pre-treatment is not last CB, the data that described splicing obtains are moved, described valid data are moved to right to low order end, and be written back into the first order register of parallel shift register, then read first Word of next CB.
The output intent of a kind of Turbo decode results provided by the invention and device, the parallel processing to Turbo decode results is realized by parallel shift register and data splicing control module, so, can low cost, realize the output of Turbo decode results expeditiously, have that storage overhead is low, processing delay is little and process the features such as simple, and then can system processing power be improved, be beneficial to the reduction of cost.
Accompanying drawing explanation
Fig. 1 is the realization flow schematic diagram of the output intent of Turbo decode results of the present invention;
Fig. 2 is the schematic diagram of the inner buffer form of Turbo decode results and the external cache form of expectation in output intent one specific embodiment of Turbo decode results of the present invention;
Fig. 3 is the realization flow schematic diagram of a specific embodiment of the output intent of the Turbo decode results shown in Fig. 2;
Fig. 4 is input to the schematic diagram of register for first Word of first CB in the Turbo decode results shown in Fig. 2;
Fig. 5 is input to the schematic diagram of register for second Word of first CB in the Turbo decode results shown in Fig. 2;
Last Word that Fig. 6 is first CB in the Turbo decode results shown in Fig. 2 is input to the schematic diagram of register;
The schematic diagram of register during the write-back process that Fig. 7 is last Word of first CB in the Turbo decode results shown in Fig. 2;
Fig. 8 is input to the schematic diagram of register for first Word of second CB in the Turbo decode results shown in Fig. 2;
Fig. 9 is the system configuration schematic diagram using Turbo decode results output device of the present invention;
Figure 10 is the structural representation of Turbo decode results output device of the present invention.
Embodiment
Basic thought of the present invention is: read in parallel shift register by the Turbo decode results stored in units of code block CB; According to the relevant information of described CB, select the tap position of parallel shift register, carry out data splicing; Control the output of splicing result; Wherein, the relevant information of described CB can be one or more in the dummy argument number of described CB, CB index, CB size.
For making the object, technical solutions and advantages of the present invention clearly understand, by the following examples also with reference to accompanying drawing, the present invention is described in more detail.
Fig. 1 shows the realization flow of the output intent of Turbo decode results of the present invention, and as shown in Figure 1, described method comprises the steps:
Step 101, reads in parallel shift register by the Turbo decode results of carrying out storing in units of CB;
In this step, described parallel shift register can be the parallel shift register of 8bit, 16bit, 32bit; Particularly, first Word of a CB of this Turbo decode results is read from the inner buffer storing described Turbo decode results, be input in the first order register of this parallel shift register, and then read next Word, be input in the first order register of parallel shift register, the former data parallel be stored in first order register is displaced in the register of the second level; Wherein, the width w of described Word can be also 8,16 or 32, is designated as Word8, Word16 or Word32 respectively;
Step 102, according to the relevant information of above-mentioned CB, selects the tap position of parallel shift register, carries out data splicing;
Particularly, in this step, can according to the dummy argument number of described CB, CB index, CB size isoparametric one or more, carry out the selection of tap position; When described CB is first CB of Turbo decode results, then the tap position of parallel shift register is selected to be the bitn ~ bit (w-1) of the second level register of parallel shift register and the bit0 ~ bit (n-1) of first order register; Wherein, n is dummy argument number;
When described CB is not first CB of Turbo decode results, then according to CB index and CB size, obtain the figure place m of the valid data that a CB does not also export, the tap position selecting parallel shift register is bit (the w-m) ~ bit (w-1) of second level register and the bit0 ~ bit (w-m-1) of first order register; Wherein: the data that the bit0 ~ bit (n-1) splicing the bitn ~ bit (w-1) and first order register that the wbit data that obtain are followed successively by second level register from low bit to higher bit position stores; Or, the data that the bit0 ~ bit (w-m-1) of bit (the w-m) ~ bit (w-1) and first order register that are followed successively by second level register stores.
Particularly, when w is 8, when CB is first CB of this Turbo decode results, may needs to fill dummy argument, ensure that the length of each CB of this Turbo decode results is identical; Such as, when the dummy argument number of first CB is 2, and the second level register of working as parallel shift register has inputted first 8bit data of this CB, when first order register has inputted second 8bit data of this CB, the data of the front two bit storage of second level register are the dummy argument of above-mentioned filling, not the valid data of Turbo decode results, therefore, the tap position needing the parallel shift register selected is the tap of rear six bit of second level register and the tap of first order register front two bit, and splicing obtains the data of a 8bit.
Step 103, controls the output of splicing result;
Here, the wbit data above-mentioned splicing obtained export external cache etc. to, then repeat above-mentioned steps, until take last group data of a CB, due to the integral multiple that CB not of uniform size is w surely, therefore also invalid data may be included in last group data;
Particularly, this step also comprises: judge whether the figure place of splicing valid data in the data that obtain is w; If the figure place of described valid data is not w, then whether the CB judging further when pre-treatment is last CB of Turbo decode results;
Correspondingly, if when the figure place of valid data is w in the data that obtain of described splicing, export described splicing result to external cache;
If the figure place of valid data is not w in the data that described splicing obtains, and when the CB of pre-treatment is last CB, can mend 0 or 1 after described valid data, after gathering together enough wbit, export external cache etc. to;
If the figure place of valid data is not w in the data that described splicing obtains, and when the CB of pre-treatment is not last CB, the data that described splicing obtains are moved, described valid data are moved to right to low order end, and be written back into the first order register of parallel shift register, then read first Word of next CB; Particularly, after being written back to first order register, now, step 102 is spliced the wbit data obtained and is invalid data, gives up, and then repeats step 101, reads first Word of next CB.
Fig. 2 shows the inner buffer form of Turbo decode results and the external cache form of expectation in output intent one specific embodiment of Turbo decode results of the present invention, for convenience of description, assuming that the maximum length of CB is 64bit in 3GPP, and supposition is 154bit when the length of the TB of pre-treatment, assuming that DSP/CPU system adopts Word width w to be 8, namely adopt Word8.According to CB separation algorithms, divide the CB obtained and add up to 3, the length of each CB is 52bit, the dummy argument of filling is 2bit, under these conditions, after Turbo decoding, the inner buffer form of three CB is as shown in the arrow left side in Fig. 2, and the external cache form that this Turbo decode results is expected is as shown on the right of arrow in Fig. 2; In Fig. 2, the rectangle frame of three shown in the arrow left side is followed successively by the hard decision result of first CB, second CB, the 3rd CB; Wherein, in the hard decision result of first CB, the front two of first 8bit data is the dummy argument of filling, and last four of each CB is the invalid data of polishing; The external cache form of the expectation shown on the right of arrow is the splicing result after left side CB removes invalid data.
Fig. 3 is the realization flow of the specific embodiment of the output intent to the Turbo decode results shown in Fig. 2, and in the present embodiment, the width w of Word is 8; As shown in Figure 3, described embodiment comprises the steps:
Step 301, reads first Word of first CB, stored in the first order register of parallel shift register;
Particularly, as shown in Figure 4, read the first order register of first 8bit data stored in parallel shift register of first CB, now, the second level register of this parallel shift register is not also stored in data.
Step 302, reads second Word of this CB, and stored in the first order register of this parallel shift register, now, in former first order register, the data shifts of buffer memory is in the register of the second level;
Particularly, as shown in Figure 5, read second 8bit data of first CB, be input in the first order register of parallel shift register, the former data parallel be stored in first order register is displaced in the register of the second level.
Step 303, according to the relevant information of this CB, as the tap position of the Selecting parameter first order registers such as dummy argument number, CB index, CB size and second level register, carries out data splicing;
Particularly, with reference to Fig. 5, because the data in bit0, bit1 position of second level register are the dummy argument of filling, therefore the tap position selected is the bit2 ~ bit7 of second level register and the bit0 ~ bit1 of first order register, carries out data splicing.
Step 304, exports external cache etc. to by splicing the 8bit data obtained;
Particularly, herein, the data exported after splicing are followed successively by the bit2 ~ bit7 of second level register from low bit to higher bit position, be then the bit0 ~ bit1 of first order register.
Step 305, read the next Word of this CB, stored in the first order register of this parallel shift register, now, in former first order register, the data shifts of buffer memory is in the register of the second level, and judges whether the figure place of splicing valid data in the Word obtained according to tap position in this step is 8, if, perform step 304, if not, then perform step 306;
Particularly, in last Word of first CB, the figure place of valid data is 4, less than 8, see Fig. 6, when last Word above-mentioned is input in first order register, the figure place of now splicing valid data in the Word obtained is still 8, therefore performs step 304, exporting external cache to by splicing the 8bit data obtained, then repeating this step;
It should be noted that, now wouldn't carry out the reading of the next Word of Turbo decode results, but by random 8bit data stored in first order register, data parallel in former first order register is displaced to second level register simultaneously, specifically can refer to Fig. 7, now splice the valid data containing 2bit in the 8bit data obtained, therefore perform step 306.
Step 306, whether the CB judging when pre-treatment is last CB of Turbo decode results, if so, then performs step 304, specifically can mend 0 or 1 after the valid data less than 8, export external cache to after gathering together enough 8bit; If not, then step 307 is performed;
Particularly, with reference to Fig. 7, when the CB of pre-treatment is not last CB of Turbo decode results, therefore perform step 307.
Step 307, the valid data in the 8bit data obtain splicing move to right to right-hand member, and be written back into first order register, in former first order register, the data shifts of buffer memory is in the register of the second level;
Particularly, see Fig. 7, by step 305, the valid data spliced in the 8bit data obtained are moved, and move to right to low order end, after utilizing random data completion to 8bit, are written back into first order register.
Step 308, reads first Word of next CB, and stored in first order register, the 8bit data shifts containing valid data in former first order register, in the register of the second level, then performs step 303, redefines tap position, carry out data splicing;
Particularly, see Fig. 8, after first Word of second CB is stored in first order register, now in the register of the second level, the position of bit6 ~ bit7 is that first CB remains 2 valid data do not exported, therefore now, the tap position determined is bit6 ~ 7 of second level register and bit0 ~ 5 of first order register, then repeats above-mentioned steps, until obtain the Turbo decode results of the external cache form as expectation shown on the right of Fig. 2 arrow.
Fig. 9 shows and uses the system configuration of Turbo decode results output device of the present invention to illustrate, as shown in Figure 9, described output device can be built in the Turbo decoding processing unit of ASIC/FPGA, it reads Turbo decode results from inner buffer, after output device process, export to exterior storage, be then supplied to CPU/DSP and use.
Figure 10 shows the structural representation of Turbo decode results output device of the present invention, and as shown in Figure 10, described output device comprises input selection module, parallel shift register, data splicing control module, exports and select module; Wherein, input selection module, for reading in described parallel shift register by the Turbo stored in units of CB decode results; Data splicing control module, for the relevant information according to described CB, selects the tap position of described parallel shift register, carries out data splicing; Export and select module, for controlling the output of splicing result.
Further, described parallel shift register comprises first order register and second level register.
Further, described input selection module, specifically for reading first Word of described CB, is input in the first order register of described parallel shift register; Read the next Word of described CB, be input in described first order register, meanwhile, the former data parallel be stored in described first order register is displaced in the second level register of described parallel shift register; Wherein, the width w of described Word is 8,16 or 32, is designated as Word8, Word16 or Word32 respectively.
Further, described data splicing control module, during specifically for being first CB of Turbo decode results as described CB, then the tap position of parallel shift register is selected to be the bitn ~ bit (w-1) of the second level register of parallel shift register and the bit0 ~ bit (n-1) of first order register; Wherein, n is the dummy argument number of described CB; When described CB is not first CB of Turbo decode results, then according to CB index and the CB size of described CB, obtain the figure place m of the valid data that a CB does not also export, the tap position selecting parallel shift register is bit (the w-m) ~ bit (w-1) of second level register and the bit0 ~ bit (w-m-1) of first order register.
Wherein, the data that bit0 ~ bit (n-1) that described data splicing control module splices the bitn ~ bit (w-1) and first order register that the wbit data that obtain are followed successively by second level register from low bit to higher bit position stores; Or the data that the bit0 ~ bit (w-m-1) of bit (the w-m) ~ bit (w-1) and first order register that are followed successively by second level register stores.
Further, described data splicing control module, also for judging to splice whether the figure place of valid data in the data that obtain is w; If the figure place of described valid data is not w, then whether the CB judging further when pre-treatment is last CB of Turbo decode results.
Further, module is selected in described output, if when the figure place of valid data is w in the data obtained specifically for described splicing, export described splicing result to external cache; If the figure place of valid data is not w in the data that described splicing obtains, and when the CB of pre-treatment is last CB, after described valid data, mends 0 or 1, after gathering together enough wbit, export external cache to; If the figure place of valid data is not w in the data that described splicing obtains, and when the CB of pre-treatment is not last CB, the data that described splicing obtains are moved, described valid data are moved to right to low order end, and be written back into the first order register of parallel shift register, then read first Word of next CB.
The above, be only preferred embodiment of the present invention, be not intended to limit protection scope of the present invention.
Claims (10)
1. an output intent for Turbo decode results, is characterized in that, described method comprises:
The Turbo decode results stored in units of code block CB is read in parallel shift register;
According to the relevant information of described code block CB, select the tap position of parallel shift register, carry out data splicing;
Control the output of splicing result;
The described output controlling splicing result is:
If when the figure place of valid data is w in the data that described splicing obtains, export described splicing result to external cache;
If the figure place of valid data is not w in the data that described splicing obtains, and when the CB of pre-treatment is last CB, after described valid data, mends 0 or 1, after gathering together enough wbit, export external cache to;
If the figure place of valid data is not w in the data that described splicing obtains, and when the CB of pre-treatment is not last CB, the data that described splicing obtains are moved, described valid data are moved to right to low order end, and be written back into the first order register of parallel shift register, then read first Word of next CB;
Wherein, the width w of Word is 8,16 or 32.
2. method according to claim 1, is characterized in that, the described Turbo decode results stored in units of code block CB being read in parallel shift register is:
Read first Word of described code block CB, be input in the first order register of described parallel shift register; Wherein, the width w of described Word is 8,16 or 32;
Read the next Word of described code block CB, be input in the first order register of described parallel shift register, the former data parallel be stored in first order register is displaced in the second level register of described parallel shift register meanwhile.
3. method according to claim 1 and 2, is characterized in that, the described relevant information according to described CB, and the tap position of selection parallel shift register is:
When described CB is first code block CB of Turbo decode results, then the tap position of parallel shift register is selected to be the bitn ~ bit (w-1) of the second level register of parallel shift register and the bit0 ~ bit (n-1) of first order register; Wherein, n is the dummy argument number of described CB;
When described CB is not first CB of Turbo decode results, then according to CB index and the CB size of described CB, obtain the figure place m of the valid data that a CB does not also export, the tap position selecting parallel shift register is bit (the w-m) ~ bit (w-1) of second level register and the bit0 ~ bit (w-m-1) of first order register.
4. method according to claim 3, it is characterized in that, described in carry out data and be spliced into: the data that the bit0 ~ bit (n-1) splicing the bitn ~ bit (w-1) and first order register that the wbit data that obtain are followed successively by second level register from low bit to higher bit position stores; Or,
The data that the bit0 ~ bit (w-m-1) splicing the wbit data that obtain are followed successively by second level register bit (w-m) ~ bit (w-1) and first order register from low bit to higher bit position stores;
Wherein, the width w of Word is 8,16 or 32.
5. method according to claim 1, is characterized in that, described method also comprises:
Judge whether the figure place of splicing valid data in the data that obtain is w;
If the figure place of described valid data is not w, then whether the code block CB judging further when pre-treatment is last code block CB of Turbo decode results;
Wherein, the width w of Word is 8,16 or 32.
6. an output device for Turbo decode results, is characterized in that, described device comprises: input selection module, parallel shift register, data splicing control module, output select module; Wherein,
Input selection module, for reading in described parallel shift register by the Turbo stored in units of code block CB decode results;
Data splicing control module, for the relevant information according to described code block CB, selects the tap position of described parallel shift register, carries out data splicing;
Export and select module, for controlling the output of splicing result;
Module is selected in described output, if when the figure place of valid data is w in the data obtained specifically for described splicing, export described splicing result to external cache; If the figure place of valid data is not w in the data that described splicing obtains, and when the code block CB of pre-treatment is last code block CB, after described valid data, mends 0 or 1, after gathering together enough wbit, export external cache to; If the figure place of valid data is not w in the data that described splicing obtains, and when the code block CB of pre-treatment is not last code block CB, the data that described splicing obtains are moved, described valid data are moved to right to low order end, and be written back into the first order register of parallel shift register, then read first Word of next code block CB;
Wherein, the width w of Word is 8,16 or 32.
7. device according to claim 6, is characterized in that, described input selection module, specifically for reading first Word of described code block CB, is input in the first order register of described parallel shift register; Read the next Word of described code block CB, be input in described first order register, meanwhile, the former data parallel be stored in described first order register is displaced in the second level register of described parallel shift register; Wherein, the width w of described Word is 8,16 or 32.
8. the device according to claim 6 or 7, it is characterized in that, described data splicing control module, specifically for when described code block CB is first code block CB of Turbo decode results, then the tap position of parallel shift register is selected to be the bitn ~ bit (w-1) of the second level register of parallel shift register and the bit0 ~ bit (n-1) of first order register; Wherein, n is the dummy argument number of described code block CB; When described code block CB is not first code block CB of Turbo decode results, then according to code block CB index and the code block CB size of described code block CB, obtain the figure place m of the valid data that a code block CB does not also export, the tap position selecting parallel shift register is bit (the w-m) ~ bit (w-1) of second level register and the bit0 ~ bit (w-m-1) of first order register;
Wherein, the width w of Word is 8,16 or 32.
9. device according to claim 8, it is characterized in that, the data that bit0 ~ bit (n-1) that described data splicing control module splices the bitn ~ bit (w-1) and first order register that the wbit data that obtain are followed successively by second level register from low bit to higher bit position stores; Or the data that the bit0 ~ bit (w-m-1) of bit (the w-m) ~ bit (w-1) and first order register that are followed successively by second level register stores;
Wherein, the width w of Word is 8,16 or 32.
10. device according to claim 6, is characterized in that, described data splicing control module, also for judging to splice whether the figure place of valid data in the data that obtain is w; If the figure place of described valid data is not w, then whether the code block CB judging further when pre-treatment is last code block CB of Turbo decode results;
Wherein, the width w of Word is 8,16 or 32.
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| CN101164242A (en) * | 2005-03-11 | 2008-04-16 | 高通股份有限公司 | Parallel turbo decoders with multiplexed output |
| CN101192833A (en) * | 2006-11-28 | 2008-06-04 | 华为技术有限公司 | A device and method for low-density checksum LDPC parallel coding |
| CN101957743A (en) * | 2010-10-12 | 2011-01-26 | 中国电子科技集团公司第三十八研究所 | Parallel digital signal processor |
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| CN101192833A (en) * | 2006-11-28 | 2008-06-04 | 华为技术有限公司 | A device and method for low-density checksum LDPC parallel coding |
| CN101957743A (en) * | 2010-10-12 | 2011-01-26 | 中国电子科技集团公司第三十八研究所 | Parallel digital signal processor |
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